July 2019 - U-Boot

[U-Boot] [PATCH 0/6] arm: socfpga: gen5: DM improvements
by Simon Goldschmidt 16 Aug '19

16 Aug '19

This series ports more ad-hoc code to DM drivers (reset, clk, timer). Simon Goldschmidt (6): ddr: socfpga: gen5: constify altera_gen5_sdram_ops arm: socfpga: gen5: increase SPL_SYS_MALLOC_F_LEN timer: dw-apb: add reset handling arm: socfpga: gen5: move initial reset handling to reset driver arm: socfpga: gen5: add readonly clk driver arm: socfpga: gen5: use DM_TIMER for systick MAINTAINERS | 1 + arch/arm/dts/socfpga-common-u-boot.dtsi | 78 ++++ arch/arm/dts/socfpga.dtsi | 5 + .../dts/socfpga_cyclone5_socrates-u-boot.dtsi | 1 + .../socfpga_cyclone5_socrates_handoff.dtsi | 26 ++ arch/arm/mach-socfpga/Kconfig | 7 +- arch/arm/mach-socfpga/Makefile | 1 - arch/arm/mach-socfpga/reset_manager_gen5.c | 13 - arch/arm/mach-socfpga/spl_gen5.c | 24 +- arch/arm/mach-socfpga/timer.c | 23 -- drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-gen5.c | 338 ++++++++++++++++++ drivers/ddr/altera/sdram_gen5.c | 2 +- drivers/timer/dw-apb-timer.c | 18 +- 14 files changed, 483 insertions(+), 55 deletions(-) create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi delete mode 100644 arch/arm/mach-socfpga/timer.c create mode 100644 drivers/clk/altera/clk-gen5.c -- 2.20.1

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[U-Boot] [PATCH v2] board: fsl: lx2160a: implement board_fix_fdt
by Pankaj Bansal 16 Aug '19

16 Aug '19

In lx2160a rev2 the pcie controller has been changed. Therefore, we need to change the device tree nodes of pcie controllers so that new controller can be probed. It involves changing the "compatible" field as well as registers names'. we are keeping same device tree for lx2160a rev1 and rev2, therefore we change the device tree nodes as part of fdt fixups. These changes would only be applied if the soc revision is not rev1. Signed-off-by: Pankaj Bansal <pankaj.bansal(a)nxp.com> --- Notes: V2: - explained the patch requirements and patch changes. board/freescale/lx2160a/lx2160a.c | 67 +++++++++++++++++++++++++++++ configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + 3 files changed, 69 insertions(+) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index addc829e5d..1182c4a1e6 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -20,6 +20,8 @@ #include <efi_loader.h> #include <asm/arch/mmu.h> #include <hwconfig.h> +#include <asm/arch/clock.h> +#include <asm/arch/config.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> #include "../common/qixis.h" @@ -108,6 +110,71 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_OF_BOARD_FIXUP +int board_fix_fdt(void *fdt) +{ + char *reg_names, *reg_name; + int names_len, old_name_len, new_name_len, remaining_names_len; + struct str_map { + char *old_str; + char *new_str; + } reg_names_map[] = { + { "ccsr", "dip" }, + { "pf_ctrl", "ctrl" } + }; + int off = -1, i; + + if (IS_SVR_REV(get_svr(), 1, 0)) + return 0; + + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie"); + while (off != -FDT_ERR_NOTFOUND) { + fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie", + strlen("fsl,ls-pcie") + 1); + + reg_names = fdt_getprop(fdt, off, "reg-names", &names_len); + if (!reg_names) + continue; + + reg_name = reg_names; + remaining_names_len = names_len - (reg_name - reg_names); + for (i = 0; (i < ARRAY_SIZE(reg_names_map)) && names_len; i++) { + old_name_len = strlen(reg_names_map[i].old_str); + new_name_len = strlen(reg_names_map[i].new_str); + if (memcmp(reg_name, reg_names_map[i].old_str, + old_name_len) == 0) { + /* first only leave required bytes for new_str + * and copy rest of the string after it + */ + memcpy(reg_name + new_name_len, + reg_name + old_name_len, + remaining_names_len - old_name_len); + /* Now copy new_str */ + memcpy(reg_name, reg_names_map[i].new_str, + new_name_len); + names_len -= old_name_len; + names_len += new_name_len; + } + + reg_name = memchr(reg_name, '\0', remaining_names_len); + if (!reg_name) + break; + + reg_name += 1; + + remaining_names_len = names_len - + (reg_name - reg_names); + } + + fdt_setprop(fdt, off, "reg-names", reg_names, names_len); + off = fdt_node_offset_by_compatible(fdt, off, + "fsl,lx2160a-pcie"); + } + + return 0; +} +#endif + #if defined(CONFIG_TARGET_LX2160AQDS) void esdhc_dspi_status_fixup(void *blob) { diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index d68b40de3f..0eca208020 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -9,6 +9,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 94f58a832f..dedb6c747e 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -10,6 +10,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_AHCI=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_BOARD_FIXUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y -- 2.17.1

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[U-Boot] [PATCH v2 1/3] sysreset: switch to using SYSRESET_POWER_OFF for poweroff
by Urja Rannikko 15 Aug '19

15 Aug '19

It seems that SYSRESET_POWER_OFF was added recently, and all previous code used SYSRESET_POWER for poweroff. SYSRESET_POWER is supposed to be a PMIC-level power cycle, not a poweroff. Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- v2: Do not change STPMIC1 driver (thats actually SYSRESET_POWER) Note: I didnt touch the test/dm/sysreset.c code yet, mostly because I wanted to get feedback on this first and that i'd need to understand the tests properly to do that (and i havent used them before at all). --- arch/arm/mach-stm32mp/cmd_poweroff.c | 2 +- arch/sandbox/cpu/state.c | 2 +- drivers/sysreset/sysreset_psci.c | 2 +- drivers/sysreset/sysreset_sandbox.c | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_poweroff.c b/arch/arm/mach-stm32mp/cmd_poweroff.c index f54dd1daf2..62347425a0 100644 --- a/arch/arm/mach-stm32mp/cmd_poweroff.c +++ b/arch/arm/mach-stm32mp/cmd_poweroff.c @@ -14,7 +14,7 @@ int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("poweroff ...\n"); mdelay(100); - ret = sysreset_walk(SYSRESET_POWER); + ret = sysreset_walk(SYSRESET_POWER_OFF); if (ret == -EINPROGRESS) mdelay(1000); diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index d3b9c05985..dee5fde4f7 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -355,7 +355,7 @@ void state_reset_for_test(struct sandbox_state *state) { /* No reset yet, so mark it as such. Always allow power reset */ state->last_sysreset = SYSRESET_COUNT; - state->sysreset_allowed[SYSRESET_POWER] = true; + state->sysreset_allowed[SYSRESET_POWER_OFF] = true; memset(&state->wdt, '\0', sizeof(state->wdt)); memset(state->spi, '\0', sizeof(state->spi)); diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c index de2ec8aeb1..c7907b3226 100644 --- a/drivers/sysreset/sysreset_psci.c +++ b/drivers/sysreset/sysreset_psci.c @@ -18,7 +18,7 @@ static int psci_sysreset_request(struct udevice *dev, enum sysreset_t type) case SYSRESET_COLD: function_id = PSCI_0_2_FN_SYSTEM_RESET; break; - case SYSRESET_POWER: + case SYSRESET_POWER_OFF: function_id = PSCI_0_2_FN_SYSTEM_OFF; break; default: diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c index 38e2a7e241..8bc9f4b4cc 100644 --- a/drivers/sysreset/sysreset_sandbox.c +++ b/drivers/sysreset/sysreset_sandbox.c @@ -57,13 +57,13 @@ static int sandbox_sysreset_request(struct udevice *dev, enum sysreset_t type) case SYSRESET_COLD: state->last_sysreset = type; break; - case SYSRESET_POWER: + case SYSRESET_POWER_OFF: state->last_sysreset = type; if (!state->sysreset_allowed[type]) return -EACCES; sandbox_exit(); break; - case SYSRESET_POWER_OFF: + case SYSRESET_POWER: if (!state->sysreset_allowed[type]) return -EACCES; default: -- 2.21.0

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[U-Boot] [PATCH v4 0/2] Add board support for iMX8QXP AI_ML board
by Manivannan Sadhasivam 15 Aug '19

15 Aug '19

Hello, This patchset adds initial board support for iMX8QXP AI_ML board from Einfochips. This board is one of the Consumer Edition and AI boards of the 96Boards family. This initial supports contains following peripherals which are tested and known to work: 1. Debug serial via UART2 2. SD card 3. Ethernet Thanks, Mani Note: This patchset depends on the below cleanup patches submitted: [U-Boot,1/2] arm: imx8: factor out uart init code [U-Boot,2/2] arm: imx8: don't duplicate build_info() Changes in v4: * Incorporated review comments from Fabio. Changes in v3: * Incorporated review comments from Fabio. Major change is switching to distro_boot. * Added Reviewed-by tag from Peng Fan. Changes in v2: * Rebased the patches on top of following patches: [U-Boot,1/2] arm: imx8: factor out uart init code [U-Boot,2/2] arm: imx8: don't duplicate build_info() Manivannan Sadhasivam (2): arm: dts: Add devicetree support for iMXQXP AI_ML board board: Add support for iMX8QXP AI_ML board arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi | 117 +++++++++++ arch/arm/dts/fsl-imx8qxp-ai_ml.dts | 181 ++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 6 + board/einfochips/imx8qxp_ai_ml/Kconfig | 12 ++ board/einfochips/imx8qxp_ai_ml/MAINTAINERS | 6 + board/einfochips/imx8qxp_ai_ml/Makefile | 8 + board/einfochips/imx8qxp_ai_ml/README | 49 +++++ .../einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c | 117 +++++++++++ board/einfochips/imx8qxp_ai_ml/imximage.cfg | 24 +++ board/einfochips/imx8qxp_ai_ml/spl.c | 49 +++++ configs/imx8qxp_ai_ml_defconfig | 83 ++++++++ include/configs/imx8qxp_ai_ml.h | 104 ++++++++++ 13 files changed, 757 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp-ai_ml.dts create mode 100644 board/einfochips/imx8qxp_ai_ml/Kconfig create mode 100644 board/einfochips/imx8qxp_ai_ml/MAINTAINERS create mode 100644 board/einfochips/imx8qxp_ai_ml/Makefile create mode 100644 board/einfochips/imx8qxp_ai_ml/README create mode 100644 board/einfochips/imx8qxp_ai_ml/imx8qxp_ai_ml.c create mode 100644 board/einfochips/imx8qxp_ai_ml/imximage.cfg create mode 100644 board/einfochips/imx8qxp_ai_ml/spl.c create mode 100644 configs/imx8qxp_ai_ml_defconfig create mode 100644 include/configs/imx8qxp_ai_ml.h -- 2.17.1

3 10

[U-Boot] [PATCH v4 0/5] dm: spi: Convert Freescale ESPI driver to driver
by Chuanhua Han 15 Aug '19

15 Aug '19

In order to convert the Freescale ESPI driver to the driver model, there are 5 related patches in the current patch set: 0001-spl-dm-disable-SPI-DM-flash-for-non-DM-SPL.patch 0002-dm-spi-Convert-Freescale-ESPI-driver-to-driver-model.patch 0003-powerpc-dts-t2080-add-espi-controller-node-support.patch 0004-powerpc-dts-t2080qds-add-espi-slave-nodes-support.patch 0005-configs-enable-espi-device-module-in-T2080QDS.patch The first patch is to solve the problem that spl can't work when spiboot, and this is required for SPI boot. The other four patches are supported by the driver model. This patchset already supports the full dm mode, and fsl_espi driver support both OF_CONTROL and PLATDATA. Chuanhua Han (5): spl: dm: disable SPI DM flash for non-DM SPL dm: spi: Convert Freescale ESPI driver to driver model powerpc: dts: t2080: add espi controller node support powerpc: dts: t2080qds: add espi slave nodes support configs: enable espi device module in T2080QDS arch/powerpc/dts/t2080.dtsi | 10 + arch/powerpc/dts/t2080qds.dts | 33 ++ configs/T2080QDS_NAND_defconfig | 2 + configs/T2080QDS_SDCARD_defconfig | 2 + configs/T2080QDS_SECURE_BOOT_defconfig | 2 + configs/T2080QDS_SPIFLASH_defconfig | 2 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 + configs/T2080QDS_defconfig | 2 + drivers/spi/fsl_espi.c | 444 ++++++++++++++++------ include/config_uncmd_spl.h | 1 + include/dm/platform_data/fsl_espi.h | 16 + 11 files changed, 395 insertions(+), 121 deletions(-) create mode 100644 include/dm/platform_data/fsl_espi.h -- 2.17.1

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[U-Boot] [PATCH v2] arm: socfpga: gen5: don't zero bss in board_init_f()
by Simon Goldschmidt 15 Aug '19

15 Aug '19

The socfpga gen5 SPL manually zeroed bss in board_init_f(). Now that the DDR driver does not use bss any more, bss is not used before board_init_r() and we can remove this hack. bss is normally zeroed by crt0.S, but after board_init_f(), before board_init_r(). socfpga just had this double-zeroing because it invalidly used bss in board_init_f() already (during DDR initialization). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- Changes in v2: - removed patch 1/2 from v1 (already applied) - improved commit message in this patch arch/arm/mach-socfpga/spl_gen5.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 87b76b47de..47e63709ad 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -79,8 +79,6 @@ void board_init_f(ulong dummy) writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, &sysmgr_regs->eccgrp_ocram); - memset(__bss_start, 0, __bss_end - __bss_start); - socfpga_sdram_remap_zero(); socfpga_pl310_clear(); -- 2.20.1

2 2

[U-Boot] [PATCH 1/7] net: sh_eth: Add R8A77980 V3H gether support
by Marek Vasut 14 Aug '19

14 Aug '19

The R8A77980 V3H gether needs a few minor adjustments to the sh_eth driver, add them to support ethernet on R8A77980. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/net/sh_eth.c | 15 +++++++++++---- drivers/net/sh_eth.h | 6 +++++- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index da79b766a6..485c4b71ad 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -374,10 +374,16 @@ static void sh_eth_write_hwaddr(struct sh_eth_info *port_info, static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac) { struct sh_eth_info *port_info = &eth->port_info[eth->port]; + unsigned long edmr; /* Configure e-dmac registers */ - sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) | - (EMDR_DESC | EDMR_EL), EDMR); + edmr = sh_eth_read(port_info, EDMR); + edmr &= ~EMDR_DESC_R; + edmr |= EMDR_DESC | EDMR_EL; +#if defined(CONFIG_R8A77980) + edmr |= EDMR_NBST; +#endif + sh_eth_write(port_info, edmr, EDMR); sh_eth_write(port_info, 0, EESIPR); sh_eth_write(port_info, 0, TRSCER); @@ -407,7 +413,7 @@ static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac) #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); -#elif defined(CONFIG_RCAR_GEN2) +#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980) sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR); #endif } @@ -426,7 +432,7 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth) sh_eth_write(port_info, GECMR_100B, GECMR); #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) sh_eth_write(port_info, 1, RTRATE); -#elif defined(CONFIG_RCAR_GEN2) +#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980) val = ECMR_RTM; #endif } else if (phy->speed == 10) { @@ -931,6 +937,7 @@ static const struct udevice_id sh_ether_ids[] = { { .compatible = "renesas,ether-r8a7791" }, { .compatible = "renesas,ether-r8a7793" }, { .compatible = "renesas,ether-r8a7794" }, + { .compatible = "renesas,gether-r8a77980" }, { } }; diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index e1bbd4913f..564cdaccb7 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -358,6 +358,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #elif defined(CONFIG_R7S72100) #define SH_ETH_TYPE_RZ #define BASE_IO_ADDR 0xE8203000 +#elif defined(CONFIG_R8A77980) +#define SH_ETH_TYPE_GETHER +#define BASE_IO_ADDR 0xE7400000 #endif /* @@ -374,6 +377,7 @@ enum EDSR_BIT { /* EDMR */ enum DMAC_M_BIT { + EDMR_NBST = 0x80, /* DMA transfer burst mode */ EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) EDMR_SRST = 0x03, /* Receive/Send reset */ @@ -563,7 +567,7 @@ enum FELIC_MODE_BIT { ECMR_PRM = 0x00000001, #ifdef CONFIG_CPU_SH7724 ECMR_RTM = 0x00000010, -#elif defined(CONFIG_RCAR_GEN2) +#elif defined(CONFIG_RCAR_GEN2) || defined (CONFIG_R8A77980) ECMR_RTM = 0x00000004, #endif -- 2.20.1

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[U-Boot] [RESEND PATCH] core: ofnode: Add ofnode_get_addr_size_index
by Keerthy 14 Aug '19

14 Aug '19

Add ofnode_get_addr_size_index function to fetch the address and size of the reg space based on index. Signed-off-by: Keerthy <j-keerthy(a)ti.com> --- Previous discussion can be found here: * https://patchwork.ozlabs.org/patch/999659/ drivers/core/ofnode.c | 13 ++++++++++--- include/dm/ofnode.h | 14 ++++++++++++++ 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 785f5c3acf..5bb06d3b00 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -251,7 +251,7 @@ int ofnode_read_size(ofnode node, const char *propname) return -EINVAL; } -fdt_addr_t ofnode_get_addr_index(ofnode node, int index) +fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size) { int na, ns; @@ -260,7 +260,7 @@ fdt_addr_t ofnode_get_addr_index(ofnode node, int index) uint flags; prop_val = of_get_address(ofnode_to_np(node), index, - NULL, &flags); + (u64 *)size, &flags); if (!prop_val) return FDT_ADDR_T_NONE; @@ -277,12 +277,19 @@ fdt_addr_t ofnode_get_addr_index(ofnode node, int index) ns = ofnode_read_simple_size_cells(ofnode_get_parent(node)); return fdtdec_get_addr_size_fixed(gd->fdt_blob, ofnode_to_offset(node), "reg", - index, na, ns, NULL, true); + index, na, ns, size, true); } return FDT_ADDR_T_NONE; } +fdt_addr_t ofnode_get_addr_index(ofnode node, int index) +{ + fdt_size_t size; + + return ofnode_get_addr_size_index(node, index, &size); +} + fdt_addr_t ofnode_get_addr(ofnode node) { return ofnode_get_addr_index(node, 0); diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index d206ee2caa..1be5ba4b45 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -354,6 +354,20 @@ ofnode ofnode_get_by_phandle(uint phandle); */ int ofnode_read_size(ofnode node, const char *propname); +/** + * ofnode_get_addr_size_index() - get an address/size from a node + * based on index + * + * This reads the register address/size from a node based on index + * + * @node: node to read from + * @index: Index of address to read (0 for first) + * @size: Pointer to size of the address + * @return address, or FDT_ADDR_T_NONE if not present or invalid + */ +phys_addr_t ofnode_get_addr_size_index(ofnode node, int index, + fdt_size_t *size); + /** * ofnode_get_addr_index() - get an address from a node * -- 2.17.1

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[U-Boot] [PATCH] drivers/spi: fsl_qspi: fix controller busy check
by Thomas Schaefer 14 Aug '19

14 Aug '19

> On Mon, Jun 24, 2019 at 10:34 PM Fabio Estevam <festevam(a)gmail.com> wrote: > > > > From: Thomas Schaefer <thomas.schaefer(a)kontron.com> > > > > During QSPI reads, current is_busy_controller function sporadically > > fails with -ETIMEDOUT due to fixed number of 5 test loops. This > > patch fixes this by using the readl_poll_timeout function with > > 1000 us timeout. > > This sounds like two different functionalities into one patch. better create a timeout fix in one patch and another patch to migrate read_poll. I have split the patch into a series of 2 to differentiate functionality, as follows Thomas

4 5

[U-Boot] [PATCH v3 0/9] NXP LS1021A-TSN Board
by Vladimir Oltean 14 Aug '19

14 Aug '19

This patchset adds initial support for the NXP LS1021A-TSN board, an evaluation platform built in partnership with VVDN/Argonboards for some IEEE 802.1 TSN features. It features a cleaned-up U-Boot board support taken from OpenIL, as well as an eTSEC migration to DM_ETH. I picked up Bin Meng's patch that converts the LS1021A-TWR (different board, same SoC): https://lists.denx.de/pipermail/u-boot/2018-May/330096.html verified it on the LS1021A-TSN board I am submitting, and made a few adjustments where necessary. TODO items: - Make the eTSEC driver support fixed-link interfaces (necessary for the enet2 <-> sja1105 internal port) - Add driver for SJA1105 switch - Potentially migrate the eTSEC MDIO bus driver to DM_MDIO and expose the TBI PHY to mdio commands (useful for debugging), once https://lists.denx.de/pipermail/u-boot/2019-June/371563.html is merged. Bin Meng (1): arm: ls1021atwr: Convert to use driver model TSEC driver Jianchao Wang (1): Add support for the NXP LS1021A-TSN board Vladimir Oltean (7): net: tsec: Refactor the readout of the tbi-handle property net: tsec: Fix offset of MDIO registers for DM_ETH net: tsec: Reverse Christmas tree notation net: tsec: Make errors visible net: tsec: Common handling of MAC station address for DM_ETH net: tsec: Change compatible strings to match Linux configs: ls1021atwr: Fix distro_bootcmd for QSPI boot arch/arm/Kconfig | 14 + arch/arm/cpu/armv7/ls102xa/cpu.c | 2 +- arch/arm/cpu/armv7/ls102xa/fdt.c | 10 + arch/arm/dts/Makefile | 2 +- arch/arm/dts/ls1021a-tsn.dts | 77 ++++++ arch/arm/dts/ls1021a-twr.dtsi | 32 +++ arch/arm/dts/ls1021a.dtsi | 30 +- board/freescale/ls1021atsn/Kconfig | 18 ++ board/freescale/ls1021atsn/MAINTAINERS | 8 + board/freescale/ls1021atsn/Makefile | 3 + board/freescale/ls1021atsn/README.rst | 97 +++++++ board/freescale/ls1021atsn/ls1021atsn.c | 260 ++++++++++++++++++ board/freescale/ls1021atsn/ls102xa_pbi.cfg | 15 + board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg | 8 + board/freescale/ls1021atwr/ls1021atwr.c | 38 --- configs/ls1021atsn_qspi_defconfig | 79 ++++++ configs/ls1021atsn_sdcard_defconfig | 91 ++++++ configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 + configs/ls1021atwr_nor_defconfig | 2 + configs/ls1021atwr_nor_lpuart_defconfig | 2 + configs/ls1021atwr_qspi_defconfig | 2 + ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 + configs/ls1021atwr_sdcard_ifc_defconfig | 2 + configs/ls1021atwr_sdcard_qspi_defconfig | 2 + doc/device-tree-bindings/net/fsl-tsec-phy.txt | 4 +- drivers/net/tsec.c | 59 ++-- include/configs/ls1021atsn.h | 250 +++++++++++++++++ include/configs/ls1021atwr.h | 30 +- include/tsec.h | 4 +- 29 files changed, 1038 insertions(+), 107 deletions(-) create mode 100644 arch/arm/dts/ls1021a-tsn.dts create mode 100644 board/freescale/ls1021atsn/Kconfig create mode 100644 board/freescale/ls1021atsn/MAINTAINERS create mode 100644 board/freescale/ls1021atsn/Makefile create mode 100644 board/freescale/ls1021atsn/README.rst create mode 100644 board/freescale/ls1021atsn/ls1021atsn.c create mode 100644 board/freescale/ls1021atsn/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg create mode 100644 configs/ls1021atsn_qspi_defconfig create mode 100644 configs/ls1021atsn_sdcard_defconfig create mode 100644 include/configs/ls1021atsn.h -- 2.17.1

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