July 2019 - U-Boot

[U-Boot] [PATCH] sunxi: Add H6 SPI SPL support
by Marek Kraus 06 Sep '19

06 Sep '19

Add H6 SPI addresses and masks (since H6 memory map is totally different). Tested on Pine H64 rev B with Winbond W25Q128FW, Signed-off-by: Marek Kraus <gamelaster(a)outlook.com> --- arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/spl_spi_sunxi.c | 123 ++++++++++++++++++++++++++++-------- configs/pine_h64_defconfig | 1 + 3 files changed, 98 insertions(+), 28 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 74e234cded..81b5948454 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -972,7 +972,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN50I_H6 help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 043d9f6ead..cdf6d53ec5 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -28,7 +28,7 @@ * A10/A13/A20 (sun4i variant) and everything else (sun6i variant). * Both of them are supported. * - * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are + * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64/H6 are * supported at the moment. */ @@ -70,6 +70,25 @@ #define SUN6I_TCR_XCH BIT(31) /*****************************************************************************/ +/* SUN50I_H6 variant of the SPI controller */ +/*****************************************************************************/ + +#define SUN50I_H6_SPI0_CCTL (0x05010000 + 0x24) +#define SUN50I_H6_SPI0_GCR (0x05010000 + 0x04) +#define SUN50I_H6_SPI0_TCR (0x05010000 + 0x08) +#define SUN50I_H6_SPI0_FIFO_STA (0x05010000 + 0x1C) +#define SUN50I_H6_SPI0_MBC (0x05010000 + 0x30) +#define SUN50I_H6_SPI0_MTC (0x05010000 + 0x34) +#define SUN50I_H6_SPI0_BCC (0x05010000 + 0x38) +#define SUN50I_H6_SPI0_TXD (0x05010000 + 0x200) +#define SUN50I_H6_SPI0_RXD (0x05010000 + 0x300) + +#define SUN50I_H6_SPI_GATING_REG (0x03001000 + 0x96C) +#define SUN50I_H6_SPI0_RST BIT(16) +#define SUN50I_H6_SPI0_GATING_CLK BIT(0) +#define SUN50I_H6_CCU_SPI0_CLK (0x03001000 + 0x940) + +/*****************************************************************************/ #define CCM_AHB_GATING0 (0x01C20000 + 0x60) #define CCM_SPI0_CLK (0x01C20000 + 0xA0) @@ -85,19 +104,29 @@ /* * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting - * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. + * from SPI Flash, H6 using PC0,PC2,PC3,PC5 , everything else is using + * pins PC0,PC1,PC2,PC3. */ static void spi0_pinmux_setup(unsigned int pin_function) { unsigned int pin; - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) - sunxi_gpio_set_cfgpin(pin, pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); - else + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { + sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); + sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); + sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); + } else { + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) + sunxi_gpio_set_cfgpin(pin, pin_function); + + if (IS_ENABLED(CONFIG_MACH_SUN4I) || + IS_ENABLED(CONFIG_MACH_SUN7I)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); + else + sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); + } } /* @@ -106,26 +135,43 @@ static void spi0_pinmux_setup(unsigned int pin_function) static void spi0_enable_clock(void) { /* Deassert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(SUN50I_H6_SPI_GATING_REG, + SUN50I_H6_SPI0_RST); + else if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); /* Open the SPI0 gate */ - setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(SUN50I_H6_SPI_GATING_REG, + SUN50I_H6_SPI0_GATING_CLK); + else + setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Divide by 4 */ - writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? - SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + writel(SPI0_CLK_DIV_BY_4, SUN50I_H6_SPI0_CCTL); + else + writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? + SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); + /* 24MHz from OSC24M */ - writel((1 << 31), CCM_SPI0_CLK); + writel((1 << 31), IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_CCU_SPI0_CLK : CCM_SPI0_CLK); - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { /* Enable SPI in the master mode and do a soft reset */ - setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | - SUN6I_CTL_ENABLE | - SUN6I_CTL_SRST); + setbits_le32(IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_SPI0_GCR : SUN6I_SPI0_GCR, + SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE | + SUN6I_CTL_SRST); + /* Wait for completion */ - while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) + while (readl(IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_SPI0_GCR : SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) ; } else { /* Enable SPI in the master mode and reset FIFO */ @@ -139,22 +185,33 @@ static void spi0_enable_clock(void) static void spi0_disable_clock(void) { /* Disable the SPI0 controller */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) - clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | - SUN6I_CTL_ENABLE); + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + clrbits_le32(IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_SPI0_GCR : SUN6I_SPI0_GCR, + SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE); else clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | SUN4I_CTL_ENABLE); /* Disable the SPI0 clock */ - writel(0, CCM_SPI0_CLK); + writel(0, IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_CCU_SPI0_CLK : CCM_SPI0_CLK); /* Close the SPI0 gate */ - clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + clrbits_le32(SUN50I_H6_SPI_GATING_REG, + SUN50I_H6_SPI0_GATING_CLK); + else + clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Assert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) - clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(SUN50I_H6_SPI_GATING_REG, + SUN50I_H6_SPI0_RST); + else if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); } @@ -162,7 +219,7 @@ static void spi0_init(void) { unsigned int pin_function = SUNXI_GPC_SPI0; - if (IS_ENABLED(CONFIG_MACH_SUN50I)) + if (IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN50I_H6)) pin_function = SUN50I_GPC_SPI0; spi0_pinmux_setup(pin_function); @@ -173,7 +230,9 @@ static void spi0_deinit(void) { /* New SoCs can disable pins, older could only set them as input */ unsigned int pin_function = SUNXI_GPIO_INPUT; - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6)) pin_function = SUNXI_GPIO_DISABLE; spi0_disable_clock(); @@ -233,7 +292,17 @@ static void spi0_read_data(void *buf, u32 addr, u32 len) if (chunk_len > SPI_READ_MAX_SIZE) chunk_len = SPI_READ_MAX_SIZE; - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { + sunxi_spi0_read_data(buf8, addr, chunk_len, + SUN50I_H6_SPI0_TCR, + SUN6I_TCR_XCH, + SUN50I_H6_SPI0_FIFO_STA, + SUN50I_H6_SPI0_TXD, + SUN50I_H6_SPI0_RXD, + SUN50I_H6_SPI0_MBC, + SUN50I_H6_SPI0_MTC, + SUN50I_H6_SPI0_BCC); + } else if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { sunxi_spi0_read_data(buf8, addr, chunk_len, SUN6I_SPI0_TCR, SUN6I_TCR_XCH, diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index e34f4fd1e4..baddc33abb 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -6,6 +6,7 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -- 2.11.0

2 3

[U-Boot] What if ATF can be part of U-Boot source, like SPL?
by Jagan Teki 06 Sep '19

06 Sep '19

In terms of code maintenance and development feasibility it is always a better approach to have out-of-tree code or binary to be part of in-house source tree. This is what exactly it was done for SPL, if I'm not wrong. So can we do the same thing for ATF on ARM64 SoCs? We are using ATF (on Allwinner) to switch EL3 to EL2 for start loading U-Boot proper and minimal PSCI, PMIC initialization. So assuming the functionality of ATF (like here) is limited so the code it require can be limited too, so why can't this code to be part of U-Boot tree? This would ultimately avoid out-off-tree ATF builds with associated variable exporting during u-boot builds. More over this idea would also help to design a single-step bootloader where it can't depends on out-of-tree sources. Code sync from ATF source to U-Boot can be possible in-terms licensing point-of-view since ATF licensed under BSD-3-Clause. I'm thinking this can be a worth-idea to look at it and I'm sure It may require some hard changes and other things to consider but just posted to understand how hard or feasible or meaningful it is? Feel free for any comments? Jagan, Amarula Solutions India.

10 22

[U-Boot] [PATCH] ARM: exynos5: Try to boot on mmc2 before mmc0/1
by Guillaume GARDET 05 Sep '19

05 Sep '19

As stated in commit a61a4a1db009e3e600258551a01b54c4f50ec103 with DM_MMC, exynos boards now enumarates external SD/MMC slot as mmc2, instead of mmc1 with legacy mode. Moving mmc2 before mmc1/0 restore the previous behavior of trying external SD/MMC before internal slot. Signed-off-by: Guillaume GARDET <guillaume.gardet(a)arm.com> Cc: Lukasz Majewski <lukma(a)denx.de> Cc: Anand Moon <linux.amoon(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- include/configs/exynos5-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 397bbf6d9d..e0a4d76d53 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -128,9 +128,9 @@ #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 2) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ - func(MMC, mmc, 2) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) -- 2.22.0

4 3

[U-Boot] [PATCH 1/1] drivers: net: pfe_eth: undefined return value
by Heinrich Schuchardt 04 Sep '19

04 Sep '19

Do not use random value from stack as return value of pfe_phy_write(). Indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/net/pfe_eth/pfe_mdio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c index 2dde9e7ac8..62309670fa 100644 --- a/drivers/net/pfe_eth/pfe_mdio.c +++ b/drivers/net/pfe_eth/pfe_mdio.c @@ -110,7 +110,6 @@ static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, u32 phy; u32 reg_data; int timeout = MDIO_TIMEOUT; - int val; if (dev_addr == MDIO_DEVAD_NONE) { reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << @@ -150,7 +149,7 @@ static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr, reg_addr, data); - return val; + return 0; } static void pfe_configure_serdes(struct pfe_eth_dev *priv) -- 2.20.1

2 2

[U-Boot] [PATCH v2 1/1] test: dm_mdio: avoid out of bounds access
by Heinrich Schuchardt 04 Sep '19

04 Sep '19

SANDBOX_PHY_REG_CNT is not an allowable index for the array u16 reg[SANDBOX_PHY_REG_CNT]. Identified by cppcheck. Fixes: b47edf8069cc ("test: dm_mdio: add a 2nd register to the emulated PHY") Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- v2 the same error occurs twice --- drivers/net/mdio_sandbox.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mdio_sandbox.c b/drivers/net/mdio_sandbox.c index df053f5381..b731f60a98 100644 --- a/drivers/net/mdio_sandbox.c +++ b/drivers/net/mdio_sandbox.c @@ -27,7 +27,7 @@ static int mdio_sandbox_read(struct udevice *dev, int addr, int devad, int reg) return -ENODEV; if (devad != MDIO_DEVAD_NONE) return -ENODEV; - if (reg < 0 || reg > SANDBOX_PHY_REG_CNT) + if (reg < 0 || reg >= SANDBOX_PHY_REG_CNT) return -ENODEV; return priv->reg[reg]; @@ -45,7 +45,7 @@ static int mdio_sandbox_write(struct udevice *dev, int addr, int devad, int reg, return -ENODEV; if (devad != MDIO_DEVAD_NONE) return -ENODEV; - if (reg < 0 || reg > SANDBOX_PHY_REG_CNT) + if (reg < 0 || reg >= SANDBOX_PHY_REG_CNT) return -ENODEV; priv->reg[reg] = val; -- 2.20.1

2 2

[U-Boot] [PATCH] net: mvpp2: support setting hardware addresses from ethernet core
by Matt Pelland 04 Sep '19

04 Sep '19

mvpp2 already has support for setting MAC addresses but this functionality was not exposed to the ethernet core. This commit exposes this functionality so that MAC address assignments stored in U-Boot's environment are correctly applied before Linux boots. Signed-off-by: Matt Pelland <mpelland(a)starry.com> --- drivers/net/mvpp2.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index bcc6fe92a9..d2d17f1417 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -5321,6 +5321,13 @@ static void mvpp2_stop(struct udevice *dev) mvpp2_cleanup_txqs(port); } +static mvpp2_write_hwaddr(struct udevice *dev) +{ + struct mvpp2_port *port = dev_get_priv(dev); + + mvpp2_prs_update_mac_da(port, port->dev_addr); +} + static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port) { writel(port->phyaddr, port->priv->iface_base + @@ -5525,6 +5532,7 @@ static const struct eth_ops mvpp2_ops = { .send = mvpp2_send, .recv = mvpp2_recv, .stop = mvpp2_stop, + .write_hwaddr = mvpp2_write_hwaddr }; static struct driver mvpp2_driver = { -- 2.21.0

4 8

[U-Boot] [PATCH v2 0/4] Marvell MDIO driver and new MDIO name property
by Alex Marginean 04 Sep '19

04 Sep '19

This is a respin of the original Marvell MDIO driver submitted by Ken about one year ago, using the new MDIO DM code. Added binding documents for mdio and marvell-mdio and introduced a new optional property for naming MDIO buses in case the driver can't reasonably pick a nice name by itself. Changes in v2: add "-mdio" to device-name for cpm/cps Alex Marginean (4): net: mdio-uclass: name MDIO according to device-name property if preset doc: bindings: add mdio.txt describing generic MDIO properties drivers: net: add marvell MDIO driver arm: dts: Set custom names for cp110 master/slave MDIO buses arch/arm/dts/armada-cp110-master.dtsi | 1 + arch/arm/dts/armada-cp110-slave.dtsi | 1 + doc/device-tree-bindings/net/marvell-mdio.txt | 15 ++ doc/device-tree-bindings/net/mdio.txt | 36 +++ drivers/net/Kconfig | 10 + drivers/net/Makefile | 1 + drivers/net/mvmdio.c | 236 ++++++++++++++++++ net/mdio-uclass.c | 11 + 8 files changed, 311 insertions(+) create mode 100644 doc/device-tree-bindings/net/marvell-mdio.txt create mode 100644 doc/device-tree-bindings/net/mdio.txt create mode 100644 drivers/net/mvmdio.c -- 2.17.1

4 11

[U-Boot] [PATCH v4 1/3] net: introduce packet capture support
by Ramon Fried 04 Sep '19

04 Sep '19

Add support for capturing ethernet packets and storing them in memory in PCAP(2.4) format, later to be analyzed by any PCAP viewer software (IE. Wireshark) This feature greatly assist debugging network issues such as detecting dropped packets, packet corruption etc. Signed-off-by: Ramon Fried <rfried.dev(a)gmail.com> Reviewed-by: Alex Marginean <alexm.osslist(a)gmail.com> Tested-by: Alex Marginean <alexm.osslist(a)gmail.com> --- Changes in v4: * Move implementation to pcap.c/pcap.h * Display error message when memory is exhausted. * Populate $pcapsize environment variable with actual capture size. * move outgoing pcap_post to eth_send() Changes in v3: * Change to implementation to command based. * Added counters for incoming/outgoing packets. * Support clearing the capture for multiple captures. * Added documentation (separate patch). Changes in v2: Fix type assignmnet to header.ts_sec cmd/Kconfig | 7 ++ cmd/Makefile | 1 + cmd/pcap.c | 71 +++++++++++++++++++++ include/net/pcap.h | 55 ++++++++++++++++ net/Makefile | 1 + net/eth-uclass.c | 7 ++ net/eth_legacy.c | 12 +++- net/net.c | 11 ++++ net/pcap.c | 156 +++++++++++++++++++++++++++++++++++++++++++++ 9 files changed, 320 insertions(+), 1 deletion(-) create mode 100644 cmd/pcap.c create mode 100644 include/net/pcap.h create mode 100644 net/pcap.c diff --git a/cmd/Kconfig b/cmd/Kconfig index 67284d8a5f..86aa5d8c00 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1263,6 +1263,13 @@ config BOOTP_NTPSERVER bool "Request & store 'ntpserverip' from BOOTP/DHCP server" depends on CMD_BOOTP +config CMD_PCAP + bool "pcap capture" + help + Selecting this will allow capturing all Ethernet packets and store + them in physical memory in a PCAP formated file, + later to be analyzed by PCAP reader application (IE. WireShark). + config BOOTP_PXE bool "Send PXE client arch to BOOTP/DHCP server" default y diff --git a/cmd/Makefile b/cmd/Makefile index 0aa3741453..61d5bc885a 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -102,6 +102,7 @@ obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o obj-$(CONFIG_CMD_ONENAND) += onenand.o obj-$(CONFIG_CMD_OSD) += osd.o obj-$(CONFIG_CMD_PART) += part.o +obj-$(CONFIG_CMD_PCAP) += pcap.o ifdef CONFIG_PCI obj-$(CONFIG_CMD_PCI) += pci.o endif diff --git a/cmd/pcap.c b/cmd/pcap.c new file mode 100644 index 0000000000..980603f7bd --- /dev/null +++ b/cmd/pcap.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 + * Ramon Fried <rfried.dev(a)gmail.com> + */ + +#include <common.h> +#include <command.h> +#include <net.h> +#include <net/pcap.h> + +static int do_pcap_init(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + phys_addr_t addr; + unsigned int size; + + if (argc != 3) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + size = simple_strtoul(argv[2], NULL, 10); + + return pcap_init(addr, size) ? CMD_RET_FAILURE : CMD_RET_SUCCESS; +} + +static int do_pcap_start(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + return pcap_start_stop(true) ? CMD_RET_FAILURE : CMD_RET_SUCCESS; +} + +static int do_pcap_stop(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + return pcap_start_stop(false) ? CMD_RET_FAILURE : CMD_RET_SUCCESS; +} + +static int do_pcap_status(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + return pcap_print_status() ? CMD_RET_FAILURE : CMD_RET_SUCCESS; +} + +static int do_pcap_clear(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + return pcap_clear() ? CMD_RET_FAILURE : CMD_RET_SUCCESS; +} + +static char pcap_help_text[] = + "- network packet capture\n\n" + "pcap\n" + "pcap init\t\t\t<addr> <max_size>\n" + "pcap start\t\t\tstart capture\n" + "pcap stop\t\t\tstop capture\n" + "pcap status\t\t\tprint status\n" + "pcap clear\t\t\tclear capture buffer\n" + "\n" + "With:\n" + "\t<addr>: user address to which pcap will be stored (hexedcimal)\n" + "\t<max_size>: Maximum size of pcap file (decimal)\n" + "\n"; + +U_BOOT_CMD_WITH_SUBCMDS(pcap, "pcap", pcap_help_text, + U_BOOT_SUBCMD_MKENT(init, 3, 0, do_pcap_init), + U_BOOT_SUBCMD_MKENT(start, 1, 0, do_pcap_start), + U_BOOT_SUBCMD_MKENT(stop, 1, 0, do_pcap_stop), + U_BOOT_SUBCMD_MKENT(status, 1, 0, do_pcap_status), + U_BOOT_SUBCMD_MKENT(clear, 1, 0, do_pcap_clear), +); diff --git a/include/net/pcap.h b/include/net/pcap.h new file mode 100644 index 0000000000..512ba982f1 --- /dev/null +++ b/include/net/pcap.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 + * Ramon Fried <rfried.dev(a)gmail.com> + */ + +/** + * pcap_init() - Initialize PCAP memory buffer + * + * @paddr physicaly memory address to store buffer + * @size maximum size of capture file in memory + * + * @return 0 on success, -ERROR on error + */ +int pcap_init(phys_addr_t paddr, unsigned long size); + +/** + * pcap_start_stop() - start / stop pcap capture + * + * @start if true, start capture if false stop capture + * + * @return 0 on success, -ERROR on error + */ +int pcap_start_stop(bool start); + +/** + * pcap_clear() - clear pcap capture buffer and statistics + * + * @return 0 on success, -ERROR on error + */ +int pcap_clear(void); + +/** + * pcap_print_status() - print status of pcap capture + * + * @return 0 on success, -ERROR on error + */ +int pcap_print_status(void); + +/** + * pcap_active() - check if pcap is enabled + * + * @return TRUE if active, FALSE if not. + */ +bool pcap_active(void); + +/** + * pcap_post() - Post a packet to PCAP file + * + * @packet: packet to post + * @len: packet length in bytes + * @outgoing packet direction (outgoing/incoming) + * @return 0 on success, -ERROR on error + */ +int pcap_post(const void *packet, size_t len, bool outgoing); diff --git a/net/Makefile b/net/Makefile index 6251ff3991..b975badeda 100644 --- a/net/Makefile +++ b/net/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o obj-$(CONFIG_NET) += net.o obj-$(CONFIG_CMD_NFS) += nfs.o obj-$(CONFIG_CMD_PING) += ping.o +obj-$(CONFIG_CMD_PCAP) += pcap.o obj-$(CONFIG_CMD_RARP) += rarp.o obj-$(CONFIG_CMD_SNTP) += sntp.o obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 031d558625..4252a02659 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -9,6 +9,9 @@ #include <dm.h> #include <environment.h> #include <net.h> +#if defined(CONFIG_CMD_PCAP) +#include <net/pcap.h> +#endif #include <dm/device-internal.h> #include <dm/uclass-internal.h> #include "eth_internal.h" @@ -344,6 +347,10 @@ int eth_send(void *packet, int length) /* We cannot completely return the error at present */ debug("%s: send() returned error %d\n", __func__, ret); } +#if defined(CONFIG_CMD_PCAP) + if (ret >= 0) + pcap_post(packet, length, true); +#endif return ret; } diff --git a/net/eth_legacy.c b/net/eth_legacy.c index e250a430f3..0705b7ccea 100644 --- a/net/eth_legacy.c +++ b/net/eth_legacy.c @@ -9,6 +9,9 @@ #include <command.h> #include <environment.h> #include <net.h> +#if defined(CONFIG_CMD_PCAP) +#include <net/pcap.h> +#endif #include <phy.h> #include <linux/errno.h> #include "eth_internal.h" @@ -352,10 +355,17 @@ int eth_is_active(struct eth_device *dev) int eth_send(void *packet, int length) { + int ret; + if (!eth_current) return -ENODEV; - return eth_current->send(eth_current, packet, length); + ret = eth_current->send(eth_current, packet, length); +#if defined(CONFIG_CMD_PCAP) + if (ret >= 0) + pcap_post(packet, lengeth, true); +#endif + return ret; } int eth_rx(void) diff --git a/net/net.c b/net/net.c index 58b0417cbe..722fa7a705 100644 --- a/net/net.c +++ b/net/net.c @@ -95,6 +95,9 @@ #include <net.h> #include <net/fastboot.h> #include <net/tftp.h> +#if defined(CONFIG_CMD_PCAP) +#include <net/pcap.h> +#endif #if defined(CONFIG_LED_STATUS) #include <miiphy.h> #include <status_led.h> @@ -671,6 +674,11 @@ done: net_set_icmp_handler(NULL); #endif net_set_state(prev_net_state); + +#if defined(CONFIG_CMD_PCAP) + if (pcap_active()) + pcap_print_status(); +#endif return ret; } @@ -1083,6 +1091,9 @@ void net_process_received_packet(uchar *in_packet, int len) debug_cond(DEBUG_NET_PKT, "packet received\n"); +#if defined(CONFIG_CMD_PCAP) + pcap_post(in_packet, len, false); +#endif net_rx_packet = in_packet; net_rx_packet_len = len; et = (struct ethernet_hdr *)in_packet; diff --git a/net/pcap.c b/net/pcap.c new file mode 100644 index 0000000000..4036d8a3fa --- /dev/null +++ b/net/pcap.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Ramon Fried <rfried.dev(a)gmail.com> + */ + +#include <common.h> +#include <net.h> +#include <net/pcap.h> +#include <time.h> +#include <asm/io.h> + +#define LINKTYPE_ETHERNET 1 + +static bool initialized; +static bool running; +static bool buffer_full; +static void *buf; +static unsigned int max_size; +static unsigned int pos; + +static unsigned long incoming_count; +static unsigned long outgoing_count; + +struct pcap_header { + u32 magic; + u16 version_major; + u16 version_minor; + s32 thiszone; + u32 sigfigs; + u32 snaplen; + u32 network; +}; + +struct pcap_packet_header { + u32 ts_sec; + u32 ts_usec; + u32 incl_len; + u32 orig_len; +}; + +static struct pcap_header file_header = { + .magic = 0xa1b2c3d4, + .version_major = 2, + .version_minor = 4, + .snaplen = 65535, + .network = LINKTYPE_ETHERNET, +}; + +int pcap_init(phys_addr_t paddr, unsigned long size) +{ + buf = map_physmem(paddr, size, 0); + if (!buf) { + printf("Failed mapping PCAP memory\n"); + return -ENOMEM; + } + + printf("PCAP capture initialized: addr: 0x%lx max length: %lu\n", + (unsigned long)buf, size); + + memcpy(buf, &file_header, sizeof(file_header)); + pos = sizeof(file_header); + max_size = size; + initialized = true; + running = false; + buffer_full = false; + incoming_count = 0; + outgoing_count = 0; + return 0; +} + +int pcap_start_stop(bool start) +{ + if (!initialized) { + printf("error: pcap was not initialized\n"); + return -ENODEV; + } + + running = start; + + return 0; +} + +int pcap_clear(void) +{ + if (!initialized) { + printf("error: pcap was not initialized\n"); + return -ENODEV; + } + + pos = sizeof(file_header); + incoming_count = 0; + outgoing_count = 0; + buffer_full = false; + + printf("pcap capture cleared\n"); + return 0; +} + +int pcap_post(const void *packet, size_t len, bool outgoing) +{ + struct pcap_packet_header header; + u64 cur_time = timer_get_us(); + + if (!initialized || !running || !buf) + return -ENODEV; + + if (buffer_full) + return -ENOMEM; + + if ((pos + len + sizeof(header)) >= max_size) { + buffer_full = true; + printf("\n!!! Buffer is full, consider increasing buffer size !!!\n"); + return -ENOMEM; + } + + header.ts_sec = cur_time / 1000000; + header.ts_usec = cur_time % 1000000; + header.incl_len = len; + header.orig_len = len; + + memcpy(buf + pos, &header, sizeof(header)); + pos += sizeof(header); + memcpy(buf + pos, packet, len); + pos += len; + + if (outgoing) + outgoing_count++; + else + incoming_count++; + + env_set_hex("pcapsize", pos); + + return 0; +} + +int pcap_print_status(void) +{ + if (!initialized) { + printf("pcap was not initialized\n"); + return -ENODEV; + } + printf("PCAP status:\n"); + printf("\tInitialized addr: 0x%lx\tmax length: %u\n", + (unsigned long)buf, max_size); + printf("\tStatus: %s.\t file size: %u\n", running ? "Active" : "Idle", + pos); + printf("\tIncoming packets: %lu Outgoing packets: %lu\n", + incoming_count, outgoing_count); + + return 0; +} + +bool pcap_active(void) +{ + return running; +} -- 2.22.0

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[U-Boot] [u-boot 1/2] drivers/fsl-mc: Create Kconfig file to manage driver specific configs better
by Florinel Iordache 04 Sep '19

04 Sep '19

Create drivers/net/fsl-mc/Kconfig and move fsl-mc specific configs from arch/arm/cpu/armv8/fsl-layerscape/Kconfig to this new Kconfig Signed-off-by: Florinel Iordache <florinel.iordache(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 17 ----------------- drivers/net/Kconfig | 1 + drivers/net/fsl-mc/Kconfig | 25 +++++++++++++++++++++++++ 3 files changed, 26 insertions(+), 17 deletions(-) create mode 100644 drivers/net/fsl-mc/Kconfig diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f48481f..87f84f7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -226,14 +226,6 @@ config FSL_LSCH3 config NXP_LSCH3_2 bool -config FSL_MC_ENET - bool "Management Complex network" - depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A - default y - select RESV_RAM - help - Enable Management Complex (MC) network - menu "Layerscape architecture" depends on FSL_LSCH2 || FSL_LSCH3 @@ -567,15 +559,6 @@ config SYS_FSL_HAS_RGMII bool depends on SYS_FSL_EC1 || SYS_FSL_EC2 - -config SYS_MC_RSV_MEM_ALIGN - hex "Management Complex reserved memory alignment" - depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A - help - Reserved memory needs to be aligned for MC to use. Default value - is 512MB. - config SPL_LDSCRIPT default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 77d0b3a..3627456 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1,5 +1,6 @@ source "drivers/net/phy/Kconfig" source "drivers/net/pfe_eth/Kconfig" +source "drivers/net/fsl-mc/Kconfig" config DM_ETH bool "Enable Driver Model for Ethernet drivers" diff --git a/drivers/net/fsl-mc/Kconfig b/drivers/net/fsl-mc/Kconfig new file mode 100644 index 0000000..25a2cb8 --- /dev/null +++ b/drivers/net/fsl-mc/Kconfig @@ -0,0 +1,25 @@ +# +# NXP Management Complex +# + +menuconfig FSL_MC_ENET + bool "NXP Management Complex" + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A + default y + select RESV_RAM + help + Enable Management Complex (MC) network + This is NXP Management Complex menuconfig + that contains all MC related config options + +if FSL_MC_ENET + +config SYS_MC_RSV_MEM_ALIGN + hex "Management Complex reserved memory alignment" + depends on RESV_RAM + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A + help + Reserved memory needs to be aligned for MC to use. Default value + is 512MB. + +endif # FSL_MC_ENET -- 1.9.1

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[U-Boot] [PATCH v2 1/2] drivers: net: driver for MDIO muxes controlled over I2C
by Alex Marginean 04 Sep '19

04 Sep '19

This driver is used for MDIO muxes driven over I2C. This is currently used on Freescale LS1028A QDS board, on which the physical MDIO MUX is controlled by an on-board FPGA which in turn is configured through I2C. Signed-off-by: Alex Marginean <alexm.osslist(a)gmail.com> Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> --- Changes in v2: - renamed APIs, config options to mdio_mux_i2creg (instead of i2c_reg) drivers/net/Kconfig | 8 +++ drivers/net/Makefile | 1 + drivers/net/mdio_mux_i2creg.c | 108 ++++++++++++++++++++++++++++++++++ 3 files changed, 117 insertions(+) create mode 100644 drivers/net/mdio_mux_i2creg.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 4d85fb1716..883b849b78 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -595,4 +595,12 @@ config FSL_ENETC This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs. +config MDIO_MUX_I2CREG + bool "MDIO MUX accessed as a register over I2C" + depends on DM_MDIO_MUX && DM_I2C + help + This driver is used for MDIO muxes driven by writing to a register of + an I2C chip. The board it was developed for uses a mux controlled by + on-board FPGA which in turn is accessed as a chip over I2C. + endif # NETDEVICES diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 97119cec7c..6122bcdb81 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -80,3 +80,4 @@ obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o +obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o diff --git a/drivers/net/mdio_mux_i2creg.c b/drivers/net/mdio_mux_i2creg.c new file mode 100644 index 0000000000..3e82898f46 --- /dev/null +++ b/drivers/net/mdio_mux_i2creg.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 + * Alex Marginean, NXP + */ + +#include <dm.h> +#include <errno.h> +#include <miiphy.h> +#include <i2c.h> + +/* + * This driver is used for MDIO muxes driven by writing to a register of an I2C + * chip. The board it was developed for uses a mux controlled by on-board FPGA + * which in turn is accessed as a chip over I2C. + */ + +struct mdio_mux_i2creg_priv { + struct udevice *chip; + int reg; + int mask; +}; + +static int mdio_mux_i2creg_select(struct udevice *mux, int cur, int sel) +{ + struct mdio_mux_i2creg_priv *priv = dev_get_priv(mux); + u8 val, val_old; + + /* if last selection didn't change we're good to go */ + if (cur == sel) + return 0; + + val_old = dm_i2c_reg_read(priv->chip, priv->reg); + val = (val_old & ~priv->mask) | (sel & priv->mask); + debug("%s: chip %s, reg %x, val %x => %x\n", __func__, priv->chip->name, + priv->reg, val_old, val); + dm_i2c_reg_write(priv->chip, priv->reg, val); + + return 0; +} + +static const struct mdio_mux_ops mdio_mux_i2creg_ops = { + .select = mdio_mux_i2creg_select, +}; + +static int mdio_mux_i2creg_probe(struct udevice *dev) +{ + struct mdio_mux_i2creg_priv *priv = dev_get_priv(dev); + ofnode chip_node, bus_node; + struct udevice *i2c_bus; + u32 reg_mask[2]; + u32 chip_addr; + int err; + + /* read the register addr/mask pair */ + err = dev_read_u32_array(dev, "mux-reg-masks", reg_mask, 2); + if (err) { + debug("%s: error reading mux-reg-masks property\n", __func__); + return err; + } + + /* parent should be an I2C chip, grandparent should be an I2C bus */ + chip_node = ofnode_get_parent(dev->node); + bus_node = ofnode_get_parent(chip_node); + + err = uclass_get_device_by_ofnode(UCLASS_I2C, bus_node, &i2c_bus); + if (err) { + debug("%s: can't find I2C bus for node %s\n", __func__, + ofnode_get_name(bus_node)); + return err; + } + + err = ofnode_read_u32(chip_node, "reg", &chip_addr); + if (err) { + debug("%s: can't read chip address in %s\n", __func__, + ofnode_get_name(chip_node)); + return err; + } + + err = i2c_get_chip(i2c_bus, (uint)chip_addr, 1, &priv->chip); + if (err) { + debug("%s: can't find i2c chip device for addr %x\n", __func__, + chip_addr); + return err; + } + + priv->reg = (int)reg_mask[0]; + priv->mask = (int)reg_mask[1]; + + debug("%s: chip %s, reg %x, mask %x\n", __func__, priv->chip->name, + priv->reg, priv->mask); + + return 0; +} + +static const struct udevice_id mdio_mux_i2creg_ids[] = { + { .compatible = "mdio-mux-i2creg" }, + { } +}; + +U_BOOT_DRIVER(mdio_mux_i2creg) = { + .name = "mdio_mux_i2creg", + .id = UCLASS_MDIO_MUX, + .of_match = mdio_mux_i2creg_ids, + .probe = mdio_mux_i2creg_probe, + .ops = &mdio_mux_i2creg_ops, + .priv_auto_alloc_size = sizeof(struct mdio_mux_i2creg_priv), +}; -- 2.17.1

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