July 2019 - U-Boot

[U-Boot] [PATCH v2 1/7] imx8: Add lpcg driver for iMX8QM/QXP
by Ye Li 17 Sep '19

17 Sep '19

Each module may have one or more lpcg registers for SW/HW enabling its clocks. Add lpcg register address and its driver for accessing lpcg. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- Changes in v2: - Fix license and blank line arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h | 198 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h | 192 +++++++++++++++++++++++++ arch/arm/include/asm/arch-imx8/lpcg.h | 25 ++++ arch/arm/mach-imx/imx8/Makefile | 2 +- arch/arm/mach-imx/imx8/lpcg.c | 114 +++++++++++++++ 5 files changed, 530 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h create mode 100644 arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h create mode 100644 arch/arm/include/asm/arch-imx8/lpcg.h create mode 100644 arch/arm/mach-imx/imx8/lpcg.c diff --git a/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h b/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h new file mode 100644 index 0000000..718dac4 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#ifndef _SC_LPCG_H +#define _SC_LPCG_H + +/*LSIO SS */ +#define PWM_0_LPCG 0x5D400000 +#define PWM_1_LPCG 0x5D410000 +#define PWM_2_LPCG 0x5D420000 +#define PWM_3_LPCG 0x5D430000 +#define PWM_4_LPCG 0x5D440000 +#define PWM_5_LPCG 0x5D450000 +#define PWM_6_LPCG 0x5D460000 +#define PWM_7_LPCG 0x5D470000 +#define GPIO_0_LPCG 0x5D480000 +#define GPIO_1_LPCG 0x5D490000 +#define GPIO_2_LPCG 0x5D4A0000 +#define GPIO_3_LPCG 0x5D4B0000 +#define GPIO_4_LPCG 0x5D4C0000 +#define GPIO_5_LPCG 0x5D4D0000 +#define GPIO_6_LPCG 0x5D4E0000 +#define GPIO_7_LPCG 0x5D4F0000 +#define FSPI_0_LPCG 0x5D520000 +#define FSPI_1_LPCG 0x5D530000 +#define GPT_0_LPCG 0x5D540000 +#define GPT_1_LPCG 0x5D550000 +#define GPT_2_LPCG 0x5D560000 +#define GPT_3_LPCG 0x5D570000 +#define GPT_4_LPCG 0x5D580000 +#define OCRAM_LPCG 0x5D590000 +#define KPP_LPCG 0x5D5A0000 +#define MU_5A_LPCG 0x5D600000 +#define MU_6A_LPCG 0x5D610000 +#define MU_7A_LPCG 0x5D620000 +#define MU_8A_LPCG 0x5D630000 +#define MU_9A_LPCG 0x5D640000 +#define MU_10A_LPCG 0x5D650000 +#define MU_11A_LPCG 0x5D660000 +#define MU_12A_LPCG 0x5D670000 +#define MU_13A_LPCG 0x5D680000 + +/* HSIO SS */ +#define CRR_5_LPCG 0x5F0F0000 +#define CRR_4_LPCG 0x5F0E0000 +#define CRR_3_LPCG 0x5F0D0000 +#define CRR_2_LPCG 0x5F0C0000 +#define CRR_1_LPCG 0x5F0B0000 +#define CRR_0_LPCG 0x5F0A0000 +#define PHY_1_LPCG 0x5F090000 +#define PHY_2_LPCG 0x5F080000 +#define SATA_0_LPCG 0x5F070000 +#define PCIE_B_LPCG 0x5F060000 +#define PCIE_A_LPCG 0x5F050000 + +/* DMA SS */ +#define FLEX_CAN_2_LPCG 0x5ACF0000 +#define FLEX_CAN_1_LPCG 0x5ACE0000 +#define FLEX_CAN_0_LPCG 0x5ACD0000 +#define FTM_1_LPCG 0x5ACB0000 +#define FTM_0_LPCG 0x5ACA0000 +#define ADC_1_LPCG 0x5AC90000 +#define ADC_0_LPCG 0x5AC80000 +#define LPI2C_4_LPCG 0x5AC40000 +#define LPI2C_3_LPCG 0x5AC30000 +#define LPI2C_2_LPCG 0x5AC20000 +#define LPI2C_1_LPCG 0x5AC10000 +#define LPI2C_0_LPCG 0x5AC00000 +#define EMVSIM_1_LPCG 0x5A4E0000 +#define EMVSIM_0_LPCG 0x5A4D0000 +#define LPUART_4_LPCG 0x5A4A0000 +#define LPUART_3_LPCG 0x5A490000 +#define LPUART_2_LPCG 0x5A480000 +#define LPUART_1_LPCG 0x5A470000 +#define LPUART_0_LPCG 0x5A460000 +#define LPSPI_3_LPCG 0x5A430000 +#define LPSPI_2_LPCG 0x5A420000 +#define LPSPI_1_LPCG 0x5A410000 +#define LPSPI_0_LPCG 0x5A400000 + +/* Display SS */ +#define DC_0_LPCG 0x56010000 +#define DC_1_LPCG 0x57010000 + +/* LVDS */ +#define DI_LVDS_0_LPCG 0x56243000 +#define DI_LVDS_1_LPCG 0x57243000 + +/* DI HDMI */ +#define DI_HDMI_LPCG 0x56263000 + +/* RX-HDMI */ +#define RX_HDMI_LPCG 0x58263000 + +/* MIPI CSI SS */ +#define MIPI_CSI_0_LPCG 0x58223000 +#define MIPI_CSI_1_LPCG 0x58243000 + +/* MIPI DSI SS */ +#define MIPI_DSI_0_LPCG 0x56223000 +#define MIPI_DSI_1_LPCG 0x57223000 + +/* Imaging SS */ +#define IMG_JPEG_ENC_LPCG 0x585F0000 +#define IMG_JPEG_DEC_LPCG 0x585D0000 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000 +#define IMG_PDMA_7_LPCG 0x58570000 +#define IMG_PDMA_6_LPCG 0x58560000 +#define IMG_PDMA_5_LPCG 0x58550000 +#define IMG_PDMA_4_LPCG 0x58540000 +#define IMG_PDMA_3_LPCG 0x58530000 +#define IMG_PDMA_2_LPCG 0x58520000 +#define IMG_PDMA_1_LPCG 0x58510000 +#define IMG_PDMA_0_LPCG 0x58500000 + +/* HSIO SS */ +#define HSIO_GPIO_LPCG 0x5F100000 +#define HSIO_MISC_LPCG 0x5F0F0000 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000 +#define HSIO_PHY_X1_LPCG 0x5F090000 +#define HSIO_PHY_X2_LPCG 0x5F080000 +#define HSIO_SATA_LPCG 0x5F070000 +#define HSIO_PCIE_X1_LPCG 0x5F060000 +#define HSIO_PCIE_X2_LPCG 0x5F050000 + +/* M4 SS */ +#define M4_0_I2C_LPCG 0x37630000 +#define M4_0_LPUART_LPCG 0x37620000 +#define M4_0_LPIT_LPCG 0x37610000 +#define M4_1_I2C_LPCG 0x3B630000 +#define M4_1_LPUART_LPCG 0x3B620000 +#define M4_1_LPIT_LPCG 0x3B610000 + +/* Audio SS */ +#define AUD_ASRC_0_LPCG 0x59400000 +#define AUD_ESAI_0_LPCG 0x59410000 +#define AUD_SPDIF_0_LPCG 0x59420000 +#define AUD_SPDIF_1_LPCG 0x59430000 +#define AUD_SAI_0_LPCG 0x59440000 +#define AUD_SAI_1_LPCG 0x59450000 +#define AUD_SAI_2_LPCG 0x59460000 +#define AUD_SAI_3_LPCG 0x59470000 +#define AUD_HDMI_RX_SAI_0_LPCG 0x59480000 +#define AUD_HDMI_TX_SAI_0_LPCG 0x59490000 +#define AUD_GPT_5_LPCG 0x594B0000 +#define AUD_GPT_6_LPCG 0x594C0000 +#define AUD_GPT_7_LPCG 0x594D0000 +#define AUD_GPT_8_LPCG 0x594E0000 +#define AUD_GPT_9_LPCG 0x594F0000 +#define AUD_GPT_10_LPCG 0x59500000 +#define AUD_DSP_LPCG 0x59580000 +#define AUD_OCRAM_LPCG 0x59590000 +#define AUD_EDMA_0_LPCG 0x595f0000 +#define AUD_ASRC_1_LPCG 0x59c00000 +#define AUD_ESAI_1_LPCG 0x59c10000 +#define AUD_SAI_6_LPCG 0x59c20000 +#define AUD_SAI_7_LPCG 0x59c30000 +#define AUD_AMIX_LPCG 0x59c40000 +#define AUD_MQS_LPCG 0x59c50000 +#define AUD_ACM_LPCG 0x59c60000 +#define AUD_REC_CLK0_LPCG 0x59d00000 +#define AUD_REC_CLK1_LPCG 0x59d10000 +#define AUD_PLL_CLK0_LPCG 0x59d20000 +#define AUD_PLL_CLK1_LPCG 0x59d30000 +#define AUD_MCLKOUT0_LPCG 0x59d50000 +#define AUD_MCLKOUT1_LPCG 0x59d60000 +#define AUD_EDMA_1_LPCG 0x59df0000 + +/* Connectivity SS */ +#define USDHC_0_LPCG 0x5B200000 +#define USDHC_1_LPCG 0x5B210000 +#define USDHC_2_LPCG 0x5B220000 +#define ENET_0_LPCG 0x5B230000 +#define ENET_1_LPCG 0x5B240000 +#define DTCP_LPCG 0x5B250000 +#define MLB_LPCG 0x5B260000 +#define USB_2_LPCG 0x5B270000 +#define USB_3_LPCG 0x5B280000 +#define NAND_LPCG 0x5B290000 +#define EDMA_LPCG 0x5B2A0000 + +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + +/* CM41 SS */ +#define CM41_I2C_LPCG 0x3B630000 + +#endif diff --git a/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h b/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h new file mode 100644 index 0000000..074b208 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#ifndef _SC_LPCG_H +#define _SC_LPCG_H + +/*LSIO SS */ +#define PWM_0_LPCG 0x5D400000 +#define PWM_1_LPCG 0x5D410000 +#define PWM_2_LPCG 0x5D420000 +#define PWM_3_LPCG 0x5D430000 +#define PWM_4_LPCG 0x5D440000 +#define PWM_5_LPCG 0x5D450000 +#define PWM_6_LPCG 0x5D460000 +#define PWM_7_LPCG 0x5D470000 +#define GPIO_0_LPCG 0x5D480000 +#define GPIO_1_LPCG 0x5D490000 +#define GPIO_2_LPCG 0x5D4A0000 +#define GPIO_3_LPCG 0x5D4B0000 +#define GPIO_4_LPCG 0x5D4C0000 +#define GPIO_5_LPCG 0x5D4D0000 +#define GPIO_6_LPCG 0x5D4E0000 +#define GPIO_7_LPCG 0x5D4F0000 +#define FSPI_0_LPCG 0x5D520000 +#define FSPI_1_LPCG 0x5D530000 +#define GPT_0_LPCG 0x5D540000 +#define GPT_1_LPCG 0x5D550000 +#define GPT_2_LPCG 0x5D560000 +#define GPT_3_LPCG 0x5D570000 +#define GPT_4_LPCG 0x5D580000 +#define OCRAM_LPCG 0x5D590000 +#define KPP_LPCG 0x5D5A0000 +#define ROMCP_LPCG 0x5D500000 +#define MU_5A_LPCG 0x5D600000 +#define MU_6A_LPCG 0x5D610000 +#define MU_7A_LPCG 0x5D620000 +#define MU_8A_LPCG 0x5D630000 +#define MU_9A_LPCG 0x5D640000 +#define MU_10A_LPCG 0x5D650000 +#define MU_11A_LPCG 0x5D660000 +#define MU_12A_LPCG 0x5D670000 +#define MU_13A_LPCG 0x5D680000 + +/* HSIO SS */ +#define CRR_5_LPCG 0x5F0F0000 +#define CRR_4_LPCG 0x5F0E0000 +#define CRR_3_LPCG 0x5F0D0000 +#define CRR_2_LPCG 0x5F0C0000 +#define CRR_1_LPCG 0x5F0B0000 +#define CRR_0_LPCG 0x5F0A0000 +#define PHY_1_LPCG 0x5F090000 +#define PHY_2_LPCG 0x5F080000 +#define SATA_0_LPCG 0x5F070000 +#define PCIE_B_LPCG 0x5F060000 +#define PCIE_A_LPCG 0x5F050000 + +/* DMA SS */ +#define FLEX_CAN_2_LPCG 0x5ACF0000 +#define FLEX_CAN_1_LPCG 0x5ACE0000 +#define FLEX_CAN_0_LPCG 0x5ACD0000 +#define FTM_1_LPCG 0x5ACB0000 +#define FTM_0_LPCG 0x5ACA0000 +#define ADC_0_LPCG 0x5AC80000 +#define LPI2C_3_LPCG 0x5AC30000 +#define LPI2C_2_LPCG 0x5AC20000 +#define LPI2C_1_LPCG 0x5AC10000 +#define LPI2C_0_LPCG 0x5AC00000 +#define PWM_LPCG 0x5A590000 +#define LCD_LPCG 0x5A580000 +#define LPUART_3_LPCG 0x5A490000 +#define LPUART_2_LPCG 0x5A480000 +#define LPUART_1_LPCG 0x5A470000 +#define LPUART_0_LPCG 0x5A460000 +#define LPSPI_3_LPCG 0x5A430000 +#define LPSPI_2_LPCG 0x5A420000 +#define LPSPI_1_LPCG 0x5A410000 +#define LPSPI_0_LPCG 0x5A400000 + +/* Display SS */ +#define DC_0_LPCG 0x56010000 +#define DC_1_LPCG 0x57010000 + +/* LVDS */ +#define DI_LVDS_0_LPCG 0x56243000 +#define DI_LVDS_1_LPCG 0x57243000 + +/* DI HDMI */ +#define DI_HDMI_LPCG 0x56263000 + +/* RX-HDMI */ +#define RX_HDMI_LPCG 0x58263000 + +/* MIPI CSI SS */ +#define MIPI_CSI_0_LPCG 0x58223000 +#define MIPI_CSI_1_LPCG 0x58243000 + +/* PARALLEL CSI SS */ +#define PARALLEL_CSI_LPCG 0x58263000 + +/* Display MIPI SS */ +#define DI_MIPI0_LPCG 0x56223000 +#define DI_MIPI1_LPCG 0x56243000 + +/* Imaging SS */ +#define IMG_JPEG_ENC_LPCG 0x585F0000 +#define IMG_JPEG_DEC_LPCG 0x585D0000 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000 +#define IMG_PDMA_7_LPCG 0x58570000 +#define IMG_PDMA_6_LPCG 0x58560000 +#define IMG_PDMA_5_LPCG 0x58550000 +#define IMG_PDMA_4_LPCG 0x58540000 +#define IMG_PDMA_3_LPCG 0x58530000 +#define IMG_PDMA_2_LPCG 0x58520000 +#define IMG_PDMA_1_LPCG 0x58510000 +#define IMG_PDMA_0_LPCG 0x58500000 + +/* HSIO SS */ +#define HSIO_GPIO_LPCG 0x5F100000 +#define HSIO_MISC_LPCG 0x5F0F0000 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000 +#define HSIO_PHY_X1_LPCG 0x5F090000 +#define HSIO_PHY_X2_LPCG 0x5F080000 +#define HSIO_SATA_LPCG 0x5F070000 +#define HSIO_PCIE_X1_LPCG 0x5F060000 +#define HSIO_PCIE_X2_LPCG 0x5F050000 + +/* M4 SS */ +#define M4_0_I2C_LPCG 0x37630000 +#define M4_0_LPUART_LPCG 0x37620000 +#define M4_0_LPIT_LPCG 0x37610000 +#define M4_1_I2C_LPCG 0x3B630000 +#define M4_1_LPUART_LPCG 0x3B620000 +#define M4_1_LPIT_LPCG 0x3B610000 + +/* Audio SS */ +#define AUD_ASRC_0_LPCG 0x59400000 +#define AUD_ESAI_0_LPCG 0x59410000 +#define AUD_SPDIF_0_LPCG 0x59420000 +#define AUD_SAI_0_LPCG 0x59440000 +#define AUD_SAI_1_LPCG 0x59450000 +#define AUD_SAI_2_LPCG 0x59460000 +#define AUD_SAI_3_LPCG 0x59470000 +#define AUD_GPT_5_LPCG 0x594B0000 +#define AUD_GPT_6_LPCG 0x594C0000 +#define AUD_GPT_7_LPCG 0x594D0000 +#define AUD_GPT_8_LPCG 0x594E0000 +#define AUD_GPT_9_LPCG 0x594F0000 +#define AUD_GPT_10_LPCG 0x59500000 +#define AUD_DSP_LPCG 0x59580000 +#define AUD_OCRAM_LPCG 0x59590000 +#define AUD_EDMA_0_LPCG 0x595f0000 +#define AUD_ASRC_1_LPCG 0x59c00000 +#define AUD_SAI_4_LPCG 0x59c20000 +#define AUD_SAI_5_LPCG 0x59c30000 +#define AUD_AMIX_LPCG 0x59c40000 +#define AUD_MQS_LPCG 0x59c50000 +#define AUD_ACM_LPCG 0x59c60000 +#define AUD_REC_CLK0_LPCG 0x59d00000 +#define AUD_REC_CLK1_LPCG 0x59d10000 +#define AUD_PLL_CLK0_LPCG 0x59d20000 +#define AUD_PLL_CLK1_LPCG 0x59d30000 +#define AUD_MCLKOUT0_LPCG 0x59d50000 +#define AUD_MCLKOUT1_LPCG 0x59d60000 +#define AUD_EDMA_1_LPCG 0x59df0000 + +/* Connectivity SS */ +#define USDHC_0_LPCG 0x5B200000 +#define USDHC_1_LPCG 0x5B210000 +#define USDHC_2_LPCG 0x5B220000 +#define ENET_0_LPCG 0x5B230000 +#define ENET_1_LPCG 0x5B240000 +#define DTCP_LPCG 0x5B250000 +#define MLB_LPCG 0x5B260000 +#define USB_2_LPCG 0x5B270000 +#define USB_3_LPCG 0x5B280000 +#define NAND_LPCG 0x5B290000 +#define EDMA_LPCG 0x5B2A0000 + +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + +#endif diff --git a/arch/arm/include/asm/arch-imx8/lpcg.h b/arch/arm/include/asm/arch-imx8/lpcg.h new file mode 100644 index 0000000..9ba4bb4 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/lpcg.h @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#ifndef __ASM_ARCH_IMX8_LPCG_H__ +#define __ASM_ARCH_IMX8_LPCG_H__ + +#if defined(CONFIG_IMX8QM) +#include "imx8qm_lpcg.h" +#elif defined(CONFIG_IMX8QXP) +#include "imx8qxp_lpcg.h" +#else +#error "No lpcg header" +#endif + +void lpcg_clock_off(u32 lpcg_addr, u8 clk); +void lpcg_clock_on(u32 lpcg_addr, u8 clk); +void lpcg_clock_autogate(u32 lpcg_addr, u8 clk); +bool lpcg_is_clock_on(u32 lpcg_addr, u8 clk); +void lpcg_all_clock_off(u32 lpcg_addr); +void lpcg_all_clock_on(u32 lpcg_addr); +void lpcg_all_clock_autogate(u32 lpcg_addr); + +#endif /* __ASM_ARCH_IMX8_LPCG_H__ */ diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 31ad169..e23f84f 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpu.o iomux.o +obj-y += cpu.o iomux.o lpcg.o diff --git a/arch/arm/mach-imx/imx8/lpcg.c b/arch/arm/mach-imx/imx8/lpcg.c new file mode 100644 index 0000000..621b871 --- /dev/null +++ b/arch/arm/mach-imx/imx8/lpcg.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/lpcg.h> + +#define LPCG_CLOCK_MASK 0x3U +#define LPCG_CLOCK_OFF 0x0U +#define LPCG_CLOCK_ON 0x2U +#define LPCG_CLOCK_AUTO 0x3U +#define LPCG_CLOCK_STOP 0x8U + +#define LPCG_ALL_CLOCK_OFF 0x00000000U +#define LPCG_ALL_CLOCK_ON 0x22222222U +#define LPCG_ALL_CLOCK_AUTO 0x33333333U +#define LPCG_ALL_CLOCK_STOP 0x88888888U + +static inline void lpcg_write(u32 lpcgVal, ulong lpcg_addr) +{ + /* + * Write twice with 4x DSC clock cycles (40x IPS clock cycles) interval + * to work around LPCG issue + */ + writel(lpcgVal, lpcg_addr); + udelay(10); /* 10us is enough. Worst case is 40x IPS cycle (200Mhz) */ + writel(lpcgVal, lpcg_addr); + udelay(10); +} + +void lpcg_clock_off(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_OFF) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +void lpcg_clock_on(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_ON) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +bool lpcg_is_clock_on(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + lpcgVal = (lpcgVal >> (clk * 4U)) & (u32)(LPCG_CLOCK_MASK); + + if (lpcgVal == LPCG_CLOCK_ON) + return true; + + return false; +} + +void lpcg_clock_autogate(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_AUTO) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +void lpcg_all_clock_off(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_OFF, (ulong)lpcg_addr); +} + +void lpcg_all_clock_on(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_ON, (ulong)lpcg_addr); + + /* Wait for clocks to start */ + while ((readl((ulong)lpcg_addr) & LPCG_ALL_CLOCK_STOP) != 0U) + { + } +} + +void lpcg_all_clock_autogate(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_AUTO, (ulong)lpcg_addr); +} -- 2.7.4

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Re: [U-Boot] [PATCH] rpi3: Enable verified boot from FIT image
by Jun Nie 17 Sep '19

17 Sep '19

Matthias Brugger <mbrugger(a)suse.com> 于2019年7月31日周三下午4:05写道： > > > > On 11/07/2019 05:55, Jun Nie wrote: > > Enable verified boot from FIT image with select configs > > and specify boot script image node in FIT image, the FIT > > image is verified before it is run. > > > > Code that reusing dtb in firmware is disabled, so that > > the dtb with pubic key packed in u-boot.bin can be used > > to verify the signature of next stage FIT image. > > > > Signed-off-by: Jun Nie <jun.nie(a)linaro.org> > > --- > > board/raspberrypi/rpi/rpi.c | 6 ++++++ > > include/configs/rpi.h | 15 ++++++++++++++- > > 2 files changed, 20 insertions(+), 1 deletion(-) > > > > diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c > > index 617c892..950ee84 100644 > > --- a/board/raspberrypi/rpi/rpi.c > > +++ b/board/raspberrypi/rpi/rpi.c > > @@ -297,6 +297,7 @@ static void set_fdtfile(void) > > env_set("fdtfile", fdtfile); > > } > > > > +#ifndef CONFIG_FIT_SIGNATURE > > /* > > * If the firmware provided a valid FDT at boot time, let's expose it in > > * ${fdt_addr} so it may be passed unmodified to the kernel. > > @@ -311,6 +312,7 @@ static void set_fdt_addr(void) > > > > env_set_hex("fdt_addr", fw_dtb_pointer); > > } > > +#endif > > > > /* > > * Prevent relocation from stomping on a firmware provided FDT blob. > > @@ -393,7 +395,9 @@ static void set_serial_number(void) > > > > int misc_init_r(void) > > { > > +#ifndef CONFIG_FIT_SIGNATURE > > set_fdt_addr(); > > +#endif > > set_fdtfile(); > > set_usbethaddr(); > > #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG > > @@ -470,6 +474,7 @@ int board_init(void) > > return bcm2835_power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD); > > } > > > > +#ifndef CONFIG_FIT_SIGNATURE > > /* > > * If the firmware passed a device tree use it for U-Boot. > > */ > > @@ -479,6 +484,7 @@ void *board_fdt_blob_setup(void) > > return NULL; > > return (void *)fw_dtb_pointer; > > } > > +#endif > > Just to get this clear we need this because we want to pass the device tree via > OF_SEPARATE, correct? You are right. U-boot need to read he signature from dtb. > > > > > int ft_board_setup(void *blob, bd_t *bd) > > { > > diff --git a/include/configs/rpi.h b/include/configs/rpi.h > > index f76c7d1..ba91205 100644 > > --- a/include/configs/rpi.h > > +++ b/include/configs/rpi.h > > @@ -180,11 +180,24 @@ > > > > #include <config_distro_bootcmd.h> > > > > +#ifdef CONFIG_FIT_SIGNATURE > > +#define FIT_BOOT_CMD \ > > + "boot_a_script=" \ > > + "load ${devtype} ${devnum}:${distro_bootpart} " \ > > + "${scriptaddr} ${prefix}${script}; " \ > > + "iminfo ${scriptaddr};" \ > > + "if test $? -eq 1; then reset; fi;" \ > > + "source ${scriptaddr}:bootscr\0" > > +#else > > +#define FIT_BOOT_CMD "" > > +#endif > > + > > Doesn't this overwrite the boot_a_script in distro_bootcmd? > > Would it make sense to add FIT booting to the distro boot command? > > Regards, > Matthias Yes, it overwrite the boot_a_script in distro_bootcmd. It is make sense to add this to the distro boot command. I can send another patch to move these lines to common code later. > > > #define CONFIG_EXTRA_ENV_SETTINGS \ > > "dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \ > > ENV_DEVICE_SETTINGS \ > > ENV_MEM_LAYOUT_SETTINGS \ > > - BOOTENV > > + BOOTENV \ > > + FIT_BOOT_CMD > > > > > > #endif > >

5 9

[U-Boot] nxp: HABv4 secure boot on iMX7 NAND broken
by Igor Opaniuk 16 Sep '19

16 Sep '19

Hi folks, Just curious if you ever faced any issues with HABv4 based secure boot on iMX7 SoC-based boards + NAND + mainline U-Boot (although it works perfectly when booting from eMMC). I'm currently playing with it on Colibri iMX7 NAND version, following all steps from [1], (colibri_imx7_defconfig, where CONFIG_SECURE_BOOT=y and CONFIG_FSL_CAAM=y, without these two options enabled it's booting ok) and facing the same issue as explained in one of NXP forum threads [2]. Taking into account that default BootROM doesn't provide any output at all to the serial console it is like looking for a needle in a haystack. Do you have any ideas about possible pitfalls/what could be missing in this puzzle? Or at least some hints where to look into? Thanks in advance! [1] https://gitlab.denx.de/u-boot/u-boot/blob/master/doc/imx/habv4/guides/mx6_m… [2] https://community.nxp.com/thread/380130 -- Best regards - Freundliche Grüsse - Meilleures salutations Igor Opaniuk mailto: igor.opaniuk(a)gmail.com skype: igor.opanyuk +380 (93) 836 40 67 http://ua.linkedin.com/in/iopaniuk

3 9

[U-Boot] [usb dwc3] xHCI driver -- a hint needed.
by Yuri Frolov 11 Sep '19

11 Sep '19

Hi, I've been trying to bring up a dwc3 usb controller included in 32-bit MIPS chip. Usb is the one port usb2.0 host module, compliant with xHCI Revision 1.0, UTMI+ Low Pin interface (ULPI) Revision 1.1 and AMBA AXI Protocol specification. g_snpsid register reports 0x5533290a revision. It's verified, that linux kernel support is ok, usb is fully functional. axi { <...> usb@1F04D050 { compatible = "be,baikal-dwc3"; reg = <0x1f04d050 0x4>; interrupts = <0x0 0x45 0x4>; #address-cells = <0x1>; #size-cells = <0x1>; clocks = <0xf 0x0>; clock-names = "usb"; ranges; status = "okay"; dwc3@1F100000 { compatible = "snps,dwc3", "synopsys,dwc3", "generic-xhci"; reg = <0x1f100000 0x10000>; interrupts = <0x0 0x44 0x4>; dr_mode = "host"; tx-fifo-resize; maximum-speed = "high-speed"; }; }; }; whereas in u-boot 'usb start' fails on hub initialization (as I can see): Any ideas why this could happen?.. Any direction where to look at? Any suggestions will be greatly appreciated. # usb start (Re)start USB... USB0: dwc3_reg->g_snpsid: 0x5533290a Register 1000140 NbrPorts 1 Starting the controller USB XHCI 1.00 scanning bus 0 for devices... New Device 0 set address 1 usb_control_msg: request: 0x5, requesttype: 0x0, value 0x1 index 0x0 length 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 0x12 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 0x9 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 0x1F get_conf_no 0 Result 25, wLength 31 if 0, ep 0 ##EP epmaxpacketin[1] = 8 set configuration 1 usb_control_msg: request: 0x9, requesttype: 0x0, value 0x1 index 0x0 length 0x0 new device strings: Mfr=1, Product=2, SerialNumber=0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x300 index 0x0 length 0xFF USB device number 1 default language ID 0x409 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x301 index 0x409 length 0xFF usb_control_msg: request: 0x6, requesttype: 0x80, value 0x302 index 0x409 length 0xFF Manufacturer U-Boot Product XHCI Host Controller SerialNumber USB hub found usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2A00 index 0x0 length 0x4 usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2A00 index 0x0 length 0xC 1 ports detected ganged power switching standalone hub individual port over-current protection TT requires at most 8 FS bit times (666 ns) power on to power good time: 20ms hub controller current requirement: 0mA port 1 is removable usb_control_msg: request: 0x0, requesttype: 0xA0, value 0x0 index 0x0 length 0x4 get_hub_status returned status 1, change 801 local power source is lost (inactive) no over-current condition exists enabling power on all ports usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x1 length 0x0 port 1 returns 0 devnum=1 poweron: query_delay=100 connect_timeout=1100 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 Port 1 Status 101 Change 1 devnum=1 port=1: USB dev found usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 portstatus 101, change 1, 12 Mb/s usb_control_msg: request: 0x1, requesttype: 0x23, value 0x10 index 0x1 length 0x0 usb_hub_port_reset: resetting port 1... usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x1 length 0x0 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 portstatus 111, change 0, 12 Mb/s STAT_C_CONNECTION = 0 STAT_CONNECTION = 1 USB_PORT_STAT_ENABLE 0 usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x1 length 0x0 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 portstatus 503, change 10, 480 Mb/s STAT_C_CONNECTION = 0 STAT_CONNECTION = 1 USB_PORT_STAT_ENABLE 1 usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x1 length 0x0 New Device 1 XHCI timeout on event type 33... cannot recover. BUG: failure at drivers/usb/host/xhci-ring.c:474/xhci_wait_for_event()! BUG! Reset CPU by CPC Here is the drivers/usb/host/xhci-baikal.c: #include <common.h> #include <usb.h> #include <linux/errno.h> #include <linux/compat.h> #include <linux/usb/dwc3.h> #include <linux/usb/xhci-omap.h> #include "xhci.h" /* Declare global data pointer */ DECLARE_GLOBAL_DATA_PTR; struct baikal_xhci { struct xhci_hccr *hcd; struct dwc3 *dwc3_reg; }; static struct baikal_xhci baikal; int __attribute__((weak)) board_usb_init(int index, enum usb_init_type init); static int baikal_xhci_core_init(struct baikal_xhci *baikal) { int ret = 0; ret = dwc3_core_init(baikal->dwc3_reg); if (ret) { debug("%s:failed to initialize core\n", __func__); return ret; } /* We are hard-coding DWC3 core to Host Mode */ dwc3_set_mode(baikal->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); return ret; } static void baikal_xhci_core_exit(struct baikal_xhci *baikal) { } int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) { struct baikal_xhci *ctx = &baikal; int ret = 0; ctx->hcd = (struct xhci_hccr *)CONFIG_USB_XHCI_BAIKAL_BASE; ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); ret = board_usb_init(index, USB_INIT_HOST); if (ret != 0) { puts("Failed to initialize board for USB\n"); return ret; } ret = baikal_xhci_core_init(ctx); if (ret < 0) { puts("Failed to initialize xhci\n"); return ret; } *hccr = (struct xhci_hccr *)(CONFIG_USB_XHCI_BAIKAL_BASE); *hcor = (struct xhci_hcor *)((uint32_t) *hccr + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); debug("baikal-xhci: init hccr %x and hcor %x hc_length %d\n", (uint32_t)*hccr, (uint32_t)*hcor, (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); return ret; } void xhci_hcd_stop(int index) { } TIA, Yuri

4 6

[U-Boot] [u-boot][xhci] Dealing with XHCI controllers with spurious success
by Aaron Williams 11 Sep '19

11 Sep '19

Hi All, I'm running into a problem with the XHCI driver on our SOC where I am getting spurious success TRBs after a short packet response. In this particular case, the driver for a USB network controller has a receive buffer that crosses a 64K boundary. This results in two TRBs being created to handle this with the first TRB having the chain and ISP bits set and the second having the IOC and ISP bits set as expected in this case. The network controller has a short response (as is expected) followed by a success response event (which is also valid) for the second TRB. The U-Boot XHCI driver, however, does not handle this properly. The xhci_bulk_tx function only looks at the first response and does not dequeue the second success response. The problem is when the next transaction occurs it dequeues the success response from the previous transaction so the responses events no longer match the TRBs. At some point the network driver goes from receive to transmit and at this point the driver panics because the event is still a response from a previous receive event and not the transmit event causing the endpoints to mismatch. This only happens in the two TRB case due to the receive buffer crossing a 64K boundary. The short packet response points to the first TRB and the success points to the second TRB. In the Linux driver I see the XHCI_SPURIOUS_SUCCESS flag is available. I'm not certain if this applies to our hardware or not. In any case, this could be solved in one of two ways. One way to solve this is to make sure that any driver where a short response is possible to not have the buffer cross a 64K boundary. The other (and correct) solution is to have the XHCI driver handle this case. If a short packet response is received and there are multiple TRBs involved, check if there is an additional success response that points to the last TRB. To me it seems valid that the two response events are received. The specification only says that there will be one response if the TRB has both the ISP and IOC bits set, but this is not the case. I came across this commit in the Linux kernel which seems to address this case: https://kernel.opensuse.org/cgit/kernel/commit/?id=ad808333d8201d53075a11bc… -Aaron

2 4

[U-Boot] [PATCH] regulator: fixed: Modify enable-active-high behavior
by Patrice Chotard 10 Sep '19

10 Sep '19

Regulator should not be enabled at probe time if regulator-boot-on property is not in the dt node. "enable-active-high" property is only used to indicate the GPIO polarity. See kernel documentation : - Documentation/devicetree/bindings/regulator/fixed-regulator.yaml - Documentation/devicetree/bindings/regulator/gpio-regulator.yaml Signed-off-by: Christophe Kerello <christophe.kerello(a)st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- drivers/power/regulator/regulator_common.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c index 3dabbe2a85..2e8a083c75 100644 --- a/drivers/power/regulator/regulator_common.c +++ b/drivers/power/regulator/regulator_common.c @@ -15,7 +15,9 @@ int regulator_common_ofdata_to_platdata(struct udevice *dev, int flags = GPIOD_IS_OUT; int ret; - if (dev_read_bool(dev, "enable-active-high")) + if (!dev_read_bool(dev, "enable-active-high")) + flags |= GPIOD_ACTIVE_LOW; + if (uc_pdata->boot_on) flags |= GPIOD_IS_OUT_ACTIVE; /* Get optional enable GPIO desc */ -- 2.17.1

3 3

[U-Boot] [PATCH v1 1/7] mmc: fsl_esdhc: Add peripheral clock support
by Yinbo Zhu 10 Sep '19

10 Sep '19

This patch is to add peripheral clock support Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- .../armv8/fsl-layerscape/fsl_lsch2_speed.c | 49 ++++++++++++------- .../armv8/fsl-layerscape/fsl_lsch3_speed.c | 45 ++++++++++++++++- .../asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- .../asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 78 insertions(+), 19 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 9ece4b90e6..23391398ed 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -22,10 +22,12 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#if (defined(CONFIG_FSL_ESDHC) &&\ - defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\ - defined(CONFIG_SYS_DPAA_FMAN) - +/* rcw_tmp is needed to get FMan clock, or to get cluster group A + * mux 2 clock for LS1043A/LS1046A. + */ +#if defined(CONFIG_SYS_DPAA_FMAN) || \ + defined(CONFIG_TARGET_LS1046ARDB) || \ + defined(CONFIG_TARGET_LS1043ARDB) u32 rcw_tmp; #endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); @@ -122,32 +124,32 @@ void get_sys_info(struct sys_info *sys_info) } #endif +#ifdef CONFIG_FSL_ESDHC #define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SHIFT 0 -#ifdef CONFIG_FSL_ESDHC -#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK +#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB) rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { case 1: - sys_info->freq_sdhc = freq_c_pll[1]; + sys_info->freq_cga_m2 = freq_c_pll[1]; break; +#if defined(CONFIG_TARGET_LS1046ARDB) case 2: - sys_info->freq_sdhc = freq_c_pll[1] / 2; + sys_info->freq_cga_m2 = freq_c_pll[1] / 2; break; +#endif case 3: - sys_info->freq_sdhc = freq_c_pll[1] / 3; + sys_info->freq_cga_m2 = freq_c_pll[1] / 3; break; +#if defined(CONFIG_TARGET_LS1046ARDB) case 6: - sys_info->freq_sdhc = freq_c_pll[0] / 2; + sys_info->freq_cga_m2 = freq_c_pll[0] / 2; break; +#endif default: - printf("Error: Unknown ESDHC clock select!\n"); + printf("Error: Unknown peripheral clock select!\n"); break; } -#else - sys_info->freq_sdhc = (sys_info->freq_systembus / - CONFIG_SYS_FSL_PCLK_DIV) / - CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif #endif @@ -183,9 +185,22 @@ int get_clocks(void) gd->mem_clk = sys_info.freq_ddrbus; #ifdef CONFIG_FSL_ESDHC - gd->arch.sdhc_clk = sys_info.freq_sdhc; +#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) +#if defined(CONFIG_TARGET_LS1046ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; +#endif +#if defined(CONFIG_TARGET_LS1043ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2; +#endif +#if defined(CONFIG_TARGET_LS1012ARDB) + gd->arch.sdhc_clk = sys_info.freq_systembus; +#endif +#else + gd->arch.sdhc_clk = (sys_info.freq_systembus / + CONFIG_SYS_FSL_PCLK_DIV) / + CONFIG_SYS_FSL_SDHC_CLK_DIV; +#endif #endif - if (gd->cpu_clk != 0) return 0; else diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index a5540f2b9d..b3e67321b4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -64,6 +64,9 @@ void get_sys_info(struct sys_info *sys_info) }; uint i, cluster; +#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) + uint rcw_tmp; +#endif uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; @@ -127,8 +130,39 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_localbus = sys_info->freq_systembus / CONFIG_SYS_FSL_IFC_CLK_DIV; #endif -} +#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#define HWA_CGA_M2_CLK_SEL 0x00380000 +#define HWA_CGA_M2_CLK_SHIFT 19 + rcw_tmp = in_le32(&gur->rcwsr[5]); + switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { + case 1: + sys_info->freq_cga_m2 = freq_c_pll[1]; + break; + case 2: + sys_info->freq_cga_m2 = freq_c_pll[1] / 2; + break; + case 3: + sys_info->freq_cga_m2 = freq_c_pll[1] / 3; + break; + case 4: + sys_info->freq_cga_m2 = freq_c_pll[1] / 4; + break; + case 6: + sys_info->freq_cga_m2 = freq_c_pll[0] / 2; + break; + case 7: + sys_info->freq_cga_m2 = freq_c_pll[0] / 3; + break; + default: + printf("Error: Unknown peripheral clock select!\n"); + break; + } +#endif +#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB) + sys_info->freq_cga_m2 = sys_info->freq_systembus; +#endif +} int get_clocks(void) { @@ -141,7 +175,16 @@ int get_clocks(void) gd->arch.mem2_clk = sys_info.freq_ddrbus2; #endif #if defined(CONFIG_FSL_ESDHC) +#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) +#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; +#endif +#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2; +#endif +#else gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV; +#endif #endif /* defined(CONFIG_FSL_ESDHC) */ if (gd->cpu_clk != 0) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index b4b7c3492e..3a59abb10e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -180,7 +180,7 @@ struct sys_info { unsigned long freq_systembus; unsigned long freq_ddrbus; unsigned long freq_localbus; - unsigned long freq_sdhc; + unsigned long freq_cga_m2; #ifdef CONFIG_SYS_DPAA_FMAN unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index ee9b33becf..3cea71ad75 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -255,6 +255,7 @@ struct sys_info { /* frequency of platform PLL */ unsigned long freq_systembus; unsigned long freq_ddrbus; + unsigned long freq_cga_m2; #ifdef CONFIG_SYS_FSL_HAS_DP_DDR unsigned long freq_ddrbus2; #endif -- 2.17.1

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[U-Boot] Regression after "distro: not taint environment variables if possible"
by Nuno Gonçalves 09 Sep '19

09 Sep '19

Hi, I found out that my Beaglebone didn't boot after: https://github.com/u-boot/u-boot/commit/13dd6665ed18f72380ca596931d609bc108… I digged out the reason that this patch makes devnum a local variable, and it ends up shadowed by other code that sets devnum as a env variable. For example to boot on the beaglebone I had to remove the setenv as in the patch below. This only fixes for my board. Many other will likely have regressions. Fixing it for all boards in a reliable way I think is very complex, unless the strategy is to wait for board maintainers to fix it as they need it, but I wonder how many latent bugs this will create for corner boot cases. Maybe this change is not worth it? Thanks, Nuno diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h index 785fc15345..bb4af0a3d5 100644 --- a/include/environment/ti/mmc.h +++ b/include/environment/ti/mmc.h @@ -56,7 +56,7 @@ "bootz; " \ "fi;\0" \ "mmcboot=mmc dev ${mmcdev}; " \ - "setenv devnum ${mmcdev}; " \ + "devnum=${mmcdev}; " \ "setenv devtype mmc; " \ "if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \

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[U-Boot] [PATCH v2 0/4] NC-SI PHY Support
by Samuel Mendoza-Jonas 09 Sep '19

09 Sep '19

This series introduces support for the NC-SI protocol to u-boot, functionality which so far has only been available in vendor trees. NC-SI (Network Controller Sideband Interface) is a protocol to manage a sideband connection to a proper network interface, for example a BMC (Baseboard Management Controller) sharing the NIC of the host system. Probing and configuration occurs by communicating with the "remote" NIC via NC-SI control frames (Ethernet header 0x88f8). Since the RFC[0] the changes have been split out into a few different patches to make the overall changes more obvious. Additionally a few small improvements have been added including adding a check to see if NC-SI is already configured, and marking the PHY bus "reset" as invalid since it does not define a bus. An example of NC-SI setup before a normal network command: => dhcp net_loop: configuring NCSI first ethernet@1e660000: link up, 100 Mbps full-duplex mac:0c:c4:7a:d5:48:43 NCSI: probing channels NCSI: configuring channel 0 NCSI: configuration done! BOOTP broadcast 1 BOOTP broadcast 2 DHCP client bound to address 10.61.161.188 (255 ms) [0]: https://patchwork.ozlabs.org/patch/1107087/ Changes in v2: - Fix endianess issue when setting MAC address - Make checksum offsets easier to read - Instantiate per-phy ncsi_priv structures - Update ncsi command help text - Used update ncsi-pkt.h version to include SPDX header Samuel Mendoza-Jonas (4): phy: Add support for the NC-SI protocol phy: Include NC-SI in phy setup net/ftgmac100: Add NC-SI mode support net: NC-SI setup and handling cmd/Kconfig | 8 + cmd/net.c | 18 + drivers/net/ftgmac100.c | 39 +- drivers/net/phy/Kconfig | 4 + drivers/net/phy/Makefile | 1 + drivers/net/phy/ncsi.c | 896 +++++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 7 + include/net.h | 3 +- include/net/ncsi-pkt.h | 442 +++++++++++++++++++ include/net/ncsi.h | 14 + include/phy.h | 12 + include/phy_interface.h | 2 + net/net.c | 27 +- 13 files changed, 1461 insertions(+), 12 deletions(-) create mode 100644 drivers/net/phy/ncsi.c create mode 100644 include/net/ncsi-pkt.h create mode 100644 include/net/ncsi.h -- 2.21.0

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[U-Boot] [PATCH 1/3] spi: Add spi_write_then_read
by Jagan Teki 07 Sep '19

07 Sep '19

Add support for SPI synchronous write followed by read, this is common interface call from spi-nor to spi drivers. Reviewed-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/spi/spi-uclass.c | 24 ++++++++++++++++++++++++ include/spi.h | 20 ++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 88cb2a1262..76c4b53c16 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -108,6 +108,30 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, return dm_spi_xfer(slave->dev, bitlen, dout, din, flags); } +int spi_write_then_read(struct spi_slave *slave, const u8 *opcode, + size_t n_opcode, const u8 *txbuf, u8 *rxbuf, + size_t n_buf) +{ + unsigned long flags = SPI_XFER_BEGIN; + int ret; + + if (n_buf == 0) + flags |= SPI_XFER_END; + + ret = spi_xfer(slave, n_opcode * 8, opcode, NULL, flags); + if (ret) { + debug("spi: failed to send command (%zu bytes): %d\n", + n_opcode, ret); + } else if (n_buf != 0) { + ret = spi_xfer(slave, n_buf * 8, txbuf, rxbuf, SPI_XFER_END); + if (ret) + debug("spi: failed to transfer %zu bytes of data: %d\n", + n_buf, ret); + } + + return ret; +} + #if !CONFIG_IS_ENABLED(OF_PLATDATA) static int spi_child_post_bind(struct udevice *dev) { diff --git a/include/spi.h b/include/spi.h index 378594163b..5eec0c4775 100644 --- a/include/spi.h +++ b/include/spi.h @@ -248,6 +248,26 @@ int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen); int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags); +/** + * spi_write_then_read - SPI synchronous write followed by read + * + * This performs a half duplex transaction in which the first transaction + * is to send the opcode and if the length of buf is non-zero then it start + * the second transaction as tx or rx based on the need from respective slave. + * + * @slave: The SPI slave device with which opcode/data will be exchanged + * @opcode: opcode used for specific transfer + * @n_opcode: size of opcode, in bytes + * @txbuf: buffer into which data to be written + * @rxbuf: buffer into which data will be read + * @n_buf: size of buf (whether it's [tx|rx]buf), in bytes + * + * Returns: 0 on success, not 0 on failure + */ +int spi_write_then_read(struct spi_slave *slave, const u8 *opcode, + size_t n_opcode, const u8 *txbuf, u8 *rxbuf, + size_t n_buf); + /* Copy memory mapped data */ void spi_flash_copy_mmap(void *data, void *offset, size_t len); -- 2.18.0.321.gffc6fa0e3

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