February 2019 - U-Boot

[U-Boot] [PATCH] lib/crc16: use non-C99 loop style
by Thomas Petazzoni 14 Feb '19

14 Feb '19

Commit 51c2345bd24837f9f67f16268da6dc71573f1325 ("Roll CRC16-CCITT into the hash infrastructure") has modified the crc16 code by adding a C99-style loop where the loop iterator is declared inside the for() statement. This breaks the build with old compiler such as gcc 4.7, that do not default to C99: ./tools/../lib/crc16.c: In function 'crc16_ccitt': ./tools/../lib/crc16.c:70:2: error: 'for' loop initial declarations are only allowed in C99 mode ./tools/../lib/crc16.c:70:2: note: use option -std=c99 or -std=gnu99 to compile your code Switching to the regular coding style used in the rest of U-Boot allows to fix this build issue. Signed-off-by: Thomas Petazzoni <thomas.petazzoni(a)bootlin.com> --- lib/crc16.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/crc16.c b/lib/crc16.c index f46ba727c9..89d2cff131 100644 --- a/lib/crc16.c +++ b/lib/crc16.c @@ -67,7 +67,9 @@ static const uint16_t crc16_tab[] = { uint16_t crc16_ccitt(uint16_t cksum, const unsigned char *buf, int len) { - for (int i = 0; i < len; i++) + int i; + + for (i = 0; i < len; i++) cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xff] ^ (cksum << 8); return cksum; -- 2.20.1

3 6

[U-Boot] [PATCH v3] net: phy: add TSE PCS support to dwmac-socfpga
by Ooi, Joyce 14 Feb '19

14 Feb '19

This adds support for TSE PCS (Triple Speed Ethernet Physical Coding Sublayer) that uses SGMII adapter when the phy-mode in device tree is set to sgmii. Signed-off-by: Ooi, Joyce <joyce.ooi(a)intel.com> --- arch/arm/mach-socfpga/include/mach/misc.h | 3 + arch/arm/mach-socfpga/misc_s10.c | 6 + drivers/net/Makefile | 3 +- drivers/net/designware.c | 5 + drivers/net/designware.h | 1 + drivers/net/dwmac_socfpga.c | 122 +++++++++++++++++++ drivers/net/phy/altr_tse_pcs.c | 184 +++++++++++++++++++++++++++++ drivers/net/phy/altr_tse_pcs.h | 56 +++++++++ 8 files changed, 379 insertions(+), 1 deletions(-) create mode 100644 drivers/net/phy/altr_tse_pcs.c create mode 100644 drivers/net/phy/altr_tse_pcs.h --- v2: add a __weak function to make it compatible for all socfpga platforms v3: remove __weak function and use board-specific implementation instead diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 4fc9570..751705e 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -30,6 +30,9 @@ void socfpga_init_security_policies(void); void socfpga_sdram_remap_zero(void); #endif +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +int socfpga_test_fpga_ready(void); +#endif void do_bridge_reset(int enable); #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index e599362..3cd9c30 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -11,6 +11,7 @@ #include <miiphy.h> #include <netdev.h> #include <asm/io.h> +#include <asm/arch/mailbox_s10.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> #include <asm/arch/misc.h> @@ -91,6 +92,11 @@ static int socfpga_set_phymode(void) return 0; } + +int socfpga_test_fpga_ready(void) +{ + return mbox_get_fpga_config_status(MBOX_CONFIG_STATUS); +} #else static int socfpga_set_phymode(void) { diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 48a2878..c2333b5 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o obj-$(CONFIG_CS8900) += cs8900.o obj-$(CONFIG_TULIP) += dc2114x.o obj-$(CONFIG_ETH_DESIGNWARE) += designware.o -obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o +obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac-socfpga.o obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DNET) += dnet.o obj-$(CONFIG_E1000) += e1000.o @@ -73,3 +73,4 @@ obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-$(CONFIG_SNI_AVE) += sni_ave.o +dwmac-socfpga-objs := phy/altr_tse_pcs.o dwmac_socfpga.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 19db0a8..666cf41 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -235,6 +235,8 @@ static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, struct phy_device *phydev) { u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; + struct udevice *dev = priv->phydev->dev; + struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); if (!phydev->link) { printf("%s: No link.\n", phydev->dev->name); @@ -254,6 +256,9 @@ static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, writel(conf, &mac_p->conf); + if (dw_pdata->pcs_adjust_link) + dw_pdata->pcs_adjust_link(dev, phydev); + printf("Speed: %d, %s duplex%s\n", phydev->speed, (phydev->duplex) ? "full" : "half", (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); diff --git a/drivers/net/designware.h b/drivers/net/designware.h index dea12b7..3a5a93f 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -255,6 +255,7 @@ extern const struct eth_ops designware_eth_ops; struct dw_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; + void (*pcs_adjust_link)(struct udevice *dev, struct phy_device *phydev); }; int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr); diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index 08fc967..7d13f3c 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -9,12 +9,16 @@ #include <asm/io.h> #include <dm.h> #include <clk.h> +#include <fdt_support.h> #include <phy.h> #include <regmap.h> #include <reset.h> #include <syscon.h> #include "designware.h" +#include "phy/altr_tse_pcs.h" +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> enum dwmac_type { @@ -27,8 +31,123 @@ struct dwmac_socfpga_platdata { struct dw_eth_pdata dw_eth_pdata; enum dwmac_type type; void *phy_intf; + struct tse_pcs pcs; }; +static void socfpga_tse_pcs_adjust_link(struct udevice *dev, + struct phy_device *phydev) +{ + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); + phys_addr_t tse_pcs_base = pdata->pcs.tse_pcs_base; + phys_addr_t sgmii_adapter_base = pdata->pcs.sgmii_adapter_base; + + if ((tse_pcs_base) && (sgmii_adapter_base)) + writew(SGMII_ADAPTER_DISABLE, + sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + + if ((tse_pcs_base) && (sgmii_adapter_base)) + tse_pcs_fix_mac_speed(&pdata->pcs, phydev, phydev->speed); +} + +static int socfpga_dw_tse_pcs_init(struct udevice *dev) +{ + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); + struct dw_eth_pdata *dw_pdata = &pdata->dw_eth_pdata; + struct eth_pdata *eth_pdata = &pdata->dw_eth_pdata.eth_pdata; + phys_addr_t tse_pcs_base = pdata->pcs.tse_pcs_base; + phys_addr_t sgmii_adapter_base = pdata->pcs.sgmii_adapter_base; + const fdt32_t *reg; + int ret = 0; + int parent, index, na, ns, offset, len; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), + "altr,gmii-to-sgmii-converter"); + if (offset > 0) { +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 + /* check FPGA status */ + ret = socfpga_test_fpga_ready(); + if (ret) { + debug("%s: FPGA not ready (%d)\n", __func__, ret); + return -EPERM; + } +#endif + /* enable HPS bridge */ + do_bridge_reset(1); + + parent = fdt_parent_offset(gd->fdt_blob, offset); + if (parent < 0) { + debug("s10-hps-bridge DT not found\n"); + return -ENODEV; + } + + na = fdt_address_cells(gd->fdt_blob, parent); + if (na < 1) { + debug("bad #address-cells\n"); + return -EINVAL; + } + + ns = fdt_size_cells(gd->fdt_blob, parent); + if (ns < 1) { + debug("bad #size-cells\n"); + return -EINVAL; + } + + index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", + "eth_tse_control_port"); + if (index < 0) { + debug("fail to find eth_tse_control_port: %s\n", + fdt_strerror(index)); + return -ENOENT; + } + + reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len); + if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) + return -EINVAL; + + reg += index * (na + ns); + tse_pcs_base = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); + if (tse_pcs_base == FDT_ADDR_T_NONE) { + debug("tse pcs address not found\n"); + return -EINVAL; + } + + index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", + "gmii_to_sgmii_adapter_avalon_slave"); + if (index < 0) { + debug("fail to find gmii_to_sgmii_adapter_avalon_slave: %s\n", + fdt_strerror(index)); + return -EINVAL; + } + + reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len); + if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) + return -EINVAL; + + reg += index * (na + ns); + sgmii_adapter_base = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); + if (sgmii_adapter_base == FDT_ADDR_T_NONE) { + debug("gmii-to-sgmii adapter address not found\n"); + return -EINVAL; + } + + if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_SGMII) { + if (tse_pcs_init(tse_pcs_base, &pdata->pcs) != 0) { + debug("Unable to intiialize TSE PCS\n"); + return -EINVAL; + } + } + /* Clear sgmii_adapter_base first */ + writel(0, sgmii_adapter_base); + + pdata->pcs.tse_pcs_base = tse_pcs_base; + pdata->pcs.sgmii_adapter_base = sgmii_adapter_base; + dw_pdata->pcs_adjust_link = socfpga_tse_pcs_adjust_link; + } + return ret; +} + static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) { struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); @@ -94,6 +213,7 @@ static int dwmac_socfpga_probe(struct udevice *dev) switch (edata->phy_interface) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_SGMII: modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; break; case PHY_INTERFACE_MODE_RMII: @@ -122,6 +242,8 @@ static int dwmac_socfpga_probe(struct udevice *dev) reset_release_bulk(&reset_bulk); } + socfpga_dw_tse_pcs_init(dev); + return designware_eth_probe(dev); } diff --git a/drivers/net/phy/altr_tse_pcs.c b/drivers/net/phy/altr_tse_pcs.c new file mode 100644 index 0000000..4423538 --- /dev/null +++ b/drivers/net/phy/altr_tse_pcs.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Intel Corporation <www.intel.com> + */ + +#include <asm/io.h> +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <net.h> +#include <linux/compat.h> +#include <phy.h> +#include <timer.h> +#include <wait_bit.h> +#include <linux/ethtool.h> + +#include <asm/omap_common.h> +#include <asm/omap_musb.h> + +#include "altr_tse_pcs.h" + +static int tse_pcs_reset(phys_addr_t base, struct tse_pcs *pcs) +{ + int ret; + u16 val; + phys_addr_t reg = base + TSE_PCS_CONTROL_REG; + + val = readw(reg); + val |= TSE_PCS_SW_RST_MASK; + + writew(val, reg); + + ret = wait_for_bit_le16(&reg, TSE_PCS_SW_RST_MASK, false, + TSE_PCS_SW_RESET_TIMEOUT, false); + + if (ret) { + debug("%s: PCS could not get out of sw reset\n", __func__); + return -ETIMEDOUT; + } + + return 0; +} + +int tse_pcs_init(phys_addr_t base, struct tse_pcs *pcs) +{ + int ret = 0; + + writew(TSE_PCS_USE_SGMII_ENA, base + TSE_PCS_IF_MODE_REG); + writew(TSE_PCS_SGMII_LINK_TIMER_0, base + TSE_PCS_LINK_TIMER_0_REG); + writew(TSE_PCS_SGMII_LINK_TIMER_1, base + TSE_PCS_LINK_TIMER_1_REG); + + ret = tse_pcs_reset(base, pcs); + if (ret == 0) + writew(SGMII_ADAPTER_ENABLE, + pcs->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + + return ret; +} + +static void pcs_link_timer_callback(struct tse_pcs *pcs) +{ + u16 val = 0; + phys_addr_t tse_pcs_base = pcs->tse_pcs_base; + phys_addr_t sgmii_adapter_base = pcs->sgmii_adapter_base; + + val = readw(tse_pcs_base + TSE_PCS_STATUS_REG); + val &= TSE_PCS_STATUS_LINK_MASK; + + if (val != 0) { + printf("Adapter: Link is established\n"); + writew(SGMII_ADAPTER_ENABLE, + sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + } else { + printf("Adapter: Link fail to establish\n"); + } +} + +static void auto_nego_timer_callback(struct tse_pcs *pcs) +{ + u16 val = 0; + u16 speed = 0; + u16 duplex = 0; + phys_addr_t tse_pcs_base = pcs->tse_pcs_base; + phys_addr_t sgmii_adapter_base = pcs->sgmii_adapter_base; + + val = readw(tse_pcs_base + TSE_PCS_STATUS_REG); + val &= TSE_PCS_STATUS_AN_COMPLETED_MASK; + + if (val != 0) { + printf("Adapter: Auto Negotiation is completed\n"); + val = readw(tse_pcs_base + TSE_PCS_PARTNER_ABILITY_REG); + speed = val & TSE_PCS_PARTNER_SPEED_MASK; + duplex = val & TSE_PCS_PARTNER_DUPLEX_MASK; + + if (duplex == TSE_PCS_PARTNER_DUPLEX_FULL) { + if (speed == TSE_PCS_PARTNER_SPEED_10) + printf("Adapter: Link Partner is Up - 10/Full\n"); + else if (speed == TSE_PCS_PARTNER_SPEED_100) + printf("Adapter: Link Partner is Up - 100/Full\n"); + else if (speed == TSE_PCS_PARTNER_SPEED_1000) + printf("Adapter: Link Partner is Up - 1000/Full\n"); + } else if (duplex == TSE_PCS_PARTNER_DUPLEX_HALF) + printf("Adapter does not support Half Duplex\n"); + else + printf("Adapter: Invalid Partner Speed and Duplex\n"); + + if (duplex == TSE_PCS_PARTNER_DUPLEX_FULL && + (speed == TSE_PCS_PARTNER_SPEED_10 || + speed == TSE_PCS_PARTNER_SPEED_100 || + speed == TSE_PCS_PARTNER_SPEED_1000)) + writew(SGMII_ADAPTER_ENABLE, + sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + } else { + printf("Auto-negotioation failed\n"); + } +} + +void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev, + unsigned int speed) +{ + phys_addr_t tse_pcs_base = pcs->tse_pcs_base; + phys_addr_t sgmii_adapter_base = pcs->sgmii_adapter_base; + u32 val, start; + + writew(SGMII_ADAPTER_ENABLE, + sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + pcs->autoneg = phy_dev->autoneg; + + if (pcs->autoneg == AUTONEG_ENABLE) { + val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); + val |= TSE_PCS_CONTROL_AN_EN_MASK; + writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG); + + val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); + val |= TSE_PCS_USE_SGMII_AN_MASK; + writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG); + + val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); + val |= TSE_PCS_CONTROL_RESTART_AN_MASK; + + tse_pcs_reset(tse_pcs_base, pcs); + + } else if (pcs->autoneg == AUTONEG_DISABLE) { + val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); + val &= ~TSE_PCS_CONTROL_AN_EN_MASK; + writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG); + + val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); + val &= ~TSE_PCS_USE_SGMII_AN_MASK; + writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG); + + val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); + val &= ~TSE_PCS_SGMII_SPEED_MASK; + + switch (speed) { + case 1000: + val |= TSE_PCS_SGMII_SPEED_1000; + break; + case 100: + val |= TSE_PCS_SGMII_SPEED_100; + break; + case 10: + val |= TSE_PCS_SGMII_SPEED_10; + break; + default: + return; + } + writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG); + + tse_pcs_reset(tse_pcs_base, pcs); + } + + start = get_timer(0); + while (1) { + if (get_timer(start) >= AUTONEGO_LINK_TIMER) { + if (pcs->autoneg == AUTONEG_ENABLE) + auto_nego_timer_callback(pcs); + else if (pcs->autoneg == AUTONEG_DISABLE) + pcs_link_timer_callback(pcs); + return; + } + udelay(100); + } +} diff --git a/drivers/net/phy/altr_tse_pcs.h b/drivers/net/phy/altr_tse_pcs.h new file mode 100644 index 0000000..0e8d4f4 --- /dev/null +++ b/drivers/net/phy/altr_tse_pcs.h @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Intel Corporation <www.intel.com> + */ + +#ifndef __TSE_PCS_H__ +#define __TSE_PCS_H__ + +#define TSE_PCS_CONTROL_AN_EN_MASK BIT(12) +#define TSE_PCS_CONTROL_REG 0x00 +#define TSE_PCS_CONTROL_RESTART_AN_MASK BIT(9) +#define TSE_PCS_IF_MODE_REG 0x28 +#define TSE_PCS_LINK_TIMER_0_REG 0x24 +#define TSE_PCS_LINK_TIMER_1_REG 0x26 +#define TSE_PCS_SIZE 0x40 +#define TSE_PCS_STATUS_AN_COMPLETED_MASK BIT(5) +#define TSE_PCS_STATUS_LINK_MASK BIT(2) +#define TSE_PCS_STATUS_REG 0x02 +#define TSE_PCS_SGMII_SPEED_1000 BIT(3) +#define TSE_PCS_SGMII_SPEED_100 BIT(2) +#define TSE_PCS_SGMII_SPEED_10 0x0 +#define TSE_PCS_SGMII_SPEED_MASK GENMASK(3, 2) +#define TSE_PCS_SW_RST_MASK BIT(15) +#define TSE_PCS_PARTNER_ABILITY_REG 0x0A +#define TSE_PCS_PARTNER_DUPLEX_FULL BIT(12) +#define TSE_PCS_PARTNER_DUPLEX_HALF 0x0000 +#define TSE_PCS_PARTNER_DUPLEX_MASK BIT(12) +#define TSE_PCS_PARTNER_SPEED_MASK GENMASK(11, 10) +#define TSE_PCS_PARTNER_SPEED_1000 BIT(11) +#define TSE_PCS_PARTNER_SPEED_100 BIT(10) +#define TSE_PCS_PARTNER_SPEED_10 0x0000 +#define TSE_PCS_SGMII_LINK_TIMER_0 0x0D40 +#define TSE_PCS_SGMII_LINK_TIMER_1 0x0003 +#define TSE_PCS_SW_RESET_TIMEOUT 100 +#define TSE_PCS_USE_SGMII_AN_MASK BIT(1) +#define TSE_PCS_USE_SGMII_ENA BIT(0) + +#define SGMII_ADAPTER_CTRL_REG 0x00 +#define SGMII_ADAPTER_DISABLE 0x0001 +#define SGMII_ADAPTER_ENABLE 0x0000 + +#define AUTONEGO_LINK_TIMER 20 + +struct tse_pcs { + struct device *dev; + phys_addr_t tse_pcs_base; + phys_addr_t sgmii_adapter_base; + struct timer_list aneg_link_timer; + int autoneg; +}; + +int tse_pcs_init(phys_addr_t base, struct tse_pcs *pcs); +void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev, + unsigned int speed); + +#endif /* __TSE_PCS_H__ */ -- 1.7.1

2 19

[U-Boot] [PATCH 0/3] sunxi: Sync Bananapi M2+ dts files and add H5 variant
by Chen-Yu Tsai 14 Feb '19

14 Feb '19

This series adds support for the H5 variant of the Bananapi M2+, and also renames the MAINTAINERS entry and defconfig for the Bananapi M2+ from its current name, Sinovoip BPI M2+. Sinovoip is the brand name used for their own VOIP-related products, while the brand name "Bananapi" should be used for single board computers bearing the Bananapi logo. This was confirmed by Bananapi. Patch 1 syncs up the BPI-M2+ device tree file from Linux v5.0-rc1. Patch 2 renames the defconfig and maintainer entries to fix the brand name. Patch 3 adds support for the H5 variant of the Bananapi M2+. Please have a look. Regards ChenYu Chen-Yu Tsai (3): sunxi: Sync Bananapi M2+ device tree from Linux v5.0-rc1 sunxi: Rename Sinovoip BPI M2 Plus to Bananapi M2 Plus H3 sunxi: Add Bananapi M2+ H5 board arch/arm/dts/sun50i-h5-bananapi-m2-plus.dts | 11 + arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts | 190 +----------------- ...2-plus.dts => sunxi-bananapi-m2-plus.dtsi} | 23 ++- board/sunxi/MAINTAINERS | 13 +- configs/Sinovoip_BPI_M2_Plus_defconfig | 21 +- ...efconfig => bananapi_m2_plus_h3_defconfig} | 0 ...efconfig => bananapi_m2_plus_h5_defconfig} | 4 +- 7 files changed, 40 insertions(+), 222 deletions(-) create mode 100644 arch/arm/dts/sun50i-h5-bananapi-m2-plus.dts copy arch/arm/dts/{sun8i-h3-bananapi-m2-plus.dts => sunxi-bananapi-m2-plus.dtsi} (92%) mode change 100644 => 120000 configs/Sinovoip_BPI_M2_Plus_defconfig copy configs/{Sinovoip_BPI_M2_Plus_defconfig => bananapi_m2_plus_h3_defconfig} (100%) copy configs/{Sinovoip_BPI_M2_Plus_defconfig => bananapi_m2_plus_h5_defconfig} (85%) -- 2.20.1

4 17

[U-Boot] U-Boot port for esp32
by kbenvin 14 Feb '19

14 Feb '19

Hi, I am new to U-Boot, and looking for a U-Boot port for esp32 soc based on xtensa. Search for esp32 in search option in this forum for any existing question didn't show up anything. Is there any U-Boot port (done/inprogress) for esp32? If not, could somebody provide any link/guide on how to start? -- Sent from: http://u-boot.10912.n7.nabble.com/

1 0

[U-Boot] [PATCH 0/8] pci: Add pcie controller driver for NXP LX SoCs
by Z.q. Hou 14 Feb '19

14 Feb '19

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Add PCIe driver for the NXP LX series SoCs. Hou Zhiqiang (8): armv8: fsl-layerscpae: correct the PCIe controllers' region size armv8: lx2160a: add MMU table entries for PCIe pci: Add pcie controller driver for NXP LX SoCs kconfig: add dependency PCIE_LX for FSL_PCIE_COMPAT pci: pcie_lx: add device tree fixups for PCI Stream IDs armv8: lx2160a: add pcie DT nodes armv8: lx2160a: enable pcie support on RDB defconfig armv8: lx2160a: enable the pci command Depends on the following patches: https://patchwork.ozlabs.org/patch/990088/ https://patchwork.ozlabs.org/patch/990093/ https://patchwork.ozlabs.org/patch/990097/ https://patchwork.ozlabs.org/patch/990098/ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 12 + arch/arm/dts/fsl-lx2160a.dtsi | 85 +++ .../arm/include/asm/arch-fsl-layerscape/cpu.h | 9 + .../asm/arch-fsl-layerscape/immap_lsch3.h | 14 +- configs/lx2160ardb_tfa_defconfig | 5 + drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_lx.c | 607 ++++++++++++++++++ drivers/pci/pcie_lx.h | 258 ++++++++ drivers/pci/pcie_lx_fixup.c | 234 +++++++ include/configs/lx2160a_common.h | 1 + 12 files changed, 1234 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/pcie_lx.c create mode 100644 drivers/pci/pcie_lx.h create mode 100644 drivers/pci/pcie_lx_fixup.c -- 2.17.1

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[U-Boot] env: Support multiple environments with varied size/offset/redund
by Tim Harvey 14 Feb '19

14 Feb '19

commit 7d714a24d7258db1188abe3c7c9c46a1cc7ab8be finalized adding support for multiple env locations in U-Boot and I'm really thankful for this work! I would like to extend this such that each env can have a unique size/offset/redund configuration. This would affect all the env drivers so before I code it up I wanted to see if there was agreement on how this should be done. We could define a new struct in environment.h: struct env_details { enum env_location loc; unsigned long size; unsigned long offset; unsigned long offset_redund; }; This can be added as a parameter to env_get_location(..) and would get initialized such that size=CONFIG_ENV_SIZE, offset=CONFIG_ENV_OFFSET, offset_redund=CONFIG_ENV_OFFSET_REDUND to that current users could do nothing for current before but boards that are interested could differ the details of the storage based on the type. Then these details would need to be passed to each env drivers init/load/save functions to be used instead of the currently hard coded configs (CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, and CONFIG_ENV_OFFSET_REDUND). There are likely some more I'll run into along the way such as hardware partition etc. Any opposing thoughts or suggestions before I code this up and submit a patch? Tim

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[U-Boot] [RFC 1/1] configs: rk3288: SPL file must fit into 32 KiB
by Heinrich Schuchardt 13 Feb '19

13 Feb '19

The SPL image for the rk3288 boards has to fit into 32 KiB. This includes 4 KiB for the device tree and up to 2 KiB for the file header. Without the patch we missed to see that the TinkerBoard spl/u-boot-spl-dtb.bin file is too big. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- include/configs/rk3288_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index c59f5eff7a..7c8d01ec50 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -23,6 +23,8 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 +/* 32 KiB - 4 KiB for dtb - 2 KiB for file header */ +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x1800) #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) # define CONFIG_SPL_TEXT_BASE 0x0 #else -- 2.20.1

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[U-Boot] [PULL] efi patch queue 2019-02-13
by Alexander Graf 13 Feb '19

13 Feb '19

Hi Tom, This is my current patch queue for efi. Please pull. Alex The following changes since commit b1b1bab7f92b838a252ab977f56d9c3584c14fb7: test/py: use default load address for tftp (2019-02-12 07:19:24 -0500) are available in the git repository at: git://github.com/agraf/u-boot.git tags/signed-efi-next for you to fetch changes up to 823c233b7ab95169ea4428b2821b72b8887b47b0: efi_loader: fix EFI_FILE_PROTOCOL.GetInfo() (2019-02-13 09:40:06 +0100) ---------------------------------------------------------------- Patch queue for efi - 2019-02-13 Goodness this time around: - HII protocol, finally allows us to run the UEFI Shell! (experimantal, disabled by default) - efi selftest now available on Cortex-M - NVMe support for distro boot - Lots of code cleanup ---------------------------------------------------------------- AKASHI Takahiro (8): distro: not taint environment variables if possible efi_loader: move efi_init_obj_list() to a new efi_setup.c efi_loader: implement GetNextVariableName() efi_selftest: fix variables test for GetNextVariableName() efi: hii: add guid package support efi: hii: add keyboard layout package support efi: hii: add HII config routing/access protocols efi_selftest: add HII database protocols test Akashi, Takahiro (1): lib: add u16_strcpy/strdup functions Alexander Graf (2): arm: Leave smccc calls in .text when efi_loader=n efi_loader: Make HII a config option Heinrich Schuchardt (38): efi_loader: efi_guid_t must be 64-bit aligned efi_loader: struct efi_configuration_table test: tests for u16_strdup() and u16_strcpy() distro_bootcmd: add NVME support efi_loader: efi_add_runtime_mmio() efi_loader: efi_connect_controller() use %pD efi_loader: use named constant for efi_dp_from_mem() efi_loader: CMD_BOOTEFI_HELLO_COMPILE in configs efi_loader: fix memory allocation on sandbox efi_loader: avoid unnecessary pointer to long conversion efi_loader: signature of StartImage and Exit efi_selftest: allow building on ARMv7-M doc: README.uefi: fix typos efi_loader: use const efi_guid_t * for variable services efi_loader: efi_set_variable use const void * efi_selftest: SNP unit test on sandbox efi_selftest: events unit test, check return values efi_selftest: tpl unit test, check return values efi_driver: simplify error message efi_loader: refactor switch to non-secure mode efi_loader: fix CopyMem() efi_loader: use u16* for file name efi_loader: consistent build flags for EFI applications efi_loader: remove duplicate GUID definition efi_loader: eliminate duplicate function hex2mem() efi_loader: remove duplicate function mem2hex() efi_loader: comments for variable services efi_loader: provide freestanding library efi_loader: use freestanding library for efi apps efi_loader: use library memcpy() in helloworld.efi efi_loader: do not use symbolic links efi_loader: fix GetNextVariableName efi_loader: GetNextVariableName() relies on REGEX x86: do not use i386 code for x86_64 memory functions efi_selftest: fix HII tests efi_loader: debug output for HII protocols lib: vsprintf: avoid overflow printing UTF16 strings efi_loader: fix EFI_FILE_PROTOCOL.GetInfo() Leif Lindholm (1): efi_loader: Initial HII database protocols arch/arm/cpu/armv7/Makefile | 1 + arch/arm/cpu/armv7/exception_level.c | 56 ++ arch/arm/cpu/armv7/smccc-call.S | 2 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/exception_level.c | 55 ++ arch/arm/cpu/armv8/smccc-call.S | 2 + arch/arm/lib/Makefile | 6 +- arch/x86/include/asm/string.h | 31 +- arch/x86/lib/Makefile | 2 +- cmd/Kconfig | 2 +- cmd/bootefi.c | 152 +--- common/bootm.c | 10 + configs/chromebook_link64_defconfig | 1 - configs/kp_imx6q_tpc_defconfig | 1 - configs/qemu-x86_64_defconfig | 1 - configs/stm32f429-discovery_defconfig | 1 - configs/stm32f429-evaluation_defconfig | 1 - configs/stm32f469-discovery_defconfig | 1 - doc/README.uefi | 10 +- include/bootm.h | 5 + include/charset.h | 23 + include/config_distro_bootcmd.h | 40 +- include/efi.h | 2 +- include/efi_api.h | 445 ++++++++++- include/efi_loader.h | 24 +- lib/charset.c | 29 + lib/efi_driver/efi_uclass.c | 3 +- lib/efi_loader/Kconfig | 16 + lib/efi_loader/Makefile | 4 +- lib/efi_loader/efi_boottime.c | 34 +- lib/efi_loader/efi_file.c | 18 +- lib/efi_loader/efi_freestanding.c | 90 +++ lib/efi_loader/efi_hii.c | 1095 ++++++++++++++++++++++++++ lib/efi_loader/efi_hii_config.c | 146 ++++ lib/efi_loader/efi_memory.c | 6 + lib/efi_loader/efi_runtime.c | 3 +- lib/efi_loader/efi_setup.c | 86 ++ lib/efi_loader/efi_variable.c | 300 +++++-- lib/efi_loader/helloworld.c | 36 +- lib/efi_selftest/Makefile | 11 +- lib/efi_selftest/efi_selftest_block_device.c | 6 +- lib/efi_selftest/efi_selftest_events.c | 6 +- lib/efi_selftest/efi_selftest_hii.c | 1035 ++++++++++++++++++++++++ lib/efi_selftest/efi_selftest_hii_data.c | 453 +++++++++++ lib/efi_selftest/efi_selftest_snp.c | 8 + lib/efi_selftest/efi_selftest_tpl.c | 4 +- lib/efi_selftest/efi_selftest_variables.c | 17 +- lib/vsprintf.c | 10 +- scripts/Makefile.lib | 2 +- test/unicode_ut.c | 23 + 50 files changed, 3980 insertions(+), 336 deletions(-) create mode 100644 arch/arm/cpu/armv7/exception_level.c create mode 100644 arch/arm/cpu/armv8/exception_level.c create mode 100644 lib/efi_loader/efi_freestanding.c create mode 100644 lib/efi_loader/efi_hii.c create mode 100644 lib/efi_loader/efi_hii_config.c create mode 100644 lib/efi_loader/efi_setup.c create mode 100644 lib/efi_selftest/efi_selftest_hii.c create mode 100644 lib/efi_selftest/efi_selftest_hii_data.c

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[U-Boot] SPL_FIT_SIGNATURE on am3358
by Douglas Zobel 13 Feb '19

13 Feb '19

I'm having trouble getting verified boot working in SPL on an am3358 based platform. The problem I hit is when fit_image_verify_with_data() calls fit_image_verify_required_sigs(). The 5th argument (sig_blob) is gd_fdt_blob() which resolves to NULL. This argument should be the FDT containing the public keys. I assume this happens because SPL_OF_CONTROL isn't enabled. As far as I can tell, SPL_OF_CONTROL isn't working on am33xx boards; enabling it causes SPL to loop infinitely in i2c init (tried on my custom hardware as well as Beaglebone Black). So the public key needs to be found elsewhere. I can keep a separate FDT with the public key stored in a read-only location. My question is what is the 'right' way to load it? Is there an interface for populating gd_fdt_blob() with my own FDT (without SPL_OF_CONTROL enabled)? Or should I modify fit_image_verify_with_data() to get the FDT from elsewhere (and probably other similar calls as well)? -Doug -- This email and any attachments are for the exclusive use of the intended recipient(s) and may contain confidential and/or privileged information. Inadvertent disclosure of this message does not constitute a waiver of any privilege, right or remedy. If you are not the intended recipient, please do not directly or indirectly use, disclose or distribute this message, and please contact the sender and delete this email, any attachments and all copies. Climate and its affiliates may use, read or archive email communications (including attachments) through its computer network, as permitted by applicable law. Climate and its affiliates (or an external service provider) may also scan emails and attachments on its computer network to ensure systems operate efficiently and to minimize security risks. Thank you.

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[U-Boot] [PATCH 0/9] xilinx: dts: Update various DT files
by Michal Simek 13 Feb '19

13 Feb '19

Hi, just put together some DT changes and send me all. Most of these patches are coming from Linux kernel. Thanks, Michal Amit Kucheria (1): arm64: dts: Fix various entry-method properties to reflect documentation Luis Araneda (2): ARM: dts: zynq: Set correct manufacturer for ZedBoard and MicroZed boards ARM: dts: zynq: correct and improve the model property of dt files Michal Simek (3): ARM: dts: Use mmc@ instead sdhci@ xilinx: dts: Remove additional empty lines arm64: zynqmp: Remove autodetected devices without description Mounika Grace Akula (1): arm64: zynqmp: Add reset-on-timeout for all boards and modify default timeout value Shubhrajyoti Datta (1): arm64: zynqmp: Fix i2c boot warning Venkatesh Yadav Abbarapu (1): arm64: zynqmp: Change the spi-rx-bus-width property to x1 arch/arm/dts/zynq-7000.dtsi | 4 ++-- arch/arm/dts/zynq-cc108.dts | 2 +- arch/arm/dts/zynq-microzed.dts | 2 +- arch/arm/dts/zynq-zc702.dts | 2 +- arch/arm/dts/zynq-zc706.dts | 2 +- arch/arm/dts/zynq-zc770-xm010.dts | 3 +-- arch/arm/dts/zynq-zc770-xm011.dts | 2 +- arch/arm/dts/zynq-zc770-xm012.dts | 2 +- arch/arm/dts/zynq-zc770-xm013.dts | 2 +- arch/arm/dts/zynq-zed.dts | 4 ++-- arch/arm/dts/zynq-zybo.dts | 2 +- arch/arm/dts/zynqmp-zc1275-revB.dts | 2 +- arch/arm/dts/zynqmp-zcu100-revC.dts | 2 -- arch/arm/dts/zynqmp-zcu102-revA.dts | 16 ---------------- arch/arm/dts/zynqmp-zcu106-revA.dts | 20 -------------------- arch/arm/dts/zynqmp-zcu111-revA.dts | 20 -------------------- arch/arm/dts/zynqmp.dtsi | 5 +++-- 17 files changed, 17 insertions(+), 75 deletions(-) -- 1.9.1

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