February 2019 - U-Boot

[U-Boot] [PATCH v2] armv8 : fsl-layerscape : Fix hang when TFA is used.
by Meenakshi Aggarwal 15 Feb '19

15 Feb '19

When TFA is used as EL3 firmware, then u-boot is crashing because DDR is not coherent. Changing DDR memory attributes to device type fix the issue. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> Signed-off-by: Udit Kumar <udit.kumar(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index be21685..32f3d2a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -100,9 +100,10 @@ static struct mm_region early_map[] = { #endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, -#if defined(CONFIG_TFABOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) - PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#if defined(CONFIG_TFABOOT) + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) +#elif defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + PTE_BLOCK_MEMTYPE(MT_NORMAL) #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | #endif -- 1.9.1

1 0

[U-Boot] [PATCH 1/3] drivers: ag7xxx: add support for qca956x-s17
by Rosy Song 15 Feb '19

15 Feb '19

Signed-off-by: Rosy Song <rosysong(a)rosinson.com> --- drivers/net/ag7xxx.c | 140 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 124 insertions(+), 16 deletions(-) diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c index 403eb64895..b3b53205fa 100644 --- a/drivers/net/ag7xxx.c +++ b/drivers/net/ag7xxx.c @@ -3,6 +3,7 @@ * Atheros AR71xx / AR9xxx GMAC driver * * Copyright (C) 2016 Marek Vasut <marex(a)denx.de> + * Copyright (C) 2019 Rosy Song <rosysong(a)rosinson.com> */ #include <common.h> @@ -23,7 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; enum ag7xxx_model { AG7XXX_MODEL_AG933X, AG7XXX_MODEL_AG934X, - AG7XXX_MODEL_AG953X + AG7XXX_MODEL_AG953X, + AG7XXX_MODEL_AG956X }; /* MAC Configuration 1 */ @@ -219,6 +221,7 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val) u32 reg_addr; u32 phy_temp; u32 reg_temp; + u32 reg_temp_w = (reg & 0xfffffffc) >> 1; u16 rv = 0; int ret; @@ -226,18 +229,25 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val) priv->model == AG7XXX_MODEL_AG953X) { phy_addr = 0x1f; reg_addr = 0x10; - } else if (priv->model == AG7XXX_MODEL_AG934X) { + } else if (priv->model == AG7XXX_MODEL_AG934X || + priv->model == AG7XXX_MODEL_AG956X) { phy_addr = 0x18; reg_addr = 0x00; } else return -EINVAL; - ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); + if (priv->model == AG7XXX_MODEL_AG956X) { + ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff); + } else + ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); if (ret) return ret; phy_temp = ((reg >> 6) & 0x7) | 0x10; - reg_temp = (reg >> 1) & 0x1e; + if (priv->model == AG7XXX_MODEL_AG956X) + reg_temp = reg_temp_w & 0x1f; + else + reg_temp = (reg >> 1) & 0x1e; *val = 0; ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv); @@ -245,7 +255,13 @@ static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val) return ret; *val |= rv; - ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv); + if (priv->model == AG7XXX_MODEL_AG956X) { + phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10; + reg_temp = (reg_temp_w + 1) & 0x1f; + ret = ag7xxx_switch_read(bus, phy_temp, reg_temp, &rv); + } else { + ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv); + } if (ret < 0) return ret; *val |= (rv << 16); @@ -260,24 +276,35 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val) u32 reg_addr; u32 phy_temp; u32 reg_temp; + u32 reg_temp_w = (reg & 0xfffffffc) >> 1; int ret; if (priv->model == AG7XXX_MODEL_AG933X || priv->model == AG7XXX_MODEL_AG953X) { phy_addr = 0x1f; reg_addr = 0x10; - } else if (priv->model == AG7XXX_MODEL_AG934X) { + } else if (priv->model == AG7XXX_MODEL_AG934X || + priv->model == AG7XXX_MODEL_AG956X) { phy_addr = 0x18; reg_addr = 0x00; } else return -EINVAL; - ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); + if (priv->model == AG7XXX_MODEL_AG956X) + ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff); + else + ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); if (ret) return ret; - phy_temp = ((reg >> 6) & 0x7) | 0x10; - reg_temp = (reg >> 1) & 0x1e; + + if (priv->model == AG7XXX_MODEL_AG956X) { + reg_temp = (reg_temp_w + 1) & 0x1f; + phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10; + } else { + phy_temp = ((reg >> 6) & 0x7) | 0x10; + reg_temp = (reg >> 1) & 0x1e; + } /* * The switch on AR933x has some special register behavior, which @@ -296,10 +323,18 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val) if (ret < 0) return ret; } else { - ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); + if (priv->model == AG7XXX_MODEL_AG956X) { + ret = ag7xxx_switch_write(bus, phy_temp, reg_temp, val >> 16); + } else + ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); if (ret < 0) return ret; + if (priv->model == AG7XXX_MODEL_AG956X) { + phy_temp = ((reg_temp_w >> 5) & 0x7) | 0x10; + reg_temp = reg_temp_w & 0x1f; + } + ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); if (ret < 0) return ret; @@ -626,9 +661,12 @@ static int ag7xxx_mii_setup(struct udevice *dev) reg = 0x4; else if (priv->model == AG7XXX_MODEL_AG953X) reg = 0x2; + else if (priv->model == AG7XXX_MODEL_AG956X) + reg = 0x7; if (priv->model == AG7XXX_MODEL_AG934X || - priv->model == AG7XXX_MODEL_AG953X) { + priv->model == AG7XXX_MODEL_AG953X || + priv->model == AG7XXX_MODEL_AG956X) { writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | reg, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); writel(reg, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); @@ -839,7 +877,8 @@ static int ag933x_phy_setup_reset_set(struct udevice *dev, int port) struct ar7xxx_eth_priv *priv = dev_get_priv(dev); int ret; - if (priv->model == AG7XXX_MODEL_AG953X) { + if (priv->model == AG7XXX_MODEL_AG953X || + priv->model == AG7XXX_MODEL_AG956X) { ret = ag7xxx_switch_write(priv->bus, port, MII_ADVERTISE, ADVERTISE_ALL); } else { @@ -855,9 +894,15 @@ static int ag933x_phy_setup_reset_set(struct udevice *dev, int port) ADVERTISE_1000FULL); if (ret) return ret; + } else if (priv->model == AG7XXX_MODEL_AG956X) { + ret = ag7xxx_switch_write(priv->bus, port, MII_CTRL1000, + ADVERTISE_1000FULL); + if (ret) + return ret; } - if (priv->model == AG7XXX_MODEL_AG953X) + if (priv->model == AG7XXX_MODEL_AG953X || + priv->model == AG7XXX_MODEL_AG956X) return ag7xxx_switch_write(priv->bus, port, MII_BMCR, BMCR_ANENABLE | BMCR_RESET); @@ -871,7 +916,8 @@ static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port) int ret; u16 reg; - if (priv->model == AG7XXX_MODEL_AG953X) { + if (priv->model == AG7XXX_MODEL_AG953X || + priv->model == AG7XXX_MODEL_AG956X) { do { ret = ag7xxx_switch_read(priv->bus, port, MII_BMCR, &reg); if (ret < 0) @@ -899,7 +945,8 @@ static int ag933x_phy_setup_common(struct udevice *dev) if (priv->model == AG7XXX_MODEL_AG933X) phymax = 4; else if (priv->model == AG7XXX_MODEL_AG934X || - priv->model == AG7XXX_MODEL_AG953X) + priv->model == AG7XXX_MODEL_AG953X || + priv->model == AG7XXX_MODEL_AG956X) phymax = 5; else return -EINVAL; @@ -939,7 +986,8 @@ static int ag933x_phy_setup_common(struct udevice *dev) for (i = 0; i < phymax; i++) { /* Read out link status */ - if (priv->model == AG7XXX_MODEL_AG953X) + if (priv->model == AG7XXX_MODEL_AG953X || + priv->model == AG7XXX_MODEL_AG956X) ret = ag7xxx_switch_read(priv->bus, i, MII_MIPSCR, &reg); else ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR); @@ -1004,6 +1052,63 @@ static int ag934x_phy_setup(struct udevice *dev) return 0; } +static int ag956x_phy_setup(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + int i, ret; + u32 reg, ctrl; + + ret = ag7xxx_switch_reg_read(priv->bus, 0x0, &reg); + if (ret) + return ret; + if ((reg & 0xffff) >= 0x1301) + ctrl = 0xc74164de; + else + ctrl = 0xc74164d0; + + ret = ag7xxx_switch_reg_write(priv->bus, 0x4, BIT(7)); + if (ret) + return ret; + + ret = ag7xxx_switch_reg_write(priv->bus, 0xe0, ctrl); + if (ret) + return ret; + + ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f); + if (ret) + return ret; + + /* + * Values suggested by the switch team when s17 in sgmii + * configuration. 0x10(S17_PWS_REG) = 0x602613a0 + */ + ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x602613a0); + if (ret) + return ret; + + ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e); + if (ret) + return ret; + + /* AR8337/AR8334 v1.0 fixup */ + ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg); + if (ret) + return ret; + if ((reg & 0xffff) == 0x1301) { + for (i = 0; i < 5; i++) { + /* Turn on Gigabit clock */ + ret = ag7xxx_switch_write(priv->bus, i, 0x1d, 0x3d); + if (ret) + return ret; + ret = ag7xxx_switch_write(priv->bus, i, 0x1e, 0x6820); + if (ret) + return ret; + } + } + + return 0; +} + static int ag7xxx_mac_probe(struct udevice *dev) { struct ar7xxx_eth_priv *priv = dev_get_priv(dev); @@ -1028,6 +1133,8 @@ static int ag7xxx_mac_probe(struct udevice *dev) ret = ag953x_phy_setup_lan(dev); } else if (priv->model == AG7XXX_MODEL_AG934X) { ret = ag934x_phy_setup(dev); + } else if (priv->model == AG7XXX_MODEL_AG956X) { + ret = ag956x_phy_setup(dev); } else { return -EINVAL; } @@ -1166,6 +1273,7 @@ static const struct udevice_id ag7xxx_eth_ids[] = { { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X }, { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X }, { .compatible = "qca,ag953x-mac", .data = AG7XXX_MODEL_AG953X }, + { .compatible = "qca,ag956x-mac", .data = AG7XXX_MODEL_AG956X }, { } }; -- 2.17.0

1 0

[U-Boot] [PATCH] usb: Select USB_MUSB_DSPS with USB_MUSB_TI
by Alex Kiernan 15 Feb '19

15 Feb '19

USB_MUSB_TI requires USB_MUSB_DSPS, failing at link time if it's not selected: drivers/usb/musb-new/built-in.o: In function `ti_musb_host_ofdata_to_platdata': drivers/usb/musb-new/ti-musb.c:193: undefined reference to `musb_dsps_ops' Signed-off-by: Alex Kiernan <alex.kiernan(a)gmail.com> --- configs/am335x_boneblack_vboot_defconfig | 1 - configs/am335x_evm_defconfig | 1 - configs/am335x_hs_evm_defconfig | 1 - configs/am335x_hs_evm_uart_defconfig | 1 - configs/brppt1_mmc_defconfig | 1 - configs/brppt1_nand_defconfig | 1 - configs/brppt1_spi_defconfig | 1 - configs/chiliboard_defconfig | 1 - drivers/usb/musb-new/Kconfig | 1 + 9 files changed, 1 insertion(+), 8 deletions(-) diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index f455b01e1e81..f4bf88b5e094 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -55,7 +55,6 @@ CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y -CONFIG_USB_MUSB_DSPS=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 924116835251..962feedd1279 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -61,7 +61,6 @@ CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y -CONFIG_USB_MUSB_DSPS=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index faa6c2b05fcd..3c9d385b049a 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -60,7 +60,6 @@ CONFIG_DM_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y -CONFIG_USB_MUSB_DSPS=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index 02332db0a6e9..9d970849cf66 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -62,7 +62,6 @@ CONFIG_DM_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y -CONFIG_USB_MUSB_DSPS=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index f2d822012619..3d2f0737fdf2 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -83,7 +83,6 @@ CONFIG_DM_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y -CONFIG_USB_MUSB_DSPS=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_FAT_WRITE=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index 275727d11f32..02dc03542c1d 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -87,7 +87,6 @@ CONFIG_DM_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y -CONFIG_USB_MUSB_DSPS=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_FAT_WRITE=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 668c4c22c27f..3619587bdc5c 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -97,7 +97,6 @@ CONFIG_DM_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y -CONFIG_USB_MUSB_DSPS=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_FAT_WRITE=y diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index a6c36eda503d..944dd0db3c87 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -50,6 +50,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_TI=y -CONFIG_USB_MUSB_DSPS=y CONFIG_FAT_WRITE=y CONFIG_LZO=y diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index f8f2205a62d3..1dd823037bec 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -21,6 +21,7 @@ config USB_MUSB_GADGET config USB_MUSB_TI bool "Enable TI OTG USB controller" depends on DM_USB + select USB_MUSB_DSPS default n help Say y here to enable support for the dual role high -- 2.17.1

2 1

[U-Boot] [PATCH v8 0/8] Add support for loading FPGA bitstream
by tien.fong.chee＠intel.com 15 Feb '19

15 Feb '19

From: Tien Fong Chee <tien.fong.chee(a)intel.com> This version mainly resolved comments from Marek and Dalon L Westergreen in [v7]. Additonal note: --------------- There are a few solutions at this moment for solving the performance issue 1. Using absolute data position to allign the core bistream in fitImage. 2. SPL program periph bitstream, then using fpga loadmk for loading the core bitstream from DDR. This is work because there is no allignment performance issue when reading whole fitImage instead of offset to the fitImage. This series is working on top of u-boot.git - http://git.denx.de/u-boot.git . [v7]: https://www.mail-archive.com/u-boot@lists.denx.de/msg314511.html Tien Fong Chee (8): ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK fit: Add function declarations to the header file ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK spl : socfpga: Implement fpga bitstream loading with socfpga loadfs ARM: socfpga: Synchronize the configuration for A10 SoCDK ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 + .../include/mach/fpga_manager_arria10.h | 39 +- arch/arm/mach-socfpga/spl_a10.c | 41 +- board/altera/arria10-socdk/fit_spl_fpga.its | 39 ++ configs/socfpga_arria10_defconfig | 21 +- .../fpga/altera-socfpga-a10-fpga-mgr.txt | 26 +- drivers/fpga/socfpga_arria10.c | 467 ++++++++++++++++++++- include/configs/socfpga_common.h | 4 +- include/image.h | 4 + 9 files changed, 626 insertions(+), 32 deletions(-) create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its -- 2.2.0

5 54

[U-Boot] [PATCH] sf: Add Macronix MX25R6435F SPI NOR flash to flash parameters array
by Ye Li 15 Feb '19

15 Feb '19

On i.MX7ULP EVK board, we use MX25R6435F NOR flash, add its parameters and IDs to flash parameter array. Otherwise, the flash probe will fails. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/mtd/spi/spi_flash_ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index ad0a0c8..17f9893 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -94,6 +94,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"mx25u25635f", INFO(0xc22539, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, {"mx66u51235f", INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, {"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) }, + {"mx25r6435f", INFO(0xc22817, 0x0, 64 * 1024, 128, RD_FULL | SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ {"s25fl008a", INFO(0x010213, 0x0, 64 * 1024, 16, 0) }, -- 2.7.4

3 2

[U-Boot] [PATCH v2] mx6ul_14x14_evk: Simplify the PMIC register writes
by Fabio Estevam 15 Feb '19

15 Feb '19

There is no need to store the values written to the PMIC inside the 'reg' variable. Make it simpler by writing the values directly. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- Changes since v1: - Remove 1/2 notation, since this is a standalome patch - Add Peng Fan on Cc board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 595ad76bbe..636c008993 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -86,16 +86,13 @@ int power_init_board(void) pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); /* SW1B step ramp up time from 2us to 4us/25mV */ - reg = 0x40; - pmic_reg_write(dev, PFUZE3000_SW1BCONF, reg); + pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40); /* SW1B mode to APS/PFM */ - reg = 0xc; - pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc); /* SW1B standby voltage set to 0.975V */ - reg = 0xb; - pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb); return 0; } -- 2.17.1

2 1

[U-Boot] [PATCH 1/3] mmc: fsl_esdhc: add esdhc_imx flag
by Y.b. Lu 15 Feb '19

15 Feb '19

The fsl_esdhc driver was for Freescale eSDHC on MPC83XX/MPC85XX initially. The later QoriQ series processors (which are evolutions of MPC83XX/MPC85XX) and i.MX series processors were using this driver for their eSDHCs too. So there are two evolution directions for eSDHC now. For the two series processors, the eSDHCs are becoming more and more different. We should have split it into two drivers, like them (sdhci-of-esdhc.c/sdhci-esdhc-imx.c) in linux kernel. But it seemed to be a lot of work now. So let's keep as it is. Be very careful to change the driver if the changes are not common for all eSDHCs, and clarify i.MX eSDHC specific things to distingush them with QorIQ eSDHC. This patch is to added an esdhc_imx flag for the development of i.MX eSDHC, to distinguish it with QoriQ eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu(a)nxp.com> --- drivers/mmc/fsl_esdhc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 21fa2ab1d4..787a13a8a9 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -147,6 +147,7 @@ struct fsl_esdhc_priv { struct gpio_desc cd_gpio; struct gpio_desc wp_gpio; #endif + bool esdhc_imx; }; /* Return the XFERTYP flags for a given command and data packet */ @@ -1462,6 +1463,16 @@ static int fsl_esdhc_probe(struct udevice *dev) priv->caps = data->caps; } + /* + * This is to specify whether current eSDHC is an i.MX eSDHC, + * since the i.MX eSDHC has been becoming more and more different + * with QorIQ eSDHC and initial MPC83XX/MPC85XX. + */ + if (!fdt_node_check_compatible(fdt, node, "fsl,esdhc")) + priv->esdhc_imx = true; + else + priv->esdhc_imx = false; + val = dev_read_u32_default(dev, "bus-width", -1); if (val == 8) priv->bus_width = 8; -- 2.17.1

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Re: [U-Boot] [PATCH v2] ARM: tegra: enable ums on nyan boards
by Tristan Bastian 15 Feb '19

15 Feb '19

Am 15.02.2019 00:42 schrieb Stephen Warren <swarren(a)wwwdotorg.org>: > > On 2/14/19 4:25 PM, Tristan Bastian wrote: > > This patch enables UMS on the nyan devices like the nyan-big. > > A patch like this has been sent in by Stephen Warren some time ago for other tegra devices: commit e6607cffef965011ef0ddc0fbe6f4b7c0d53aeec > > But the nyan devices never received that functionality. > > > > v2: fixed corrupted patch > > That should be below the ---, but I assume Tom can fix that when > applying the patch. > > Acked-by: Stephen Warren <swarren(a)nvidia.com> > but... > > > diff --git a/arch/arm/dts/tegra124-nyan.dtsi b/arch/arm/dts/tegra124-nyan.dtsi > > index 51895e4816..2b28fe1497 100644 > > --- a/arch/arm/dts/tegra124-nyan.dtsi > > +++ b/arch/arm/dts/tegra124-nyan.dtsi > > @@ -414,6 +414,7 @@ > > > > usb@7d000000 { /* Rear external USB port. */ > > status = "okay"; > > + dr_mode = "otg"; > > nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; > > }; > > Do you also need to add aliases for the USB nodes, like I did in my > similar patch: > > > diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts > > index 52e8c0e59c6b..464287e03ecf 100644 > > --- a/arch/arm/dts/tegra124-jetson-tk1.dts > > +++ b/arch/arm/dts/tegra124-jetson-tk1.dts > > @@ -17,7 +17,8 @@ > > sdhci1 = "/sdhci@700b0400"; > > spi0 = "/spi@7000d400"; > > spi1 = "/spi@7000da00"; > > - usb0 = "/usb@7d008000"; > > + usb0 = "/usb@7d000000"; > > + usb1 = "/usb@7d008000"; > > }; At least for nyan-big this is done in the: tegra124-nyan-big.dts file. So there is no need to also do this here.

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[U-Boot] [PATCH] ARM: dts: uniphier: sync with Linux 5.0-rc2
by Masahiro Yamada 15 Feb '19

15 Feb '19

Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/dts/uniphier-ld20.dtsi | 11 ++++------- arch/arm/dts/uniphier-ld4.dtsi | 14 ++++++++++++++ arch/arm/dts/uniphier-pro4.dtsi | 16 ++++++++++++++++ arch/arm/dts/uniphier-pxs2.dtsi | 6 ++++-- arch/arm/dts/uniphier-sld8.dtsi | 14 ++++++++++++++ 5 files changed, 52 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index b9ed613..a411f4a 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -206,13 +206,10 @@ cooling-maps { map0 { trip = <&cpu_alert>; - cooling-device = <&cpu0 - THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert>; - cooling-device = <&cpu2 - THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index b73d594..c2706ce 100644 --- a/arch/arm/dts/uniphier-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -235,6 +235,16 @@ }; }; + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + sd: sdhc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; @@ -246,6 +256,8 @@ clocks = <&mio_clk 0>; reset-names = "host", "bridge"; resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; bus-width = <4>; cap-sd-highspeed; sd-uhs-sdr12; @@ -263,6 +275,8 @@ clocks = <&mio_clk 1>; reset-names = "host", "bridge", "hw"; resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; bus-width = <8>; cap-mmc-highspeed; cap-mmc-hw-reset; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index ef34208..d090fc7 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -269,6 +269,16 @@ }; }; + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + sd: sdhc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; @@ -280,6 +290,8 @@ clocks = <&mio_clk 0>; reset-names = "host", "bridge"; resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; bus-width = <4>; cap-sd-highspeed; sd-uhs-sdr12; @@ -297,6 +309,8 @@ clocks = <&mio_clk 1>; reset-names = "host", "bridge", "hw"; resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 5>; bus-width = <8>; cap-mmc-highspeed; cap-mmc-hw-reset; @@ -313,6 +327,8 @@ clocks = <&mio_clk 2>; reset-names = "host", "bridge"; resets = <&mio_rst 2>, <&mio_rst 5>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; bus-width = <4>; cap-sd-highspeed; }; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index fa25ffd..4e11e85 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -141,8 +141,10 @@ cooling-maps { map { trip = <&cpu_alert>; - cooling-device = <&cpu0 - THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index f7fcf6b..efce027 100644 --- a/arch/arm/dts/uniphier-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -239,6 +239,16 @@ }; }; + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + sd: sdhc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; @@ -250,6 +260,8 @@ clocks = <&mio_clk 0>; reset-names = "host", "bridge"; resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; bus-width = <4>; cap-sd-highspeed; sd-uhs-sdr12; @@ -267,6 +279,8 @@ clocks = <&mio_clk 1>; reset-names = "host", "bridge", "hw"; resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; bus-width = <8>; cap-mmc-highspeed; cap-mmc-hw-reset; -- 2.7.4

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[U-Boot] [PATCH v2] ARM: tegra: enable ums on nyan boards
by Tristan Bastian 15 Feb '19

15 Feb '19

This patch enables UMS on the nyan devices like the nyan-big. A patch like this has been sent in by Stephen Warren some time ago for other tegra devices: commit e6607cffef965011ef0ddc0fbe6f4b7c0d53aeec But the nyan devices never received that functionality. v2: fixed corrupted patch Signed-off-by: Tristan Bastian <tristan-c.bastian(a)gmx.de> --- arch/arm/dts/tegra124-nyan.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/tegra124-nyan.dtsi b/arch/arm/dts/tegra124-nyan.dtsi index 51895e4816..2b28fe1497 100644 --- a/arch/arm/dts/tegra124-nyan.dtsi +++ b/arch/arm/dts/tegra124-nyan.dtsi @@ -414,6 +414,7 @@ usb@7d000000 { /* Rear external USB port. */ status = "okay"; + dr_mode = "otg"; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; }; -- 2.19.1

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