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February 2019

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[U-Boot] [PATCH] MSCC: Jaguar2 enable debug uart
by Horatiu Vultur 01 Feb '19

01 Feb '19

Enable debug uart for Jaguar2 SoC family. Signed-off-by: Horatiu Vultur <horatiu.vultur(a)microchip.com> --- board/mscc/jr2/jr2.c | 7 +++++++ configs/mscc_jr2_defconfig | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c index eac4dca..226181f 100644 --- a/board/mscc/jr2/jr2.c +++ b/board/mscc/jr2/jr2.c @@ -64,6 +64,13 @@ static void vcoreiii_gpio_set_alternate(int gpio, int mode) } } +void board_debug_uart_init(void) +{ + /* too early for the pinctrl driver, so configure the UART pins here */ + vcoreiii_gpio_set_alternate(10, 1); + vcoreiii_gpio_set_alternate(11, 1); +} + static void do_board_detect(void) { int i; diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index 040e1e1..d80ca41 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -56,3 +56,9 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_LZMA=y +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0x70100000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y -- 2.7.4

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[U-Boot] [PATCH 1/3] fsl_sec: fix register layout on Layerscape architectures
by laurentiu.tudor＠nxp.com 01 Feb '19

01 Feb '19

From: Laurentiu Tudor <laurentiu.tudor(a)nxp.com> On Layerscape architectures the SEC memory map is 1MB and the register blocks contained in it are 64KB aligned, not 4KB as the ccsr_sec structure currently assumes. Fix the layout of the structure for these architectures. Signed-off-by: Laurentiu Tudor <laurentiu.tudor(a)nxp.com> --- include/fsl_sec.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 16e3fcb5a1..be08a2b88b 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -121,10 +121,18 @@ typedef struct ccsr_sec { u32 chanum_ls; /* CHA Number Register, LS */ u32 secvid_ms; /* SEC Version ID Register, MS */ u32 secvid_ls; /* SEC Version ID Register, LS */ +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + u8 res9[0x6f020]; +#else u8 res9[0x6020]; +#endif u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + u8 res10[0x8ffd8]; +#else u8 res10[0x8fd8]; +#endif } ccsr_sec_t; #define SEC_CTPR_MS_AXI_LIODN 0x08000000 -- 2.17.1

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