February 2019 - U-Boot

[U-Boot] [PATCH v2 0/4] sunxi: SPI: Add SUN6I generation SPI support
by Andre Przywara 12 Feb '19

12 Feb '19

We already have a driver for the SPI devices in older Allwinner CPUs. Newer SoCs (SUN6I generation) have a similar, but improved IP block. This series adds support for that, so we can access the SPI flash that some newer boards come with. This series gathers some patches that have appeared on the list in one form or another before (hence the v2 tag), but brings them all together and updates them. The SUN4I/SUN6I SPI devices share a very similar architecure, but differ annoyingly in quite some details, to a point where a shared driver would look unnecessarily complicated. So we use an #ifdef based approach, which keeps the driver simple, at the cost of not being able to access both types of device in one binary build. But since there are no SoCs which feature both types, this is a theoretical disadvantage. Patch 1/4 moves the clock toggling from the probe/remove to the claim/release-bus stage. Patch 2/4 adds the SPI gate clocks and reset gates to the clock drivers, also describes at least the enable bit for the SPI mod clock. This is used in patch 3/4, which uses the new DM clock framework in the driver, helping to abstract differences between the SUN4I/SUN6I types. Patch 4/4 eventually adds support for the new SUN6I generation SPI device. The actual device support is determined at compile time, based on the CONFIG_SUNXI_GEN_SUN6I symbol. What's left out of this series is the config bits needed to actually activate the support for a board. At the moment this is unnecessarily verbose, so that Oskari is looking at simplifying this at the Kconfig level, which would complement this series. This has been briefly tested on the Pine64-LTS and the OrangePi PC2 board. Please test them if you have other devices with a SUN6I SPI generation. Cheers, Andre. Jagan Teki (2): clk: sunxi: Implement SPI gates clocks and reset spi: sunxi: Add CLK support to Allwinner SPI driver Oskari Lemmela (2): spi: sunxi: Enable and disable SPI clock on bus claim/release spi: sunxi: Support newer SoCs drivers/clk/sunxi/clk_a10.c | 9 +++ drivers/clk/sunxi/clk_a10s.c | 7 ++ drivers/clk/sunxi/clk_a23.c | 7 ++ drivers/clk/sunxi/clk_a31.c | 13 ++++ drivers/clk/sunxi/clk_a64.c | 7 ++ drivers/clk/sunxi/clk_a80.c | 15 ++++ drivers/clk/sunxi/clk_a83t.c | 7 ++ drivers/clk/sunxi/clk_h3.c | 7 ++ drivers/clk/sunxi/clk_h6.c | 6 ++ drivers/clk/sunxi/clk_r40.c | 13 ++++ drivers/clk/sunxi/clk_v3s.c | 4 + drivers/spi/Kconfig | 4 +- drivers/spi/sun4i_spi.c | 177 +++++++++++++++++++++++++++++++++++++------ 13 files changed, 252 insertions(+), 24 deletions(-) -- 2.14.5

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[U-Boot] [PATCH 1/3] spi: Kconfig: Mark CONFIG_SPI as Legacy spi support
by Jagan Teki 12 Feb '19

12 Feb '19

CONFIG_SPI is mandatory for SPI support even if the given board has dm or non-dm versions, so mark CONFIG_SPI as non-dm config option and move the respective non-dm drivers below to that. This eventually reduce the explicit CONFIG_SPI enablement for dm version spi drivers. Cc: Vignesh R <vigneshr(a)ti.com> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/spi/Kconfig | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2fb4862c4a..bed279cbc4 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -1,7 +1,4 @@ -menuconfig SPI - bool "SPI Support" - -if SPI +menu "SPI Support" config DM_SPI bool "Enable Driver Model for SPI drivers" @@ -294,6 +291,14 @@ config ZYNQMP_GQSPI endif # if DM_SPI +config SPI + bool "Legacy SPI support" + help + Enable the legacy SPI support. This will include legacy SPI + interface code for non-dm SPI drivers. + +if SPI + config SOFT_SPI bool "Soft SPI driver" help @@ -387,4 +392,6 @@ config OMAP3_SPI (McSPI). This driver be used to access SPI chips on platforms embedding this OMAP3 McSPI IP core. -endif # menu "SPI Support" +endif # if SPI + +endmenu # menu "SPI Support" -- 2.18.0.321.gffc6fa0e3

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[U-Boot] [PATCH] configs: tbs_a711: lower dram frequency
by Tomas Novotny 12 Feb '19

12 Feb '19

The dram chip on the tablet was changed. The new one requires a lower frequency, so change it. Frequency 564 was also stable in the tests, but use slightly lower one to be on a safe side. Signed-off-by: Tomas Novotny <tomas(a)novotny.cz> --- configs/tbs_a711_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig index 103ce9be46..2b2d7ade2a 100644 --- a/configs/tbs_a711_defconfig +++ b/configs/tbs_a711_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_SPL=y CONFIG_MACH_SUN8I_A83T=y CONFIG_DRAM_TYPE=7 -CONFIG_DRAM_CLK=648 +CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -- 2.12.3

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[U-Boot] [PATCH v4 0/3] stm32mp1: add trusted boot with TF-A
by Patrick Delaunay 12 Feb '19

12 Feb '19

This patch serie add a new configuration stm32mp15_trusted_defconfig to handle STM32MP157 boards with TF-A as secure first stage bootloader. TF-A code is available in GitHub https://github.com/ARM-software/arm-trusted-firmware With platform stm32mp1 platform https://github.com/ARM-software/arm-trusted-firmware/tree/master/plat/st/st… For details, see documentation https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/… PS: upstream of trusted boot for TF-A is still in progress. Changes in v4: - Rebase on master - add CONFIG_CMD_CLK in trusted defconfig (allignment with basic defconfig) Changes in v3: - Remove patch 4/4 added by error in v2 and sent by other serie http://patchwork.ozlabs.org/patch/1033475/ Changes in v2: - Rebase and solve conflict on arch/arm/mach-stm32mp/config.mk Patrick Delaunay (3): stm32mp1: add trusted boot with TF-A stm32mp1: bsec: access with SMC for trusted boot stm32mp1: display board information arch/arm/Kconfig | 6 ++- arch/arm/mach-stm32mp/Kconfig | 17 ++++-- arch/arm/mach-stm32mp/bsec.c | 28 ++++++++++ arch/arm/mach-stm32mp/config.mk | 15 +++++- arch/arm/mach-stm32mp/cpu.c | 9 +++- arch/arm/mach-stm32mp/include/mach/stm32.h | 4 ++ arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h | 64 +++++++++++++++++++++++ board/st/stm32mp1/MAINTAINERS | 5 +- board/st/stm32mp1/README | 56 ++++++++++++++------ board/st/stm32mp1/stm32mp1.c | 44 +++++++++++++++- configs/stm32mp15_trusted_defconfig | 58 ++++++++++++++++++++ drivers/clk/clk_stm32mp1.c | 2 + drivers/ram/stm32mp1/stm32mp1_ram.c | 3 +- include/configs/stm32mp1.h | 2 + 14 files changed, 283 insertions(+), 30 deletions(-) create mode 100644 arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h create mode 100644 configs/stm32mp15_trusted_defconfig -- 2.7.4

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[U-Boot] [PATCH 1/2] xilinx: Move zynq_board_read_rom_ethaddr to shared location
by Michal Simek 12 Feb '19

12 Feb '19

Zynq and ZynqMP are sharing similar code and there is no reason to do code duplication. Move zynq_board_read_rom_ethaddr() to common file for easier conversion to DM. Use ZynqMP version that's why also add CONFIG_ZYNQ_EEPROM_BUS to Syzygy which is only one Zynq board which is using this feature. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- board/opalkelly/zynq/board.c | 2 ++ board/xilinx/common/board.c | 25 +++++++++++++++++++++++++ board/xilinx/zynq/Makefile | 1 + board/xilinx/zynq/board.c | 13 ------------- board/xilinx/zynqmp/Makefile | 1 + board/xilinx/zynqmp/zynqmp.c | 17 ----------------- include/configs/syzygy_hub.h | 1 + 7 files changed, 30 insertions(+), 30 deletions(-) create mode 100644 board/xilinx/common/board.c diff --git a/board/opalkelly/zynq/board.c b/board/opalkelly/zynq/board.c index a95c9d1eff0f..ee666185ec09 100644 --- a/board/opalkelly/zynq/board.c +++ b/board/opalkelly/zynq/board.c @@ -1 +1,3 @@ +#include "../../xilinx/common/board.c" + #include "../../xilinx/zynq/board.c" diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c new file mode 100644 index 000000000000..7e813d856404 --- /dev/null +++ b/board/xilinx/common/board.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 - 2019 Xilinx, Inc. + * Michal Simek <michal.simek(a)xilinx.com> + */ + +#include <common.h> +#include <dm/uclass.h> +#include <i2c.h> + +int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) +{ +#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ + defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \ + defined(CONFIG_ZYNQ_EEPROM_BUS) + i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS); + + if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, + CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, + ethaddr, 6)) + printf("I2C EEPROM MAC address read failed\n"); +#endif + + return 0; +} diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index e7645be189c3..8d3301543959 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -4,6 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. obj-y := board.o +obj-y += ../common/board.o ifneq ($(CONFIG_XILINX_PS_INIT_FILE),"") PS_INIT_FILE := $(shell cd $(srctree); readlink -f $(CONFIG_XILINX_PS_INIT_FILE)) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 614d93c082a6..f9973840bf20 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -77,19 +77,6 @@ int board_late_init(void) return 0; } -int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) -{ -#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ - defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) - if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, - CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, - ethaddr, 6)) - printf("I2C EEPROM MAC address read failed\n"); -#endif - - return 0; -} - #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) int dram_init_banksize(void) { diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 960b81fc5853..80f8ca7e1e4b 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -4,6 +4,7 @@ # Michal Simek <michal.simek(a)xilinx.com> obj-y := zynqmp.o +obj-y += ../common/board.o ifneq ($(CONFIG_XILINX_PS_INIT_FILE),"") PS_INIT_FILE := $(shell cd $(srctree); readlink -f $(CONFIG_XILINX_PS_INIT_FILE)) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 41e88b03f9d1..e7dfd49a3ccf 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -20,7 +20,6 @@ #include <usb.h> #include <dwc3-uboot.h> #include <zynqmppl.h> -#include <i2c.h> #include <g_dnl.h> DECLARE_GLOBAL_DATA_PTR; @@ -409,22 +408,6 @@ int board_early_init_r(void) return 0; } -int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) -{ -#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ - defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \ - defined(CONFIG_ZYNQ_EEPROM_BUS) - i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS); - - if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, - CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, - ethaddr, 6)) - printf("I2C EEPROM MAC address read failed\n"); -#endif - - return 0; -} - unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, char * const argv[]) { diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h index 88ee77284890..75036977d486 100644 --- a/include/configs/syzygy_hub.h +++ b/include/configs/syzygy_hub.h @@ -12,6 +12,7 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x57 +#define CONFIG_ZYNQ_EEPROM_BUS 0 #define CONFIG_EXTRA_ENV_SETTINGS \ "fit_image=fit.itb\0" \ -- 1.9.1

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[U-Boot] [PATCH v1] x86: tangier: Add initial ACPI support for PMIC device
by Andy Shevchenko 12 Feb '19

12 Feb '19

Basin Cove PMIC is connected to I2C0 bus which is hidden from the OS and access is going via SCU device, enumerated via PCI. For now, we add just a minimum support of PMIC device to allow enabling, e.g. USB OTG, in the OS. Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- .../asm/arch-tangier/acpi/southcluster.asl | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index e166e510cb..b08d852e59 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -320,6 +320,92 @@ Device (PCI0) }) } } + + Device (IPC1) + { + Name (_ADR, 0x00130000) + + Method (_STA, 0, NotSerialized) + { + Return (STA_VISIBLE) + } + + Device (PMIC) + { + Name (_ADR, Zero) + Name (_HID, "INTC100E") + Name (_CID, "INTC100E") + Name (_DDN, "Basin Cove PMIC") + Name (_DEP, Package () + { + IPC1 + }) + Method (_STA, 0, NotSerialized) + { + Return (STA_VISIBLE) + } + + Method (_CRS, 0, Serialized) + { + Name (RBUF, ResourceTemplate() + { + /* + * Shadow registers in SRAM for PMIC: + * SRAM PMIC register + * -------------------- + * 0x00- Unknown + * 0x03 THRMIRQ (0x04) + * 0x04 BCUIRQ (0x05) + * 0x05 ADCIRQ (0x06) + * 0x06 CHGRIRQ0 (0x07) + * 0x07 CHGRIRQ1 (0x08) + * 0x08- Unknown + * 0x0a PBSTATUS (0x27) + * 0x0b- Unknown + */ + Memory32Fixed(ReadWrite, 0xFFFFF610, 0x00000010) + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 30 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 23 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 52 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 51 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 50 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 27 } + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 49 } + }) + Return (RBUF) + } + + OperationRegion (PMOP, 0x8D, Zero, 0x0100) + Field (PMOP, DWordAcc, NoLock, Preserve) + { + SEL1, 32, + SEL2, 32, + VCCL, 32, + VNNL, 32, + AONL, 32, + CNTC, 32, + CNTN, 32, + AONN, 32, + CNT1, 32, + CNT2, 32, + CNT3, 32, + FLEX, 32, + PRG1, 32, + PRG2, 32, + PRG3, 32, + VLDO, 32, + } + + Name (AVBL, Zero) + Method (_REG, 2, NotSerialized) + { + If ((Arg0 == 0x8D)) + { + AVBL = Arg1 + } + } + } + } } Device (FLIS) -- 2.20.1

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[U-Boot] [PATCH 1/3] x86: Change 4-level page table base address to low memory
by Bin Meng 12 Feb '19

12 Feb '19

At present the 4-level page table base address for 64-bit U-Boot proper is assigned an address that conflicts with CONFIG_LOADADDR. Change it to an address within the low memory range instead. Fixes crashes seen when 'dhcp' on QEMU x86_64 with "-net nic -net user,tftp=.,bootfile=u-boot". Reported-by: Alexander Graf <agraf(a)suse.de> Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/i386/cpu.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 208ef08..af42431 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -462,6 +462,7 @@ int cpu_has_64bit(void) has_long_mode(); } +#define PAGETABLE_BASE 0x80000 #define PAGETABLE_SIZE (6 * 4096) /** @@ -523,10 +524,7 @@ int cpu_jump_to_64bit_uboot(ulong target) uint32_t *pgtable; func_t func; - /* TODO(sjg(a)chromium.org): Find a better place for this */ - pgtable = (uint32_t *)0x1000000; - if (!pgtable) - return -ENOMEM; + pgtable = (uint32_t *)PAGETABLE_BASE; build_pagetable(pgtable); -- 2.7.4

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[U-Boot] [PATCH] Fix : Uboot crash when booting from SD.
by Meenakshi Aggarwal 12 Feb '19

12 Feb '19

Issue : In case of SD boot, u-boot was crashing due to DDR was not coherent Fix : Making DDR as device memory will make sure DDR is coherent when we are relocating the code Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> Signed-off-by: Udit Kumar <udit.kumar(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 978d46b..cb1abf3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -102,7 +102,7 @@ static struct mm_region early_map[] = { CONFIG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_TFABOOT) || \ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) - PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | #endif -- 1.9.1

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[U-Boot] [PATCH 0/7] Add netcp networking support on K2G ICE EVM
by Murali Karicheri 12 Feb '19

12 Feb '19

This patch series add networking capability to K2G ICE EVM based on netcp driver. Networking function has been tested using the latest master branch from u-boot repo. Following boot mode has been tested for networking. Net boot (tftp images over ethernet interface and boot kernel) log at https://pastebin.ubuntu.com/p/b3nyCXPhWc/ MMC boot: (load images from boot folder of rootfs and boot kernel) log at https://pastebin.ubuntu.com/p/FWycmKd9KB/ Used Linux upstream linux kernel version 4.19.9 for the tests. Please review and apply if this looks good. Thanks Murali Karicheri (7): ARM: k2g-ice: Add pinmux support for rgmii interface ARM: k2g-gp-evm: update to rgmii pinmux configuration net: netcp: add support for phy with rgmii ids ARM: k2g: add a workaround to reset the phy k2g: config enable ti phy dp83867 for k2g ARM: dts: k2g-evm: remove unused phy-mode property from phy node ARM: dts: k2g-ice: add dt node for netcp arch/arm/dts/keystone-k2g-evm.dts | 1 - arch/arm/dts/keystone-k2g-ice.dts | 35 +++++++++++++ .../mach-keystone/include/mach/hardware-k2g.h | 3 ++ arch/arm/mach-keystone/include/mach/mux-k2g.h | 5 ++ board/ti/ks2_evm/board_k2g.c | 15 ++++++ board/ti/ks2_evm/mux-k2g.h | 51 +++++++++++++------ drivers/net/ti/keystone_net.c | 22 +++++++- include/configs/k2g_evm.h | 1 + 8 files changed, 116 insertions(+), 17 deletions(-) -- 2.17.0

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[U-Boot] FW: [PATCHv3 00/11] pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs
by Prabhakar Kushwaha 12 Feb '19

12 Feb '19

[Re-sending after including mailing list] Dear Tom, > -----Original Message----- > From: Z.q. Hou > Sent: Friday, January 25, 2019 3:33 PM > To: u-boot(a)lists.denx.de; albert.u.boot(a)aribaud.net; Priyanka Jain > <priyanka.jain(a)nxp.com>; York Sun <york.sun(a)nxp.com>; > sriram.dash(a)nxp.com; yamada.masahiro(a)socionext.com; Prabhakar Kushwaha > <prabhakar.kushwaha(a)nxp.com>; Mingkai Hu <mingkai.hu(a)nxp.com>; M.h. > Lian <minghuan.lian(a)nxp.com> > Cc: Z.q. Hou <zhiqiang.hou(a)nxp.com> > Subject: [PATCHv3 00/11] pci: Add PCIe Gen4 controller driver for NXP > Layerscape SoCs > > From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> > > Add PCIe Gen4 driver for the NXP Layerscape series SoCs. > > Hou Zhiqiang (11): > armv8: fsl-layerscpae: correct the PCIe controllers' region size > armv8: lx2160a: add MMU table entries for PCIe > pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs > kconfig: add dependency PCIE_LAYERSCAPE_GEN4 for FSL_PCIE_COMPAT > pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs > armv8: lx2160a: add PCIe controller DT nodes > armv8: lx2160a: enable PCIe support on RDB defconfig > armv8: lx2160a: enable the pci command > pci: ls_pcie_g4: add Workaround for A-011577 > pci: ls_pcie_g4: Add Workaround for A-011451 > pci: ls_pcie_g4: add Workaround for A-011452 > > Depends on the following patches: > https://patchwork.ozlabs.org/patch/990088/ > https://patchwork.ozlabs.org/patch/990093/ > https://patchwork.ozlabs.org/patch/990097/ > https://patchwork.ozlabs.org/patch/990098/ > > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 12 + > arch/arm/dts/fsl-lx2160a.dtsi | 85 +++ > .../arm/include/asm/arch-fsl-layerscape/cpu.h | 9 + > .../asm/arch-fsl-layerscape/immap_lsch3.h | 14 +- > configs/lx2160ardb_tfa_defconfig | 5 + > drivers/pci/Kconfig | 8 + > drivers/pci/Makefile | 2 + > drivers/pci/pci_auto.c | 34 + > drivers/pci/pcie_layerscape_gen4.c | 593 ++++++++++++++++++ > drivers/pci/pcie_layerscape_gen4.h | 273 ++++++++ > drivers/pci/pcie_layerscape_gen4_fixup.c | 249 ++++++++ > include/configs/lx2160a_common.h | 1 + > include/pci.h | 9 + > include/pci_ids.h | 1 + > 15 files changed, 1295 insertions(+), 2 deletions(-) create mode > 100644 drivers/pci/pcie_layerscape_gen4.c > create mode 100644 drivers/pci/pcie_layerscape_gen4.h > create mode 100644 drivers/pci/pcie_layerscape_gen4_fixup.c > Sorry for my unawareness, who is maintainer for driver/pci. I am finding multiple names for driver pcie. Simon Glass <sjg(a)chromium.org> (commit_signer:20/37=54%) Bin Meng <bmeng.cn(a)gmail.com> (commit_signer:19/37=51%,authored:11/37=30%) Stefan Roese <sr(a)denx.de> (commit_signer:4/37=11%,authored:2/37=5%) York Sun <york.sun(a)nxp.com> (commit_signer:4/37=11%) Tuomas Tynkkynen <tuomas.tynkkynen(a)iki.fi> (commit_signer:3/37=8%,authored:3/37=8%) Xiaowei Bao <xiaowei.bao(a)nxp.com> (authored:3/37=8%) u-boot(a)lists.denx.de (open list) considering this patch-set is touching driver/pci. I would like PCI maintainer to have a look. Patch related to arch/arm/../fsl-layerscape can be reviewed by me. --pk

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