November 2019 - U-Boot

[U-Boot] [RFC PATCH] ARM: reset: Move SYSRESET condition from Makefile into source file
by Claudius Heine 28 Nov '19

28 Nov '19

In case CONFIG_SYSRESET is set, do_reset from reset.c will not be available anywere, even if SYSRESET is disabled for SPL in the board specific header file like this: #if defined(CONFIG_SPL_BUILD) #undef CONFIG_WDT #undef CONFIG_WATCHDOG #undef CONFIG_SYSRESET #define CONFIG_HW_WATCHDOG #endif 'do_reset' is called from SPL for instance from the panic handler in case SPL_USB_SDP is enabled and PANIC_HANG is not set. Setting PANIC_HANG would solve this issue, but it also changes the behavior in case a panic occurs. Signed-off-by: Claudius Heine <ch(a)denx.de> --- arch/arm/lib/Makefile | 2 -- arch/arm/lib/reset.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 9de9a9acee..763eb4498f 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -56,9 +56,7 @@ obj-y += interrupts_64.o else obj-y += interrupts.o endif -ifndef CONFIG_SYSRESET obj-y += reset.o -endif obj-y += cache.o obj-$(CONFIG_SYS_ARM_CACHE_CP15) += cache-cp15.o diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index f3ea116e87..11e680be1d 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -22,6 +22,7 @@ #include <common.h> +#if !defined(CONFIG_SYSRESET) __weak void reset_misc(void) { } @@ -40,3 +41,4 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /*NOTREACHED*/ return 0; } +#endif -- 2.21.0

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[U-Boot] [PATCH v2 1/2] rockchip: dwmmc: add handling for u-boot, spl-fifo-mode
by Heiko Stuebner 28 Nov '19

28 Nov '19

From: Heiko Stuebner <heiko.stuebner(a)theobroma-systems.com> Rockchips dwmmc controllers can't do dma to non-ddr addresses, like for example the soc-internal sram but during boot parts of TrustedFirmware need to be placed there from the read FIT image. So add handling for a u-boot,spl-fifo-mode to not put the mmc controllers into fifo mode for all time. The regular fifo-mode property still takes precedent and only if not set do we check for the spl-specific property. Suggested-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> Signed-off-by: Heiko Stuebner <heiko.stuebner(a)theobroma-systems.com> --- drivers/mmc/rockchip_dw_mmc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index b2a1201631..a0e1be8794 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -72,6 +72,11 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) return -EINVAL; priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); +#ifdef CONFIG_SPL_BUILD + if (!priv->fifo_mode) + priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode"); +#endif + /* * 'clock-freq-min-max' is deprecated * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab6…) -- 2.24.0

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[U-Boot] [PATCH v8 00/19] Add Intel Agilex SoC support
by Ley Foon Tan 28 Nov '19

28 Nov '19

This is 8th version of patchset to add Intel Agilex SoC[1] support. This patchset needs to apply after patchset in [2] for manager driver struct to defines conversion and [3] for enable cache driver build in SPL. Patch status: Have changes: Patch 12, 17 Other patches unchanged. Detail changelog can find in commit message. Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in Agilex are CCU, clock manager and SDRAM, other IPs have minor changes compared to Stratix 10. Intel Agilex HPS TRM: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb… v7->v8: ------- Patch 12: - Fixed missing CONFIG_ prefix for TARGET_SOCFPGA_STRATIX10. Patch 17: - Include socfpga_agilex-u-boot.dtsi in socfpga_agilex_socdk-u-boot.dtsi, instead of include it in socfpga_agilex_socdk.dts. History: --------- [v1]: https://patchwork.ozlabs.org/cover/1097830/ [v2]: https://patchwork.ozlabs.org/cover/1127440/ [v3]: https://patchwork.ozlabs.org/cover/1149863/ [v4]: https://patchwork.ozlabs.org/cover/1161483/ [v5]: https://patchwork.ozlabs.org/cover/1175076/ [v6]: https://patchwork.ozlabs.org/cover/1191577/ [v7]: https://patchwork.ozlabs.org/cover/1200811/ [1]: https://www.intel.com/content/www/us/en/products/programmable/fpga/agilex.h… [2]: https://patchwork.ozlabs.org/cover/1191562/ ("arm: socfpga: Convert drivers from struct to defines") [3]: https://patchwork.ozlabs.org/patch/1191569/ ("spl: Allow cache drivers to be used in SPL") Ley Foon Tan (19): arm: socfpga: agilex: Add base address for Intel Agilex SoC arm: socfpga: Move firewall code to firewall file arm: socfpga: Move Stratix10 and Agilex reset manager common code arm: socfpga: agilex: Add reset manager support arm: socfpga: Move Stratix10 and Agilex system manager common code arm: socfpga: agilex: Add system manager support arm: socfpga: Move Stratix10 and Agilex clock manager common code arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz clk: agilex: Add clock driver for Agilex arm: socfpga: agilex: Add clock wrapper functions cache: Add Arteris Ncore cache coherent unit driver arm: agilex: Add clock handoff offset for Agilex ddr: altera: Restructure Stratix 10 SDRAM driver ddr: altera: agilex: Add SDRAM driver for Agilex board: intel: agilex: Add socdk board support for Intel Agilex SoC arm: socfpga: agilex: Add SPL for Agilex SoC arm: dts: agilex: Add base dtsi and devkit dts configs: socfpga: Move Stratix10 and Agilex common CONFIGs arm: socfpga: agilex: Enable Agilex SoC build arch/arm/Kconfig | 4 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex-u-boot.dtsi | 96 +++ arch/arm/dts/socfpga_agilex.dtsi | 622 ++++++++++++++++++ arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 39 ++ arch/arm/dts/socfpga_agilex_socdk.dts | 141 ++++ arch/arm/mach-socfpga/Kconfig | 16 + arch/arm/mach-socfpga/Makefile | 17 + arch/arm/mach-socfpga/clock_manager_agilex.c | 85 +++ arch/arm/mach-socfpga/clock_manager_s10.c | 3 +- .../mach-socfpga/{spl_s10.c => firewall.c} | 122 +--- .../mach-socfpga/include/mach/base_addr_s10.h | 4 + .../mach-socfpga/include/mach/clock_manager.h | 2 + .../include/mach/clock_manager_agilex.h | 14 + .../include/mach/clock_manager_s10.h | 16 +- .../include/mach/clock_manager_soc64.h | 21 + .../mach/{firewall_s10.h => firewall.h} | 10 +- .../mach-socfpga/include/mach/handoff_s10.h | 9 +- .../mach-socfpga/include/mach/reset_manager.h | 5 +- .../include/mach/reset_manager_s10.h | 95 --- .../include/mach/reset_manager_soc64.h | 38 ++ .../include/mach/system_manager.h | 5 +- .../include/mach/system_manager_s10.h | 124 ---- .../include/mach/system_manager_soc64.h | 123 ++++ arch/arm/mach-socfpga/mailbox_s10.c | 2 +- arch/arm/mach-socfpga/misc.c | 5 + arch/arm/mach-socfpga/misc_s10.c | 2 +- arch/arm/mach-socfpga/reset_manager_s10.c | 35 +- arch/arm/mach-socfpga/spl_agilex.c | 98 +++ arch/arm/mach-socfpga/spl_s10.c | 95 +-- arch/arm/mach-socfpga/system_manager_s10.c | 26 +- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 15 +- board/intel/agilex-socdk/MAINTAINERS | 7 + board/intel/agilex-socdk/Makefile | 7 + board/intel/agilex-socdk/socfpga.c | 7 + configs/socfpga_agilex_defconfig | 60 ++ drivers/cache/Kconfig | 8 + drivers/cache/Makefile | 1 + drivers/cache/cache-ncore.c | 164 +++++ drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex.c | 579 ++++++++++++++++ drivers/clk/altera/clk-agilex.h | 237 +++++++ drivers/ddr/altera/Kconfig | 6 +- drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_agilex.c | 168 +++++ drivers/ddr/altera/sdram_s10.c | 298 +-------- drivers/ddr/altera/sdram_s10.h | 148 +---- drivers/ddr/altera/sdram_soc64.c | 304 +++++++++ .../ddr/altera/{sdram_s10.h => sdram_soc64.h} | 71 +- include/configs/socfpga_agilex_socdk.h | 12 + ...ratix10_socdk.h => socfpga_soc64_common.h} | 14 +- include/configs/socfpga_stratix10_socdk.h | 193 +----- include/dt-bindings/clock/agilex-clock.h | 71 ++ 53 files changed, 3091 insertions(+), 1158 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c copy arch/arm/mach-socfpga/{spl_s10.c => firewall.c} (53%) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h rename arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} (94%) delete mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h delete mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_soc64.h create mode 100644 arch/arm/mach-socfpga/spl_agilex.c create mode 100644 board/intel/agilex-socdk/MAINTAINERS create mode 100644 board/intel/agilex-socdk/Makefile create mode 100644 board/intel/agilex-socdk/socfpga.c create mode 100644 configs/socfpga_agilex_defconfig create mode 100644 drivers/cache/cache-ncore.c create mode 100644 drivers/clk/altera/clk-agilex.c create mode 100644 drivers/clk/altera/clk-agilex.h create mode 100644 drivers/ddr/altera/sdram_agilex.c create mode 100644 drivers/ddr/altera/sdram_soc64.c copy drivers/ddr/altera/{sdram_s10.h => sdram_soc64.h} (79%) create mode 100644 include/configs/socfpga_agilex_socdk.h copy include/configs/{socfpga_stratix10_socdk.h => socfpga_soc64_common.h} (94%) create mode 100644 include/dt-bindings/clock/agilex-clock.h -- 2.19.0

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[U-Boot] [PATCH] cmd: pxe: Increase maximum path length
by Ben Wolsieffer 28 Nov '19

28 Nov '19

On NixOS, cross compiled kernels have long suffixes that cause them to exceed the current maximum path length. The PXE/TFTP max path length is used for extlinux.conf support as well, which is where this problem usually manifest's itself. Signed-off-by: Ben Wolsieffer <benwolsieffer(a)gmail.com> --- cmd/pxe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/pxe.c b/cmd/pxe.c index 2059975446..744cd82730 100644 --- a/cmd/pxe.c +++ b/cmd/pxe.c @@ -21,7 +21,7 @@ #include "menu.h" #include "cli.h" -#define MAX_TFTP_PATH_LEN 127 +#define MAX_TFTP_PATH_LEN 512 const char *pxe_default_paths[] = { #ifdef CONFIG_SYS_SOC -- 2.24.0

1 0

[U-Boot] [PATCH v2 0/8] rockchip: rk3399: Use spl_board_init in SPL, TPL
by Jagan Teki 28 Nov '19

28 Nov '19

This is v2 set for previous v1. No much diff, except the latest rebase. Usually spl_board_init has preloader_console_init which would help to print boot up banner during SPL and TPL. The current rk3399 lacking that in few of the boards, this series make reuse of spl_board_init in SPL and TPL stages. with this series: ================ U-Boot TPL 2019.07-rc1-00243-g3f0cad6bd2 (May 08 2019 - 11:29:32 +0530) Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2019.07-rc1-00243-g3f0cad6bd2 (May 08 2019 - 11:29:32 +0530) Trying to boot from MMC1 U-Boot 2019.07-rc1-00243-g3f0cad6bd2 (May 08 2019 - 11:29:32 +0530) Model: FriendlyElec NanoPC-T4 DRAM: 3.9 GiB MMC: dwmmc@fe310000: 2, dwmmc@fe320000: 1, sdhci@fe330000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@ff1a0000 Out: serial@ff1a0000 Err: serial@ff1a0000 Model: FriendlyElec NanoPC-T4 Net: eth0: ethernet@fe300000 Hit any key to stop autoboot: 0 => without this series: =================== U-Boot TPL board init Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL board init Trying to boot from MMC1 U-Boot 2019.07-rc1-00243-g3f0cad6bd2 (May 08 2019 - 11:29:32 +0530) Model: FriendlyElec NanoPC-T4 DRAM: 3.9 GiB MMC: dwmmc@fe310000: 2, dwmmc@fe320000: 1, sdhci@fe330000: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@ff1a0000 Out: serial@ff1a0000 Err: serial@ff1a0000 Model: FriendlyElec NanoPC-T4 Net: eth0: ethernet@fe300000 Hit any key to stop autoboot: 0 => Any inputs? Jagan. Jagan Teki (8): board: rk3399: Drop explicit uart enablement in spl_board_init rockchip: rk3399: Support common spl_board_init rockchip: rk3399: spl: Mark printascii into debug rockchip: rk3399: Move u-boot, dm-pre-reloc of uart0, uart2 rockchip: rk3399: Enable SPL_BOARD_INIT rockchip: rk3399: tpl: Add spl_board_init rockchip: rk3399: tpl: Mark printascii into debug rockchip: rk3399: Enable TPL_BOARD_INIT arch/arm/dts/rk3399-gru.dtsi | 1 - arch/arm/dts/rk3399-puma.dtsi | 1 - arch/arm/dts/rk3399-u-boot.dtsi | 8 +++ arch/arm/mach-rockchip/Kconfig | 2 + arch/arm/mach-rockchip/rk3399-board-spl.c | 65 ++++++++++++++++++- arch/arm/mach-rockchip/rk3399-board-tpl.c | 9 ++- board/rockchip/evb_rk3399/evb-rk3399.c | 29 --------- .../puma_rk3399/puma-rk3399.c | 58 ----------------- board/vamrs/rock960_rk3399/rock960-rk3399.c | 31 --------- configs/puma-rk3399_defconfig | 1 - 10 files changed, 82 insertions(+), 123 deletions(-) -- 2.18.0.321.gffc6fa0e3

3 17

[U-Boot] [PATCH v1] configs: ls1028ardb: enable ugreen usb network card AX88179 and AX8817X drvier
by Yinbo Zhu 28 Nov '19

28 Nov '19

enable ls1028ardb ugreen usb network card AX88179 and AX8817X driver Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- configs/ls1028ardb_tfa_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 0664014..fc6d2ec 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -78,4 +78,6 @@ CONFIG_WDT_SP805=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -- 2.7.4

1 0

[U-Boot] [PATCH 1/5] Revert "powerpc: mpc85xx: delete FSL_SATA for T2080QDS board."
by Peng Ma 28 Nov '19

28 Nov '19

This reverts commit 856b9cdb53f0e6c8d98f81cf71ef363c16b0aa0e. Signed-off-by: Peng Ma <peng.ma(a)nxp.com> --- arch/powerpc/cpu/mpc85xx/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 8cc82f80b4..6fc6ea8fef 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -352,6 +352,7 @@ config TARGET_T2080QDS select PHYS_64BIT select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE select FSL_DDR_INTERACTIVE + imply CMD_SATA config TARGET_T2080RDB bool "Support T2080RDB" @@ -360,7 +361,6 @@ config TARGET_T2080RDB select SUPPORT_SPL select PHYS_64BIT imply CMD_SATA - imply FSL_SATA imply PANIC_HANG config TARGET_T2081QDS @@ -1099,8 +1099,10 @@ config ARCH_T2080 select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 select FSL_IFC + imply CMD_SATA imply CMD_NAND imply CMD_REGINFO + imply FSL_SATA config ARCH_T2081 bool -- 2.17.1

3 9

[U-Boot] [PATCH v2] ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT
by Alex Marginean 27 Nov '19

27 Nov '19

Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean(a)nxp.com> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - moved code under arm/cpu from board as it's in fact SoC related Replaces v1 and this earlier patch: https://patchwork.ozlabs.org/patch/1144486/ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 ++ arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 9 ++ .../arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 93 +++++++++++++++++++ .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 8 ++ 4 files changed, 119 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 83a3319321..c6490556e6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1098,6 +1098,12 @@ static void config_core_prefetch(void) } } +#ifdef CONFIG_PCIE_ECAM_GENERIC +__weak void set_ecam_icids(void) +{ +} +#endif + int arch_early_init_r(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 @@ -1149,6 +1155,9 @@ int arch_early_init_r(void) #endif #ifdef CONFIG_SYS_DPAA_QBMAN setup_qbman_portals(); +#endif +#ifdef CONFIG_PCIE_ECAM_GENERIC + set_ecam_icids(); #endif return 0; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index e993209593..1e7e46e88a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -421,6 +421,12 @@ static void fdt_disable_multimedia(void *blob, unsigned int svr) } #endif +#ifdef CONFIG_PCIE_ECAM_GENERIC +__weak void fdt_fixup_ecam(void *blob) +{ +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -485,4 +491,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_ARCH_LS1028A fdt_disable_multimedia(blob, svr); #endif +#ifdef CONFIG_PCIE_ECAM_GENERIC + fdt_fixup_ecam(blob); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c index 9462298fbf..8110412da6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -33,3 +33,96 @@ struct icid_id_table icid_tbl[] = { }; int icid_tbl_sz = ARRAY_SIZE(icid_tbl); + +/* integrated PCI is handled separately as it's not part of CCSR/SCFG */ +#ifdef CONFIG_PCIE_ECAM_GENERIC + +#define ECAM_IERB_BASE 0x1f0800000ULL +#define ECAM_IERB_OFFSET_NA -1 +#define ECAM_IERB_FUNC_CNT ARRAY_SIZE(ierb_offset) +/* cache related transaction attributes for PCIe functions */ +#define ECAM_IERB_MSICAR (ECAM_IERB_BASE + 0xa400) +#define ECAM_IERB_MSICAR_VALUE 0x30 + +/* offset of IERB config register per PCI function */ +static int ierb_offset[] = { + 0x0800, + 0x1800, + 0x2800, + 0x3800, + 0x4800, + 0x5800, + 0x6800, + ECAM_IERB_OFFSET_NA, + 0x0804, + 0x0808, + 0x1804, + 0x1808, +}; + +/* + * Use a custom function for LS1028A, for now this is the only SoC with IERB + * and we're currently considering reorganizing IERB for future SoCs. + */ +void set_ecam_icids(void) +{ + int i; + + out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE); + + for (i = 0; i < ECAM_IERB_FUNC_CNT; i++) { + if (ierb_offset[i] == ECAM_IERB_OFFSET_NA) + continue; + + out_le32(ECAM_IERB_BASE + ierb_offset[i], + FSL_ECAM_STREAM_ID_START + i); + } +} + +static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset, + const char *name, uint32_t idx, u32 val) +{ + val = cpu_to_be32(val); + return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name, + strlen(name), + idx * sizeof(val), &val, + sizeof(val)); +} + +static int fdt_getprop_len(void *fdt, int nodeoffset, const char *name) +{ + int len; + + if (fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), &len)) + return len; + + return 0; +} + +void fdt_fixup_ecam(void *blob) +{ + int off; + + off = fdt_node_offset_by_compatible(blob, 0, "pci-host-ecam-generic"); + if (off < 0) { + debug("ECAM node not found\n"); + return; + } + + if (fdt_getprop_len(blob, off, "msi-map") != 16 || + fdt_getprop_len(blob, off, "iommu-map") != 16) { + log_err("invalid msi/iommu-map propertly size in ECAM node\n"); + return; + } + + fdt_setprop_inplace_idx_u32(blob, off, "msi-map", 2, + FSL_ECAM_STREAM_ID_START); + fdt_setprop_inplace_idx_u32(blob, off, "msi-map", 3, + ECAM_IERB_FUNC_CNT); + + fdt_setprop_inplace_idx_u32(blob, off, "iommu-map", 2, + FSL_ECAM_STREAM_ID_START); + fdt_setprop_inplace_idx_u32(blob, off, "iommu-map", 3, + ECAM_IERB_FUNC_CNT); +} +#endif /* CONFIG_PCIE_ECAM_GENERIC */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 94ea99a349..01d362d183 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -42,6 +42,10 @@ * -the MC is responsible for allocating and setting up 'isolation context * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. * + * - ECAM (integrated PCI) + * - U-Boot applies the value here to HW and does DT fix-up for both + * 'iommu-map' and 'msi-map' + * * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: @@ -98,6 +102,10 @@ #define FSL_DPAA2_STREAM_ID_START 23 #define FSL_DPAA2_STREAM_ID_END 63 +/* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now */ +#define FSL_ECAM_STREAM_ID_START 32 +#define FSL_ECAM_STREAM_ID_END 63 + #define FSL_SEC_STREAM_ID 64 #define FSL_SEC_JR1_STREAM_ID 65 #define FSL_SEC_JR2_STREAM_ID 66 -- 2.17.1

2 1

[U-Boot] [PATCH v2] armv8: fsl-layerscape: LS1044A/1048A: enable Only 1x 10GE port
by Pramod Kumar 27 Nov '19

27 Nov '19

LS1044A, LS1048A are LS1088A personalities, which support only one 1x 10GE port. MAC1 and MAC2 are associated with 1G SGMII, 2.5G SGMII, and XFI. Disable MAC1 to have only one 1x 10GE port for LS1044A, LS1048A. Signed-off-by: Pramod Kumar <pramod.kumar_1(a)nxp.com> --- Changes for v2: - incorporated review comment's arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 27 ++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c index 8e8b45a..7b465e1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c @@ -1,10 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017-2019 NXP */ #include <common.h> #include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <asm/io.h> struct serdes_config { u8 ip_protocol; @@ -32,6 +34,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } }, {} }; + static struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ {0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } }, @@ -48,6 +51,19 @@ static struct serdes_config *serdes_cfg_tbl[] = { serdes2_cfg_tbl, }; +bool soc_has_mac1(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr, ver; + + svr = gur_in32(&gur->svr); + ver = SVR_SOC_VER(svr); + if (ver == SVR_LS1088A) + return true; + else + return false; +} + int serdes_get_number(int serdes, int cfg) { struct serdes_config *ptr; @@ -87,7 +103,14 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) return 0; - + /* + * LS1044A/1048A support only one XFI port + * Disable MAC1 for LS1044A/1048A + */ + if (!serdes && lane == 2) { + if (!soc_has_mac1()) + return 0; + } ptr = serdes_cfg_tbl[serdes]; while (ptr->ip_protocol) { if (ptr->ip_protocol == cfg) -- 2.7.4

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[U-Boot] [PATCH] warp7: Fix U-Boot corruption after saving the environment
by Fabio Estevam 27 Nov '19

27 Nov '19

U-Boot binary has grown in such a way that it goes beyond the reserved area for the environment variables. Running "saveenv" followed by a "reset" causes U-Boot to hang because of this overlap. Fix this problem by increasing the CONFIG_ENV_OFFSET size. Also, in order to prevent this same problem in the future, use CONFIG_BOARD_SIZE_LIMIT, which will detect the overlap in build-time. CONFIG_BOARD_SIZE_LIMIT does not accept math expressions, so declare CONFIG_ENV_OFFSET with its direct value instead. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- include/configs/warp7.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 73541fe176..d103567cf4 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -132,7 +132,18 @@ /* environment organization */ #define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (8 * SZ_64K) +/* Environment starts at 768k = 768 * 1024 = 786432 */ +#define CONFIG_ENV_OFFSET 786432 +/* + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot-dtb.imx offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 785408 #define CONFIG_SYS_FSL_USDHC_NUM 1 #define CONFIG_SYS_MMC_ENV_DEV 0 -- 2.17.1

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