November 2019 - U-Boot

[U-Boot] [v2 1/8] rtc: pcf8563: support driver model
by Biwen Li 29 Nov '19

29 Nov '19

This supports driver model to drop warning as follows: - drivers/rtc/pcf8563.c: In function rtc_read: drivers/rtc/pcf8563.c:111:10: warning: implicit declaration of function i2c_reg_read; did you mean dm_i2c_reg_read? [-Wimplicit-function-declaration drivers/rtc/pcf8563.c: In function rtc_write: drivers/rtc/pcf8563.c:116:2: warning: implicit declaration of function i2c_reg_write; did you mean dm_i2c_reg_write? [-Wimplicit-function-declaration] Signed-off-by: Biwen Li <biwen.li(a)nxp.com> --- Changes in v2: - none drivers/rtc/pcf8563.c | 107 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c index a839d6cc98..44204e133e 100644 --- a/drivers/rtc/pcf8563.c +++ b/drivers/rtc/pcf8563.c @@ -12,9 +12,11 @@ #include <common.h> #include <command.h> +#include <dm.h> #include <rtc.h> #include <i2c.h> +#if !CONFIG_IS_ENABLED(DM_RTC) static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); @@ -115,3 +117,108 @@ static void rtc_write (uchar reg, uchar val) { i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } +#else +static int pcf8563_rtc_get(struct udevice *dev, struct rtc_time *tmp) +{ + int rel = 0; + uchar sec, min, hour, mday, wday, mon_cent, year; + + sec = dm_i2c_reg_read(dev, 0x02); + min = dm_i2c_reg_read(dev, 0x03); + hour = dm_i2c_reg_read(dev, 0x04); + mday = dm_i2c_reg_read(dev, 0x05); + wday = dm_i2c_reg_read(dev, 0x06); + mon_cent = dm_i2c_reg_read(dev, 0x07); + year = dm_i2c_reg_read(dev, 0x08); + + debug ("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon_cent, mday, wday, + hour, min, sec); + debug ("Alarms: wday: %02x day: %02x hour: %02x min: %02x\n", + dm_i2c_reg_read(dev, 0x0C), + dm_i2c_reg_read(dev, 0x0B), + dm_i2c_reg_read(dev, 0x0A), + dm_i2c_reg_read(dev, 0x09)); + + if (sec & 0x80) { + puts ("### Warning: RTC Low Voltage - date/time not reliable\n"); + rel = -1; + } + + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon_cent & 0x1F); + tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 1900 : 2000); + tmp->tm_wday = bcd2bin (wday & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst = 0; + + debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return rel; +} + +static int pcf8563_rtc_set(struct udevice *dev, const struct rtc_time *tmp) +{ + uchar century; + + debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + dm_i2c_reg_write(dev, 0x08, bin2bcd(tmp->tm_year % 100)); + + century = (tmp->tm_year >= 2000) ? 0 : 0x80; + dm_i2c_reg_write(dev, 0x07, bin2bcd(tmp->tm_mon) | century); + + dm_i2c_reg_write(dev, 0x06, bin2bcd(tmp->tm_wday)); + dm_i2c_reg_write(dev, 0x05, bin2bcd(tmp->tm_mday)); + dm_i2c_reg_write(dev, 0x04, bin2bcd(tmp->tm_hour)); + dm_i2c_reg_write(dev, 0x03, bin2bcd(tmp->tm_min)); + dm_i2c_reg_write(dev, 0x02, bin2bcd(tmp->tm_sec)); + + return 0; +} + +static int pcf8563_rtc_reset(struct udevice *dev) +{ + /* clear all control & status registers */ + dm_i2c_reg_write(dev, 0x00, 0x00); + dm_i2c_reg_write(dev, 0x01, 0x00); + dm_i2c_reg_write(dev, 0x0D, 0x00); + + /* clear Voltage Low bit */ + dm_i2c_reg_write(dev, 0x02, dm_i2c_reg_read (dev, 0x02) & 0x7F); + + /* reset all alarms */ + dm_i2c_reg_write(dev, 0x09, 0x00); + dm_i2c_reg_write(dev, 0x0A, 0x00); + dm_i2c_reg_write(dev, 0x0B, 0x00); + dm_i2c_reg_write(dev, 0x0C, 0x00); + + return 0; +} + +static const struct rtc_ops pcf8563_rtc_ops = { + .get = pcf8563_rtc_get, + .set = pcf8563_rtc_set, + .reset = pcf8563_rtc_reset, +}; + +static const struct udevice_id pcf8563_rtc_ids[] = { + { .compatible = "nxp,pcf8563" }, + { } +}; + +U_BOOT_DRIVER(rtc_pcf8563) = { + .name = "rtc-pcf8563", + .id = UCLASS_RTC, + .of_match = pcf8563_rtc_ids, + .ops = &pcf8563_rtc_ops, +}; +#endif -- 2.17.1

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[U-Boot] [PATCH 0/4] ARM: imx6: DHCOM i.MX6 PDK: Fixing reset
by Claudius Heine 29 Nov '19

29 Nov '19

Hi, currently the reset on the DHCOM i.MX6 board is brocken in u-boot. This patchset fixes that by integrating the sysreset and watchdog dm driver. regards, Claudius Claudius Heine (4): ARM: dts: dh-imx6: add wdt-reboot node for sysreset driver ARM: imx6: DHCOM i.MX6 PDK: Enable sysreset driver ARM: imx6: DHCOM i.MX6 PDK: Enable wdt command ARM: imx6: DHCOM i.MX6 PDK: Use HW_WATCHDOG in SPL arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi | 5 +++++ configs/dh_imx6_defconfig | 3 +++ include/configs/dh_imx6.h | 5 +++++ 3 files changed, 13 insertions(+) -- 2.21.0

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[U-Boot] [RFC PATCH] ARM: at91: Print CPU serial number in cpuinfo
by Alexander Dahl 29 Nov '19

29 Nov '19

The SAMA5D2 and SAMA5D4 series SoCs have a 64-bit Serial Number (unique ID) burned in, which is displayed with 'print_cpuinfo()' now (in the same format the SAM-BA applet prints it). Example output: CPU: SAMA5D27 1G bits DDR2 SDRAM Serial number 0: 0x4630394b 1: 0x190d2750 Crystal frequency: 24 MHz CPU clock : 492 MHz Master clock : 164 MHz Signed-off-by: Alexander Dahl <ada(a)thorsis.com> --- I looked over lots of other 'print_cpuinfo()' implementations for different SoCs and found none printing a unique ID at all. Is there another place for this? Is it just few SoCs have such a serial number at all? Or is it not desired to print those along with the other CPU info? Greets Alex --- arch/arm/mach-at91/armv7/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 5da067cda1..6d50e1aea4 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -13,6 +13,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/at91_pit.h> #include <asm/arch/at91_gpbr.h> +#include <asm/arch/at91_sfr.h> #include <asm/arch/clk.h> #ifndef CONFIG_SYS_AT91_MAIN_CLOCK @@ -42,9 +43,16 @@ void arch_preboot_os(void) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; char buf[32]; printf("CPU: %s\n", get_cpu_name()); + +#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D4) + printf("Serial number 0: 0x%08x\n", sfr->sn0); + printf(" 1: 0x%08x\n", sfr->sn1); +#endif + printf("Crystal frequency: %8s MHz\n", strmhz(buf, get_main_clk_rate())); printf("CPU clock : %8s MHz\n", -- 2.20.1

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[U-Boot] [PATCH] spl: Allow cache drivers to be used in SPL
by Ley Foon Tan 29 Nov '19

29 Nov '19

Add an option for building cache drivers in SPL. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> --- common/spl/Kconfig | 5 +++++ drivers/Makefile | 1 + drivers/cache/Makefile | 2 +- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index c661809923..6e095c33e1 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -714,6 +714,11 @@ config SPL_UBI README.ubispl for more info. if SPL_DM +config SPL_CACHE + bool "Support cache drivers in SPL" + help + Enable support for cache drivers in SPL. + config SPL_DM_SPI bool "Support SPI DM drivers in SPL" help diff --git a/drivers/Makefile b/drivers/Makefile index 0befeddfcb..0e42d006b9 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -31,6 +31,7 @@ ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/ +obj-$(CONFIG_SPL_CACHE) += cache/ obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/ obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index 4a6458c602..c1f766cfca 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -1,5 +1,5 @@ -obj-$(CONFIG_CACHE) += cache-uclass.o +obj-$(CONFIG_$(SPL_)CACHE) += cache-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_cache.o obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o -- 2.19.0

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[U-Boot] [PATCH] blk: Better guard some of our object files for linking
by Tom Rini 28 Nov '19

28 Nov '19

When we do not have CONFIG_BLK (or SPL/TPL) enabled there are very few cases where we need the blk_legacy code linked in. To catch these, build when we have CONFIG_PARTITIONS set. In addition, we only need cmd/blk_common.o to be linked in when we have CONFIG_HAVE_BLOCK_DEVICE set, so make use of that directly. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- cmd/Makefile | 2 +- cmd/blk_common.c | 2 -- drivers/block/Makefile | 2 +- 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/cmd/Makefile b/cmd/Makefile index 2d723ea0f07d..f823d16755e6 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -15,7 +15,7 @@ obj-$(CONFIG_CMD_AES) += aes.o obj-$(CONFIG_CMD_AB_SELECT) += ab_select.o obj-$(CONFIG_CMD_ADC) += adc.o obj-$(CONFIG_CMD_ARMFLASH) += armflash.o -obj-y += blk_common.o +obj-$(CONFIG_HAVE_BLOCK_DEVICE) += blk_common.o obj-$(CONFIG_CMD_SOURCE) += source.o obj-$(CONFIG_CMD_BCB) += bcb.o obj-$(CONFIG_CMD_BDI) += bdinfo.o diff --git a/cmd/blk_common.c b/cmd/blk_common.c index cee25a0d4100..c5514cf8f8e8 100644 --- a/cmd/blk_common.c +++ b/cmd/blk_common.c @@ -11,7 +11,6 @@ #include <common.h> #include <blk.h> -#ifdef CONFIG_HAVE_BLOCK_DEVICE int blk_common_cmd(int argc, char * const argv[], enum if_type if_type, int *cur_devnump) { @@ -96,4 +95,3 @@ int blk_common_cmd(int argc, char * const argv[], enum if_type if_type, } } } -#endif diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 3feb0aa997df..8443625091b7 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_$(SPL_)BLK) += blk-uclass.o ifndef CONFIG_$(SPL_)BLK -obj-y += blk_legacy.o +obj-$(CONFIG_PARTITIONS) += blk_legacy.o endif ifndef CONFIG_SPL_BUILD -- 2.17.1

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Re: [U-Boot] [PATCH v1 2/2] board: colibri_imx7: reserve DDR memory for Cortex-M4
by Igor Opaniuk 28 Nov '19

28 Nov '19

Hi Stefano, On Mon, Oct 14, 2019 at 3:40 PM <sbabic(a)denx.de> wrote: > > > From: Igor Opaniuk <igor.opaniuk(a)toradex.com> > > i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for > > the rpmsg communication. Both use cases need a fixed location of > > memory reserved. For the rpmsg use case the reserved area needs > > to be in sync with the kernel's hardcoded vring descriptor location. > > Use the linux,usable-memory property to carve out 1MB of memory > > in case the M4 core is running. Also make sure that the i.MX 7 > > specific rpmsg driver does not get loaded in case we do not carve > > out memory. > > Signed-off-by: Stefan Agner <stefan.agner(a)toradex.com> > > Signed-off-by: Igor Opaniuk <igor.opaniuk(a)toradex.com> > > Signed-off-by: Igor Opaniuk <igor.opaniuk(a)gmail.com> > > Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov(a)toradex.com> > > Applied to u-boot-imx, master, thanks ! Unfortunately I can't find this commit neither in u-boot-imx/next neither in u-boot-imx/master. > > Best regards, > Stefano Babic > > -- > ===================================================================== > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de > ===================================================================== > -- Best regards - Freundliche Grüsse - Meilleures salutations Igor Opaniuk mailto: igor.opaniuk(a)gmail.com skype: igor.opanyuk +380 (93) 836 40 67 http://ua.linkedin.com/in/iopaniuk

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[U-Boot] [U-boot] regression: bootaux doesn't work with DCACHE enabled
by Igor Opaniuk 28 Nov '19

28 Nov '19

Hi all, U-boot imx-specific bootaux command doesn't work properly with the old legacy binary format if the DCACHE is enabled (I've tested only executing from OCRAM) in the mainline U-boot. Interesting thing is that invocation of `dcache flush` before bootaux doesn't help, but only full disabling it with `dcache off`. To reproduce: > tftpboot ${loadaddr} ${board_name}/hello_world.bin > cp.b ${loadaddr} 0x7F8000 $filesize > bootaux 0x7F8000 However this works: > tftpboot ${loadaddr} ${board_name}/hello_world.bin > cp.b ${loadaddr} 0x7F8000 $filesize > dcache off > bootaux 0x7F8000 Any ideas and suggestions? Thanks -- Best regards - Freundliche Grüsse - Meilleures salutations Igor Opaniuk mailto: igor.opaniuk(a)gmail.com skype: igor.opanyuk +380 (93) 836 40 67 http://ua.linkedin.com/in/iopaniuk

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[U-Boot] [PATCH 1/2] rockchip: px30: Fixup PMUGRF registers layout order
by Paul Kocialkowski 28 Nov '19

28 Nov '19

According to the PX30 TRM, the iomux registers come first, before the pull and strength control registers. Signed-off-by: Paul Kocialkowski <paul.kocialkowski(a)bootlin.com> --- arch/arm/include/asm/arch-rockchip/grf_px30.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_px30.h b/arch/arm/include/asm/arch-rockchip/grf_px30.h index c167bb42fac9..3d2a8770322e 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_px30.h +++ b/arch/arm/include/asm/arch-rockchip/grf_px30.h @@ -112,18 +112,18 @@ struct px30_grf { check_member(px30_grf, mac_con1, 0x904); struct px30_pmugrf { - unsigned int gpio0a_e; - unsigned int gpio0b_e; - unsigned int gpio0c_e; - unsigned int gpio0d_e; - unsigned int gpio0a_p; - unsigned int gpio0b_p; - unsigned int gpio0c_p; - unsigned int gpio0d_p; unsigned int gpio0al_iomux; unsigned int gpio0bl_iomux; unsigned int gpio0cl_iomux; unsigned int gpio0dl_iomux; + unsigned int gpio0a_p; + unsigned int gpio0b_p; + unsigned int gpio0c_p; + unsigned int gpio0d_p; + unsigned int gpio0a_e; + unsigned int gpio0b_e; + unsigned int gpio0c_e; + unsigned int gpio0d_e; unsigned int gpio0l_sr; unsigned int gpio0h_sr; unsigned int gpio0l_smt; -- 2.24.0

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[U-Boot] GPT overlap on i.MX6
by Jagan Teki 28 Nov '19

28 Nov '19

Hi, I have created GPT table start from 8MB for kernel, roots etc. something like Part Start LBA End LBA Name Attributes Type GUID Partition GUID 1 0x00004000 0x00023fff "boota" attrs: 0x0000000000000004 type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 guid: c12a7328-f81f-11d2-ba4b-00a0c93ec93b 2 0x00024000 0x00043fff "bootb" attrs: 0x0000000000000004 type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 guid: 21686148-6449-6e6f-744e-656564454649 3 0x00044000 0x00243fff "rootfsa" attrs: 0x0000000000000000 type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 guid: b921b045-1df0-41c3-af44-4c6f280d3fae 4 0x00244000 0x00443fff "rootfsb" attrs: 0x0000000000000000 type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 guid: 8da63339-0007-60c0-c436-083ac8230908 5 0x00444000 0x0070bfde "data" attrs: 0x0000000000000000 type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 guid: 4f72ab70-69be-5948-81ff-4fc3daf24faa I have not included SPL, U-Boot to the partition list since it start from 0x400 in i.MX6. So I'm writing SPL separately using fastboot(with offset) or ums. But by doing this, the partition header seems overlapped so the output looks GUID Partition Table Entry Array CRC is wrong: 0x6a1aba0a != 0x8e4fd548 find_valid_gpt: *** ERROR: Invalid GPT *** find_valid_gpt: *** Using Backup GPT *** Part Start LBA End LBA Name Attributes Type GUID Partition GUID 1 0x00004000 0x00023fff "boota" attrs: 0x0000000000000004 type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 guid: c12a7328-f81f-11d2-ba4b-00a0c93ec93b 2 0x00024000 0x00043fff "bootb" attrs: 0x0000000000000004 type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 guid: 21686148-6449-6e6f-744e-656564454649 3 0x00044000 0x00243fff "rootfsa" attrs: 0x0000000000000000 type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 guid: b921b045-1df0-41c3-af44-4c6f280d3fae 4 0x00244000 0x00443fff "rootfsb" attrs: 0x0000000000000000 type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 guid: 8da63339-0007-60c0-c436-083ac8230908 5 0x00444000 0x0070bfde "data" attrs: 0x0000000000000000 type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 guid: 4f72ab70-69be-5948-81ff-4fc3daf24faa So, what I understand is If I create the GPT first and then write the SPL, the SPL writing process will destroy the GPT Table and if I write SPL first and then create GPT, the GPT creation process will destroy the SPL. Is there any way to fix this? I remember we can prevent this overlap by preserving GPT Table som other or boot partition instead of having them at the beginning by default. Any inputs? Jagan.

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[U-Boot] Using sspi for hardware detection?
by Romain Naour 28 Nov '19

28 Nov '19

Hello, I'm working on a modular socfpga based system with several optional boards. Each optional board contain a board ID that can be read through a SPI bus. Since we want just read the board ID, we used manually the sspi command, something like: => sspi 1:1.0 8 0 42 But it seems that the sspi command can't be used in a uboot script. sspi seems only used to manually test spi drivers. If we compare with i2c command, we have a i2c read to memory: i2c read chip address[.0, .1, .2] length memaddress - read to memory Why there is no such feature for spi ? Is there an interest to evolve the sspi command to add a read to memory? sspi <bus id>: <chip select>.<mode> <bit length> <data> <memaddress> By looking at existing code, it seems that hardware detection in uboot is handled by architecture/board specific code to set custom environment variable like "fpgatype" [1] or "unit_ident" "unit_serial" [2] (misc_init_r). What do you recommend? Implement a custom misc_init_r() for hardware detection? [1] https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/mach-socfpga/misc… [2] https://gitlab.denx.de/u-boot/u-boot/blob/master/board/softing/vining_fpga/… Best regards, Romain

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