November 2019 - U-Boot

[U-Boot] [PATCH] ARM: socfpga: Fix FPGA bitstream loading code
by Marek Vasut 01 Dec '19

01 Dec '19

According to SoCFPGA Cyclone V datasheet rev.2018.01.26 page 175 (Chapter 5, FPGA Manager, data register) and Arria10 datasheet rev.2017.07.22 page 211 (Chapter 5.4.1.2, FPGA Manager, img_data_w register), the FPGA data register must be written with writes with non-incrementing address. The current code increments the address in 32-byte bursts. Fix the code so it does not increment the address and writes the register repeatedly instead. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Tien Fong Chee <tien.fong.chee(a)intel.com> --- drivers/fpga/socfpga.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index 685957626b..6ecea771ce 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -55,8 +55,7 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size) " cmp %2, #0\n" " beq 2f\n" "1: ldmia %0!, {r0-r7}\n" - " stmia %1!, {r0-r7}\n" - " sub %1, #32\n" + " stmia %1, {r0-r7}\n" " subs %2, #1\n" " bne 1b\n" "2: cmp %3, #0\n" -- 2.20.1

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[U-Boot] [PATCH 1/4] doc: rockchip: Update build instruction for rk3308
by Andy Yan 01 Dec '19

01 Dec '19

After commit d8765e2422cd ("Enable building of u-boot.itb on Rockchip platform"), u-boot.itb will automatically generated by "make all" command, manually command "make u-boot.itb" is no longer needed. Signed-off-by: Andy Yan <andy.yan(a)rock-chips.com> --- doc/README.rockchip | 1 - 1 file changed, 1 deletion(-) diff --git a/doc/README.rockchip b/doc/README.rockchip index 67c14006a3..dae4ebc8e4 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -108,7 +108,6 @@ For example: => export BL31=/path/to/rkbin/bin/rk33/rk3308_bl31_v2.22.elf => make roc-rk3308-cc_defconfig => make CROSS_COMPILE=aarch64-linux-gnu- all - => make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb => ./tools/mkimage -n rk3308 -T rksd -d /path/to/rkbin/bin/rk33/rk3308_ddr_589MHz_uart2_m0_v1.26.bin idbloader.img => cat spl/u-boot-spl.bin >> idbloader.img -- 2.17.1

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[U-Boot] [PATCH v2 1/3] rockchip: px30: Fixup PMUGRF registers layout order
by Paul Kocialkowski 01 Dec '19

01 Dec '19

According to the PX30 TRM, the iomux registers come first, before the pull and strength control registers. Signed-off-by: Paul Kocialkowski <paul.kocialkowski(a)bootlin.com> Reviewed-by: Kever Yang <kever.yang(a)rock-chips.com> Reviewed-by: Heiko Stuebner <heiko.stuebner(a)theobroma-systems.com> --- arch/arm/include/asm/arch-rockchip/grf_px30.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_px30.h b/arch/arm/include/asm/arch-rockchip/grf_px30.h index c167bb42fac9..3d2a8770322e 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_px30.h +++ b/arch/arm/include/asm/arch-rockchip/grf_px30.h @@ -112,18 +112,18 @@ struct px30_grf { check_member(px30_grf, mac_con1, 0x904); struct px30_pmugrf { - unsigned int gpio0a_e; - unsigned int gpio0b_e; - unsigned int gpio0c_e; - unsigned int gpio0d_e; - unsigned int gpio0a_p; - unsigned int gpio0b_p; - unsigned int gpio0c_p; - unsigned int gpio0d_p; unsigned int gpio0al_iomux; unsigned int gpio0bl_iomux; unsigned int gpio0cl_iomux; unsigned int gpio0dl_iomux; + unsigned int gpio0a_p; + unsigned int gpio0b_p; + unsigned int gpio0c_p; + unsigned int gpio0d_p; + unsigned int gpio0a_e; + unsigned int gpio0b_e; + unsigned int gpio0c_e; + unsigned int gpio0d_e; unsigned int gpio0l_sr; unsigned int gpio0h_sr; unsigned int gpio0l_smt; -- 2.24.0

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[U-Boot] [PATCH 1/2] rockchip: misc: don't fail if eth_addr already set
by Heiko Stuebner 01 Dec '19

01 Dec '19

From: Heiko Stuebner <heiko.stuebner(a)theobroma-systems.com> rockchip_setup_macaddr() runs from an initcall, so returning an error code will make that initcall fail thus breaking the boot process. And if an ethernet address is already set this is definitly not a cause for that, so just return success in that case. Fixes: 04825384999f ("rockchip: rk3399: derive ethaddr from cpuid"); Signed-off-by: Heiko Stuebner <heiko.stuebner(a)theobroma-systems.com> --- arch/arm/mach-rockchip/misc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c index bed4317f7e..d0fb3d07a7 100644 --- a/arch/arm/mach-rockchip/misc.c +++ b/arch/arm/mach-rockchip/misc.c @@ -29,7 +29,7 @@ int rockchip_setup_macaddr(void) /* Only generate a MAC address, if none is set in the environment */ if (env_get("ethaddr")) - return -1; + return 0; if (!cpuid) { debug("%s: could not retrieve 'cpuid#'\n", __func__); -- 2.24.0

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[U-Boot] [PATCH 1/3] ARM: rmobile: Convert H2 Lager to DM_SPI{, _FLASH}
by Marek Vasut 30 Nov '19

30 Nov '19

Enable DM_SPI and DM_SPI_FLASH in U-Boot on H2 Lager. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- configs/lager_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 1be6df22e9..6dff5234c6 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -40,7 +40,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_SDRAM=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -71,7 +70,7 @@ CONFIG_SH_MMCIF=y CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_MTD_DEVICE=y -CONFIG_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y @@ -89,6 +88,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_SH_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y -- 2.24.0.393.g34dc348eaf

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[U-Boot] [PATCH v2 1/2] pci: layerscape: move PCIE related CONFIG to PCI Kconfig
by Pankaj Bansal 30 Nov '19

30 Nov '19

move the PCIE related config from arch Kconfig to PCI Kconfig. As the PCI_LAYERSCAPE driver is being used in platform other than fsl-layerscale platforms like ls102xa. Signed-off-by: Pankaj Bansal <pankaj.bansal(a)nxp.com> --- Notes: V2: - new patch to fix the issues with patch [2/2] arch/arm/cpu/armv7/ls102xa/Kconfig | 8 -------- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 14 -------------- drivers/pci/Kconfig | 15 +++++++++++++++ 3 files changed, 15 insertions(+), 22 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index b9511da3f3..57d7fd9e55 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -27,14 +27,6 @@ config ARCH_LS1021A menu "LS102xA architecture" depends on ARCH_LS1021A -config FSL_PCIE_COMPAT - string "PCIe compatible of Kernel DT" - depends on PCIE_LAYERSCAPE - default "fsl,ls1021a-pcie" if ARCH_LS1021A - help - This compatible is used to find pci controller node in Kernel DT - to complete fixup. - config LS1_DEEP_SLEEP bool "Deep sleep" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f1578b10bc..efe7a7f37d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -252,20 +252,6 @@ menu "Layerscape architecture" config FSL_LAYERSCAPE bool -config FSL_PCIE_COMPAT - string "PCIe compatible of Kernel DT" - depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4 - default "fsl,ls1012a-pcie" if ARCH_LS1012A - default "fsl,ls1028a-pcie" if ARCH_LS1028A - default "fsl,ls1043a-pcie" if ARCH_LS1043A - default "fsl,ls1046a-pcie" if ARCH_LS1046A - default "fsl,ls2080a-pcie" if ARCH_LS2080A - default "fsl,ls1088a-pcie" if ARCH_LS1088A - default "fsl,lx2160a-pcie" if ARCH_LX2160A - help - This compatible is used to find pci controller node in Kernel DT - to complete fixup. - config HAS_FEATURE_GIC64K_ALIGN bool default y if ARCH_LS1043A diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 13603b9d57..3856f7d755 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -143,6 +143,21 @@ config PCIE_LAYERSCAPE_GEN4 several PCIe controllers. The PCIe controller can work in RC or EP mode according to RCW[HOST_AGT_PEX] setting. +config FSL_PCIE_COMPAT + string "PCIe compatible of Kernel DT" + depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4 + default "fsl,ls1012a-pcie" if ARCH_LS1012A + default "fsl,ls1028a-pcie" if ARCH_LS1028A + default "fsl,ls1043a-pcie" if ARCH_LS1043A + default "fsl,ls1046a-pcie" if ARCH_LS1046A + default "fsl,ls2080a-pcie" if ARCH_LS2080A + default "fsl,ls1088a-pcie" if ARCH_LS1088A + default "fsl,lx2160a-pcie" if ARCH_LX2160A + default "fsl,ls1021a-pcie" if ARCH_LS1021A + help + This compatible is used to find pci controller node in Kernel DT + to complete fixup. + config PCIE_INTEL_FPGA bool "Intel FPGA PCIe support" depends on DM_PCI -- 2.17.1

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[U-Boot] [PATCH] net: tftp: Fix too small block size
by Andre Przywara 30 Nov '19

30 Nov '19

Commit b618b3707633 ("net: Convert CONFIG_TFTP_BLOCKSIZE to Kconfig") accidentally set the default *option* TFTP block size to 512 bytes, even though the comment in the code says that this is a terrible choice. Most boards didn't define the symbol before, so they got the default block size of 1468 bytes before, but now use 512 bytes, which is also the fallback. This leads to both abysmal performance and a lot of hashes printed on the screen (one character for every 5K), which is both annoying and slow over serial links. Set the default block size in Kconfig back to the value it had before. This improves TFTP performance from 2.8 MB/s to 6.9 MB/s on a Pine64. Fixes: b618b3707633 ("net: Convert CONFIG_TFTP_BLOCKSIZE to Kconfig") Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- net/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/Kconfig b/net/Kconfig index 68cecf75a2..a07f6746c5 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -31,7 +31,7 @@ config IP_DEFRAG config TFTP_BLOCKSIZE int "TFTP block size" - default 512 + default 1468 help Default TFTP block size. -- 2.14.5

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[U-Boot] [PATCH] net: ftgmac100: align RX/TX descriptors on ARCH_DMA_MINALIGN
by Cédric Le Goater 30 Nov '19

30 Nov '19

Fixes: e766849713ff ("net: ftgmac100: convert the RX/TX descriptor arrays") Signed-off-by: Cédric Le Goater <clg(a)kaod.org> --- drivers/net/ftgmac100.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 92c38a81bd35..c14647af7844 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -71,8 +71,8 @@ enum ftgmac100_model { struct ftgmac100_data { struct ftgmac100 *iobase; - struct ftgmac100_txdes txdes[PKTBUFSTX]; - struct ftgmac100_rxdes rxdes[PKTBUFSRX]; + struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN); + struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN); int tx_index; int rx_index; @@ -309,7 +309,7 @@ static int ftgmac100_start(struct udevice *dev) } priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask; - start = (ulong)&priv->txdes[0]; + start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1); end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); @@ -319,7 +319,7 @@ static int ftgmac100_start(struct udevice *dev) } priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask; - start = (ulong)&priv->rxdes[0]; + start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1); end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); @@ -369,7 +369,7 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) { struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index]; - ulong des_start = (ulong)curr_des; + ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1); ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); @@ -391,7 +391,7 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index]; unsigned short rxlen; - ulong des_start = (ulong)curr_des; + ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1); ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); ulong data_start = curr_des->rxdes3; @@ -426,7 +426,7 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) static u32 ftgmac100_read_txdesc(const void *desc) { const struct ftgmac100_txdes *txdes = desc; - ulong des_start = (ulong)txdes; + ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1); ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN); invalidate_dcache_range(des_start, des_end); @@ -444,7 +444,7 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) struct ftgmac100_data *priv = dev_get_priv(dev); struct ftgmac100 *ftgmac100 = priv->iobase; struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; - ulong des_start = (ulong)curr_des; + ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1); ulong des_end = des_start + roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); ulong data_start; -- 2.21.0

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[U-Boot] [PATCH] net: phy: micrel: make sure the factory test bit is cleared
by Eugen.Hristev＠microchip.com 30 Nov '19

30 Nov '19

From: Nicolas Ferre <nicolas.ferre(a)microchip.com> The KSZ8081 PHY has a factory test mode which is set at the de-assertion of the reset line based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a pull-down is missing, or if the pin has a pull-up, the factory test mode should be cleared by manually writing a 0 (according to the datasheet). Create another ksz8081_config function to handle this case. Suggested-by: Antoine Tenart <antoine.tenart(a)bootlin.com> Signed-off-by: Nicolas Ferre <nicolas.ferre(a)microchip.com> --- drivers/net/phy/micrel_ksz8xxx.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/micrel_ksz8xxx.c b/drivers/net/phy/micrel_ksz8xxx.c index daa57ce..5340ea0 100644 --- a/drivers/net/phy/micrel_ksz8xxx.c +++ b/drivers/net/phy/micrel_ksz8xxx.c @@ -24,6 +24,7 @@ static struct phy_driver KSZ804_driver = { }; #define MII_KSZPHY_OMSO 0x16 +#define KSZPHY_OMSO_FACTORY_TEST (1 << 15) #define KSZPHY_OMSO_B_CAST_OFF (1 << 9) static int ksz_genconfig_bcastoff(struct phy_device *phydev) @@ -80,12 +81,30 @@ static struct phy_driver KSZ8051_driver = { .shutdown = &genphy_shutdown, }; +static int ksz8081_config(struct phy_device *phydev) +{ + int ret; + + ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO); + if (ret < 0) + return ret; + + ret &= ~KSZPHY_OMSO_FACTORY_TEST; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO, + ret | KSZPHY_OMSO_B_CAST_OFF); + if (ret < 0) + return ret; + + return genphy_config(phydev); +} + static struct phy_driver KSZ8081_driver = { .name = "Micrel KSZ8081", .uid = 0x221560, .mask = 0xfffff0, .features = PHY_BASIC_FEATURES, - .config = &ksz_genconfig_bcastoff, + .config = &ksz8081_config, .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; -- 2.7.4

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[U-Boot] [PATCH] net: phy: aquantia: wait for phy init sequence to finish
by Florin Chiculita 30 Nov '19

30 Nov '19

Aquantia quad-phys may take longer to initialize. This commit adds a polling mechanism for a global alarm bit that tells if phy init sequence is completed. Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita(a)nxp.com> --- drivers/net/phy/aquantia.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 465ec2d..ae3112c 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -37,6 +37,9 @@ #define GLOBAL_FAULT 0xc850 #define GLOBAL_RSTATUS_1 0xc885 +#define GLOBAL_ALARM_1 0xcc00 +#define SYSTEM_READY_BIT 0x40 + #define GLOBAL_STANDARD_CONTROL 0x0 #define SOFT_RESET BIT(15) #define LOW_POWER BIT(11) @@ -258,6 +261,17 @@ int aquantia_config(struct phy_device *phydev) { u32 val, id, rstatus, fault; u32 reg_val1 = 0; + int num_retries = 5; + + /* check if the system is out of reset and init sequence completed. + * chip-wide reset for gen1 quad phys takes longer + */ + while (--num_retries) { + rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1); + if (rstatus & SYSTEM_READY_BIT) + break; + mdelay(10); + } id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID); rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1); -- 1.9.3

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