June 2018 - U-Boot

[U-Boot] [PATCH u-boot 0/5] Amlogic Meson GX Updates for v2018.07
by Neil Armstrong 19 Jun '18

19 Jun '18

This patchset : - fixes meson-saradc build - adds the meson clock driver from Beniamino with it's consent - switches to the clock driver for Ethernet and I2C - Enables boot from USB if config is enabled - finally enables USB, Regulator & ADC drivers for selected boards Beniamino Galvani (2): clk: add Amlogic meson clock driver meson: use the clock driver Neil Armstrong (3): adc: meson-saradc: fix regmap_init_mem call config: meson-gx-common: Enable USB boot configs: Update Meson GX configs arch/arm/include/asm/arch-meson/clock.h | 117 +++++++++ arch/arm/include/asm/arch-meson/gx.h | 10 - arch/arm/mach-meson/Kconfig | 2 + arch/arm/mach-meson/eth.c | 3 +- board/amlogic/libretech-cc/libretech-cc.c | 4 - board/amlogic/odroid-c2/odroid-c2.c | 3 - configs/khadas-vim_defconfig | 14 ++ configs/libretech-cc_defconfig | 17 ++ configs/odroid-c2_defconfig | 4 + configs/p212_defconfig | 14 ++ drivers/adc/meson-saradc.c | 2 +- drivers/clk/Makefile | 1 + drivers/clk/clk_meson.c | 393 ++++++++++++++++++++++++++++++ drivers/clk/clk_meson.h | 47 ++++ drivers/i2c/meson_i2c.c | 20 +- include/configs/meson-gx-common.h | 7 + 16 files changed, 635 insertions(+), 23 deletions(-) create mode 100644 arch/arm/include/asm/arch-meson/clock.h create mode 100644 drivers/clk/clk_meson.c create mode 100644 drivers/clk/clk_meson.h -- 2.7.4

2 10

[U-Boot] [PATCH 1/2] configs: db410c: Set eMMC env partition to BOOT2
by Ramon Fried 19 Jun '18

19 Jun '18

BOOT2 partition is empty and free for using to store the environment. Use that instead of the default user partition. Signed-off-by: Ramon Fried <ramon.fried(a)gmail.com> --- include/configs/dragonboard410c.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 86fa735470..46a7179f1b 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -94,6 +94,7 @@ REFLASH(dragonboard/u-boot.img, 8)\ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 /* mmc0 = emmc, mmc1 = sd */ +#define CONFIG_SYS_MMC_ENV_PART 2 /* Set env partition to BOOT2 partition */ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) -- 2.17.1

2 3

[U-Boot] [PATCH] common: Fix cpu nr type which is always unsigned type
by Michal Simek 19 Jun '18

19 Jun '18

cpu_cmd() is reading cpu number via simple_strtoul() which is always unsigned type. Platform code implementations are not expecting that nr can be negative and there is not checking in the code for that too. This patch is using u32 type for cpu number to make sure that platform code get proper value range. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 8 ++++---- arch/arm/cpu/armv8/zynqmp/mp.c | 8 ++++---- arch/arm/mach-imx/mx6/mp.c | 8 ++++---- arch/powerpc/cpu/mpc85xx/mp.c | 10 +++++----- arch/powerpc/cpu/mpc86xx/mp.c | 8 ++++---- include/common.h | 8 ++++---- 6 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index dd89d0a83f89..7627fd13e7d8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -191,14 +191,14 @@ int is_core_online(u64 cpu_id) return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1; } -int cpu_reset(int nr) +int cpu_reset(u32 nr) { puts("Feature is not implemented.\n"); return 0; } -int cpu_disable(int nr) +int cpu_disable(u32 nr) { puts("Feature is not implemented.\n"); @@ -231,7 +231,7 @@ static int core_to_pos(int nr) return i; } -int cpu_status(int nr) +int cpu_status(u32 nr) { u64 *table; int pos; @@ -257,7 +257,7 @@ int cpu_status(int nr) return 0; } -int cpu_release(int nr, int argc, char * const argv[]) +int cpu_release(u32 nr, int argc, char * const argv[]) { u64 boot_addr; u64 *table = (u64 *)get_spin_tbl_addr(); diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c index 7e270a7dc232..2a71870ae7bc 100644 --- a/arch/arm/cpu/armv8/zynqmp/mp.c +++ b/arch/arm/cpu/armv8/zynqmp/mp.c @@ -45,7 +45,7 @@ int is_core_valid(unsigned int core) return 0; } -int cpu_reset(int nr) +int cpu_reset(u32 nr) { puts("Feature is not implemented.\n"); return 0; @@ -131,7 +131,7 @@ static void enable_clock_r5(void) udelay(0x500); } -int cpu_disable(int nr) +int cpu_disable(u32 nr) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { u32 val = readl(&crfapb_base->rst_fpd_apu); @@ -144,7 +144,7 @@ int cpu_disable(int nr) return 0; } -int cpu_status(int nr) +int cpu_status(u32 nr) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8); @@ -220,7 +220,7 @@ void initialize_tcm(bool mode) } } -int cpu_release(int nr, int argc, char * const argv[]) +int cpu_release(u32 nr, int argc, char * const argv[]) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { u64 boot_addr = simple_strtoull(argv[0], NULL, 16); diff --git a/arch/arm/mach-imx/mx6/mp.c b/arch/arm/mach-imx/mx6/mp.c index c3806dca3ad0..eda168d86711 100644 --- a/arch/arm/mach-imx/mx6/mp.c +++ b/arch/arm/mach-imx/mx6/mp.c @@ -29,20 +29,20 @@ static uint32_t cpu_ctrl_mask[MAX_CPUS] = { SRC_SCR_CORE_3_ENABLE_MASK }; -int cpu_reset(int nr) +int cpu_reset(u32 nr) { /* Software reset of the CPU N */ src->scr |= cpu_reset_mask[nr]; return 0; } -int cpu_status(int nr) +int cpu_status(u32 nr) { printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr])); return 0; } -int cpu_release(int nr, int argc, char *const argv[]) +int cpu_release(u32 nr, int argc, char *const argv[]) { uint32_t boot_addr; @@ -78,7 +78,7 @@ int is_core_valid(unsigned int core) return 1; } -int cpu_disable(int nr) +int cpu_disable(u32 nr) { /* Disable the CPU N */ src->scr &= ~cpu_ctrl_mask[nr]; diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 42501ca3cec5..b0aa72ed6e02 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -42,7 +42,7 @@ int hold_cores_in_reset(int verbose) return 0; } -int cpu_reset(int nr) +int cpu_reset(u32 nr) { volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); out_be32(&pic->pir, 1 << nr); @@ -53,7 +53,7 @@ int cpu_reset(int nr) return 0; } -int cpu_status(int nr) +int cpu_status(u32 nr) { u32 *table, id = get_my_id(); @@ -79,7 +79,7 @@ int cpu_status(int nr) } #ifdef CONFIG_FSL_CORENET -int cpu_disable(int nr) +int cpu_disable(u32 nr) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -95,7 +95,7 @@ int is_core_disabled(int nr) { return (coredisrl & (1 << nr)); } #else -int cpu_disable(int nr) +int cpu_disable(u32 nr) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -137,7 +137,7 @@ static u8 boot_entry_map[4] = { BOOT_ENTRY_R3_LOWER, }; -int cpu_release(int nr, int argc, char * const argv[]) +int cpu_release(u32 nr, int argc, char * const argv[]) { u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; u64 boot_addr; diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c index 97bd160df8a5..ce300eac5b0e 100644 --- a/arch/powerpc/cpu/mpc86xx/mp.c +++ b/arch/powerpc/cpu/mpc86xx/mp.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; -int cpu_reset(int nr) +int cpu_reset(u32 nr) { /* dummy function so common/cmd_mp.c will build * should be implemented in the future, when cpu_release() @@ -23,13 +23,13 @@ int cpu_reset(int nr) return 1; } -int cpu_status(int nr) +int cpu_status(u32 nr) { /* dummy function so common/cmd_mp.c will build */ return 0; } -int cpu_disable(int nr) +int cpu_disable(u32 nr) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; @@ -66,7 +66,7 @@ int is_core_disabled(int nr) { return 0; } -int cpu_release(int nr, int argc, char * const argv[]) +int cpu_release(u32 nr, int argc, char * const argv[]) { /* dummy function so common/cmd_mp.c will build * should be implemented in the future */ diff --git a/include/common.h b/include/common.h index 60c79137e212..940161f1758b 100644 --- a/include/common.h +++ b/include/common.h @@ -536,10 +536,10 @@ void show_activity(int arg); /* Multicore arch functions */ #ifdef CONFIG_MP -int cpu_status(int nr); -int cpu_reset(int nr); -int cpu_disable(int nr); -int cpu_release(int nr, int argc, char * const argv[]); +int cpu_status(u32 nr); +int cpu_reset(u32 nr); +int cpu_disable(u32 nr); +int cpu_release(u32 nr, int argc, char * const argv[]); #endif #else /* __ASSEMBLY__ */ -- 1.9.1

2 1

[U-Boot] [PATCH v2] mmc: sdhci: Fix MMC HS200 tuning command failures
by Michal Simek 19 Jun '18

19 Jun '18

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> This patch fixes the mmc tuning command failures when tuning pattern data needs to read back for comparision against the expected bit pattern. Reported-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - Fixed typo and added Reported-by drivers/mmc/sdhci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 40e28abda67f..cdeba914f95c 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -161,8 +161,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, /* We shouldn't wait for data inihibit for stop commands, even though they might use busy signaling */ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION || - cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || - cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) + ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)) mask &= ~SDHCI_DATA_INHIBIT; while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { @@ -184,8 +184,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); mask = SDHCI_INT_RESPONSE; - if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || - cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) + if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data) mask = SDHCI_INT_DATA_AVAIL; if (!(cmd->resp_type & MMC_RSP_PRESENT)) -- 1.9.1

3 2

[U-Boot] [PATCH V4 1/2] ARM: image: Add option for ignoring ep bit 3
by Marek Vasut 19 Jun '18

19 Jun '18

Add option to the booti_setup() which indicates to it that the caller requires the image to be relocated to the beginning of the RAM and that the information whether the image can be located anywhere in RAM at 2 MiB aligned boundary or not is to be ignored. This is useful ie. in case the Image is wrapped in another envelope, ie. fitImage and not relocating it but moving it would corrupt the envelope. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Bin Chen <bin.chen(a)linaro.org> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> Cc: Tom Rini <trini(a)konsulko.com> --- V2: Rename ignore_ep to force_reloc V3: No change V4: - Add stdbool.h include - Switch force_reloc to bool --- arch/arm/lib/image.c | 5 +++-- cmd/booti.c | 2 +- include/image.h | 5 ++++- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c index 1a04e2b875..699bf44e70 100644 --- a/arch/arm/lib/image.c +++ b/arch/arm/lib/image.c @@ -26,7 +26,8 @@ struct Image_header { uint32_t res5; }; -int booti_setup(ulong image, ulong *relocated_addr, ulong *size) +int booti_setup(ulong image, ulong *relocated_addr, ulong *size, + bool force_reloc) { struct Image_header *ih; uint64_t dst; @@ -63,7 +64,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size) * images->ep. Otherwise, relocate the image to the base of RAM * since memory below it is not accessible via the linear mapping. */ - if (le64_to_cpu(ih->flags) & BIT(3)) + if (!force_reloc && (le64_to_cpu(ih->flags) & BIT(3))) dst = image - text_offset; else dst = gd->bd->bi_dram[0].start; diff --git a/cmd/booti.c b/cmd/booti.c index 45fbb99b68..04353b68ec 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -37,7 +37,7 @@ static int booti_start(cmd_tbl_t *cmdtp, int flag, int argc, debug("* kernel: cmdline image address = 0x%08lx\n", ld); } - ret = booti_setup(ld, &relocated_addr, &image_size); + ret = booti_setup(ld, &relocated_addr, &image_size, false); if (ret != 0) return 1; diff --git a/include/image.h b/include/image.h index 95d5934344..420b8ff576 100644 --- a/include/image.h +++ b/include/image.h @@ -17,6 +17,7 @@ #include "compiler.h" #include <asm/byteorder.h> +#include <stdbool.h> /* Define this to avoid #ifdefs later on */ struct lmb; @@ -881,9 +882,11 @@ int bootz_setup(ulong image, ulong *start, ulong *end); * @image: Address of image * @start: Returns start address of image * @size : Returns size image + * @force_reloc: Ignore image->ep field, always place image to RAM start * @return 0 if OK, 1 if the image was not recognised */ -int booti_setup(ulong image, ulong *relocated_addr, ulong *size); +int booti_setup(ulong image, ulong *relocated_addr, ulong *size, + bool force_reloc); /*******************************************************************/ /* New uImage format specific code (prefixed with fit_) */ -- 2.17.1

3 7

[U-Boot] [PATCH v2 0/8] Fix some coverity warnings
by Simon Glass 19 Jun '18

19 Jun '18

This series attempts to fix various problems reported by Coverity, in subsystems where I have some knowledge. Changes in v2: - Change log_get_cat_name() to always return a valid string, even if the uclass is not found - Also remove the leading / from the "/spl" path - Add a missing free() from one error path - Add a comment defending the technical memory leaks that remain - Fre the string when device_bind() fails, and presumably doesn't need it Simon Glass (8): log: Fix incorect range check in log_get_cat_name() console: Fix handling of NULL global_data sandbox: Use memcpy() to move overlapping regions fdtgrep: Fix logic of free() in do_fdtgrep() fdtgrep: Separate out checking of two allocations rsa: Fix missing memory leak on error in fdt_add_bignum() spi: sandbox: Fix memory leak in sandbox_sf_bind_emul() sandbox: swap_case: Increase number of base address regs arch/sandbox/cpu/os.c | 5 +++-- common/console.c | 8 ++++++-- common/log.c | 10 +++++++--- drivers/misc/swap_case.c | 2 +- drivers/mtd/spi/sandbox.c | 7 ++++--- include/log.h | 3 ++- lib/rsa/rsa-sign.c | 13 ++++++++++--- tools/fdtgrep.c | 16 +++++++++++----- 8 files changed, 44 insertions(+), 20 deletions(-) -- 2.18.0.rc1.244.gcf134e6275-goog

2 16

[U-Boot] [PATCH] gpio: omap_gpio: Name GPIO's by bank and index with DM_GPIO
by Adam Ford 19 Jun '18

19 Jun '18

There are multiple GPIO banks with up to 32 pins / bank. When using 'gpio status -a' to read the pins, this patch displays both GPIO<bank>_<index> similar to how the device trees display in addition to displaying gpio_# Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c index 4d54df284d..651f6994e4 100644 --- a/drivers/gpio/omap_gpio.c +++ b/drivers/gpio/omap_gpio.c @@ -288,11 +288,17 @@ static int omap_gpio_probe(struct udevice *dev) struct gpio_bank *bank = dev_get_priv(dev); struct omap_gpio_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + int banknum; + char name[18], *str; - uc_priv->bank_name = plat->port_name; + banknum = plat->bank_index; + sprintf(name, "GPIO%d_", banknum + 1); + str = strdup(name); + if (!str) + return -ENOMEM; + uc_priv->bank_name = str; uc_priv->gpio_count = GPIO_PER_BANK; bank->base = (void *)plat->base; - return 0; } -- 2.17.1

2 1

[U-Boot] [PATCH] arm: mach-omap2/omap3/clock.c: Enable all GPIO with CMD_GPIO
by Adam Ford 19 Jun '18

19 Jun '18

When CMD_GPIO is enabled the command 'gpio status -a' can cause a hang or reboot if GPIO banks are not enabled, because it scans all banks. This patch enables all GPIO banks so 'gpio status -a' can fully execute. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/mach-omap2/omap3/clock.c b/arch/arm/mach-omap2/omap3/clock.c index b9d92c62b1..9a03bfa9d3 100644 --- a/arch/arm/mach-omap2/omap3/clock.c +++ b/arch/arm/mach-omap2/omap3/clock.c @@ -750,23 +750,23 @@ void per_clocks_enable(void) setbits_le32(&prcm_base->iclken_per, 0x00000800); #endif -#ifdef CONFIG_OMAP3_GPIO_2 +#if (CONFIG_IS_ENABLED(OMAP3_GPIO_2) || CONFIG_IS_ENABLED(CMD_GPIO)) setbits_le32(&prcm_base->fclken_per, 0x00002000); setbits_le32(&prcm_base->iclken_per, 0x00002000); #endif -#ifdef CONFIG_OMAP3_GPIO_3 +#if (CONFIG_IS_ENABLED(OMAP3_GPIO_3) || CONFIG_IS_ENABLED(CMD_GPIO)) setbits_le32(&prcm_base->fclken_per, 0x00004000); setbits_le32(&prcm_base->iclken_per, 0x00004000); #endif -#ifdef CONFIG_OMAP3_GPIO_4 +#if (CONFIG_IS_ENABLED(OMAP3_GPIO_4) || CONFIG_IS_ENABLED(CMD_GPIO)) setbits_le32(&prcm_base->fclken_per, 0x00008000); setbits_le32(&prcm_base->iclken_per, 0x00008000); #endif -#ifdef CONFIG_OMAP3_GPIO_5 +#if (CONFIG_IS_ENABLED(OMAP3_GPIO_5) || CONFIG_IS_ENABLED(CMD_GPIO)) setbits_le32(&prcm_base->fclken_per, 0x00010000); setbits_le32(&prcm_base->iclken_per, 0x00010000); #endif -#ifdef CONFIG_OMAP3_GPIO_6 +#if (CONFIG_IS_ENABLED(OMAP3_GPIO_6) || CONFIG_IS_ENABLED(CMD_GPIO)) setbits_le32(&prcm_base->fclken_per, 0x00020000); setbits_le32(&prcm_base->iclken_per, 0x00020000); #endif -- 2.17.1

2 1

[U-Boot] [PATCH V3] block: Add SPL_BLOCK_CACHE and default n
by Adam Ford 19 Jun '18

19 Jun '18

When enabling BLOCK_CACHE on devices with limited RAM during SPL, some devices may not boot. This creates an option to enable block caching in SPL by defaults off. It is dependent on SPL_BLK Fixes: 46960ad6d09b ("block: Have BLOCK_CACHE default to y in some cases") Signed-off-by: Adam Ford <aford173(a)gmail.com> --- V3: Change dependency to only SPL_BLK and not BLOCK_CACHE and further clean up macros/ifdefs V2: Clean up macros and ifdefs diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 0792373cfc..f9502b36ba 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -37,6 +37,13 @@ config BLOCK_CACHE it will prevent repeated reads from directory structures and other filesystem data structures. +config SPL_BLOCK_CACHE + bool "Use block device cache in SPL" + depends on SPL_BLK + default n + help + This option enables the disk-block cache in SPL + config IDE bool "Support IDE controllers" select HAVE_BLOCK_DEVICE diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 5fcafb193e..0e80ce9405 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -11,4 +11,4 @@ endif obj-$(CONFIG_IDE) += ide.o obj-$(CONFIG_SANDBOX) += sandbox.o -obj-$(CONFIG_BLOCK_CACHE) += blkcache.o +obj-$(CONFIG_$(SPL_)BLOCK_CACHE) += blkcache.o diff --git a/include/blk.h b/include/blk.h index fc0c239e46..86f6d5057f 100644 --- a/include/blk.h +++ b/include/blk.h @@ -111,7 +111,7 @@ struct blk_desc { #define PAD_TO_BLOCKSIZE(size, blk_desc) \ (PAD_SIZE(size, blk_desc->blksz)) -#ifdef CONFIG_BLOCK_CACHE +#if CONFIG_IS_ENABLED(BLOCK_CACHE) /** * blkcache_read() - attempt to read a set of blocks from cache * -- 2.17.1

2 1

[U-Boot] [PATCH] arm: Do not clear LR on exception in SPL
by Andrew F. Davis 19 Jun '18

19 Jun '18

When an exception or interrupt occurs the link register (LR) may contain the source of the exception, although we do not print the value it may still be extracted with a debugger. When in SPL we loop on getting and exception, but use a linking branch, which over-writes the LR value, use a regular branch instruction here. Signed-off-by: Andrew F. Davis <afd(a)ti.com> --- arch/arm/lib/vectors.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 79afc27e84..d629cb1dc2 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -133,7 +133,7 @@ not_used: irq: fiq: 1: - bl 1b /* hang and never return */ + b 1b /* hang and never return */ #else /* !CONFIG_SPL_BUILD */ -- 2.17.1

2 1