September 2017 - U-Boot

[U-Boot] [PATCH 1/5] dm: usb: Add a new USB controller operation 'get_max_xfer_size'
by Bin Meng 28 Sep '17

28 Sep '17

The HCD may have limitation on the maximum bytes to be transferred in a USB transfer. USB class driver needs to be aware of this. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- drivers/usb/host/usb-uclass.c | 11 +++++++++++ include/usb.h | 22 +++++++++++++++++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index 0b8a501..bc44fc3 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -150,6 +150,17 @@ int usb_update_hub_device(struct usb_device *udev) return ops->update_hub_device(bus, udev); } +int usb_get_max_xfer_size(struct usb_device *udev, size_t *size) +{ + struct udevice *bus = udev->controller_dev; + struct dm_usb_ops *ops = usb_get_ops(bus); + + if (!ops->get_max_xfer_size) + return -ENOSYS; + + return ops->get_max_xfer_size(bus, size); +} + int usb_stop(void) { struct udevice *bus; diff --git a/include/usb.h b/include/usb.h index fad0401..0ddc082 100644 --- a/include/usb.h +++ b/include/usb.h @@ -766,6 +766,14 @@ struct dm_usb_ops { * representation of this hub can be updated (xHCI) */ int (*update_hub_device)(struct udevice *bus, struct usb_device *udev); + + /** + * get_max_xfer_size() - Get HCD's maximum transfer bytes + * + * The HCD may have limitation on the maximum bytes to be transferred + * in a USB transfer. USB class driver needs to be aware of this. + */ + int (*get_max_xfer_size)(struct udevice *bus, size_t *size); }; #define usb_get_ops(dev) ((struct dm_usb_ops *)(dev)->driver->ops) @@ -939,7 +947,7 @@ int usb_new_device(struct usb_device *dev); int usb_alloc_device(struct usb_device *dev); /** - * update_hub_device() - Update HCD's internal representation of hub + * usb_update_hub_device() - Update HCD's internal representation of hub * * After a hub descriptor is fetched, notify HCD so that its internal * representation of this hub can be updated. @@ -950,6 +958,18 @@ int usb_alloc_device(struct usb_device *dev); int usb_update_hub_device(struct usb_device *dev); /** + * usb_get_max_xfer_size() - Get HCD's maximum transfer bytes + * + * The HCD may have limitation on the maximum bytes to be transferred + * in a USB transfer. USB class driver needs to be aware of this. + * + * @dev: USB device + * @size: maximum transfer bytes + * @return 0 if OK, -ve on error + */ +int usb_get_max_xfer_size(struct usb_device *dev, size_t *size); + +/** * usb_emul_setup_device() - Set up a new USB device emulation * * This is normally called when a new emulation device is bound. It tells -- 2.9.2

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 28 Sep '17

28 Sep '17

The following changes since commit 91ebf300934461e450f5ef8f386ea9e55d2636c5: Travis-CI: Checkout only v1.4.3 of dtc (2017-09-22 07:40:06 -0400) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to 78787e28bbefad9d647fc9f7467893b8d2627481: usb: xhci: Set 'Average TRB Length' to 8 for control endpoints (2017-09-23 15:12:29 +0200) ---------------------------------------------------------------- Bin Meng (20): dm: usb: Add a new USB controller operation 'get_max_xfer_size' dm: usb: xhci: Implement get_max_xfer_size() operation dm: usb: ehci: Implement get_max_xfer_size() operation usb: storage: Refactor to use max_xfer_blk from struct us_data dm: usb: storage: Fix broken read/write when both EHCD and xHCD are enabled usb: kbd: Set a default polling mechanism for USB keyboard dm: usb: Fix broken usb_stop() dm: usb: Remove no longer needed blk_unbind_all() usb: xhci: Don't assume LS/FS devices are always behind a HS hub usb: Handle audio extension endpoint descriptor in usb_parse_config() usb: xhci: Add interrupt transfer support usb: Only get 64 bytes device descriptor for full speed devices usb: Read device descriptor after device is addressed for xHCI usb: xhci: Fix max packet size for full speed device endpoint 0 usb: hub: Clear port reset before usb_hub_port_connect_change() usb: hub: Clear BH reset status change for a 3.0 hub usb: xhci: Honor endpoint's interval usb: xhci: Program max burst size for endpoint usb: xhci: Set 'Error Count' to 0 for isoch endpoints usb: xhci: Set 'Average TRB Length' to 8 for control endpoints Eddie Cai (4): usb: rockchip: add the rockusb gadget usb: rockchip: add rockusb command rockchip:usb: add a simple readme for rockusb rockchip: rk3288: enable rockusb support on rk3288 based device Marek Vasut (1): usb: xhci: Set number of event segments and entries to 1 Philipp Tomsich (3): rockchip: xhci: Convert to livetree usb: dwc2: convert to livetree usb: host: ehci-generic: convert to livetree Seung-Woo Kim (1): usb: dwc2: Align size of invalidating dcache before starting DMA arch/arm/include/asm/arch-rockchip/f_rockusb.h | 132 +++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 2 + cmd/Kconfig | 9 ++ cmd/Makefile | 1 + cmd/rockusb.c | 74 ++++++++++ common/usb.c | 45 +++--- common/usb_hub.c | 16 ++- common/usb_storage.c | 64 ++++++--- configs/Cyrus_P5020_defconfig | 1 - configs/Cyrus_P5040_defconfig | 1 - configs/MPC8610HPCD_defconfig | 1 - configs/MPC8641HPCN_36BIT_defconfig | 1 - configs/MPC8641HPCN_defconfig | 1 - configs/apalis_imx6_defconfig | 1 - configs/apalis_imx6_nospl_com_defconfig | 1 - configs/apalis_imx6_nospl_it_defconfig | 1 - configs/chromebit_mickey_defconfig | 8 ++ configs/chromebook_jerry_defconfig | 8 ++ configs/chromebook_minnie_defconfig | 8 ++ configs/colibri_imx6_defconfig | 1 - configs/colibri_imx6_nospl_defconfig | 1 - configs/evb-rk3288_defconfig | 10 ++ configs/fennec-rk3288_defconfig | 6 + configs/firefly-rk3288_defconfig | 7 +- configs/miqi-rk3288_defconfig | 6 + configs/mx6cuboxi_defconfig | 1 - configs/phycore-rk3288_defconfig | 7 + configs/popmetal-rk3288_defconfig | 6 + configs/rock2_defconfig | 9 ++ configs/rpi_2_defconfig | 1 - configs/rpi_3_32b_defconfig | 1 - configs/rpi_3_defconfig | 1 - configs/rpi_defconfig | 1 - configs/sandbox_defconfig | 1 - configs/sandbox_flattree_defconfig | 1 - configs/sandbox_noblk_defconfig | 1 - configs/sandbox_spl_defconfig | 1 - configs/seaboard_defconfig | 1 - configs/tinker-rk3288_defconfig | 6 + configs/ventana_defconfig | 1 - doc/README.rockusb | 51 +++++++ drivers/usb/Kconfig | 2 +- drivers/usb/gadget/Kconfig | 8 ++ drivers/usb/gadget/Makefile | 1 + drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 3 +- drivers/usb/gadget/f_rockusb.c | 691 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/dwc2.c | 2 +- drivers/usb/host/ehci-generic.c | 2 +- drivers/usb/host/ehci-hcd.c | 12 ++ drivers/usb/host/usb-uclass.c | 30 +++- drivers/usb/host/xhci-mem.c | 24 +++- drivers/usb/host/xhci-rockchip.c | 4 +- drivers/usb/host/xhci.c | 264 ++++++++++++++++++++++++++++++++-- drivers/usb/host/xhci.h | 9 +- include/configs/rk3288_common.h | 12 ++ include/linux/usb/ch9.h | 20 +++ include/usb.h | 22 ++- 57 files changed, 1509 insertions(+), 93 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/f_rockusb.h create mode 100644 cmd/rockusb.c create mode 100644 doc/README.rockusb create mode 100644 drivers/usb/gadget/f_rockusb.c

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[U-Boot] [PATCH V2 1/2] pinctrl: rmobile: Add pinconf to Renesas RCar pincontrol driver
by Marek Vasut 28 Sep '17

28 Sep '17

Add pinconf support to the PFC driver, so that it can handle DT props bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- V2: Unlock the pincontrol registers via PMMR when setting drive strength and power source --- drivers/pinctrl/renesas/pfc.c | 187 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 187 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 63e2eeb449..1675485d66 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -477,6 +477,188 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector done: return ret; } +#if CONFIG_IS_ENABLED(PINCONF) +static const struct pinconf_param sh_pfc_pinconf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 }, +}; + +static void __iomem * +sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin, + unsigned int *offset, unsigned int *size) +{ + const struct pinmux_drive_reg_field *field; + const struct pinmux_drive_reg *reg; + unsigned int i; + + for (reg = pfc->info->drive_regs; reg->reg; ++reg) { + for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) { + field = &reg->fields[i]; + + if (field->size && field->pin == pin) { + *offset = field->offset; + *size = field->size; + + return (void __iomem *)(uintptr_t)reg->reg; + } + } + } + + return NULL; +} + +static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, + unsigned int pin, u16 strength) +{ + unsigned int offset; + unsigned int size; + unsigned int step; + void __iomem *reg; + void __iomem *unlock_reg = + (void __iomem *)(uintptr_t)pfc->info->unlock_reg; + u32 val; + + reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); + if (!reg) + return -EINVAL; + + step = size == 2 ? 6 : 3; + + if (strength < step || strength > 24) + return -EINVAL; + + /* Convert the value from mA based on a full drive strength value of + * 24mA. We can make the full value configurable later if needed. + */ + strength = strength / step - 1; + + val = sh_pfc_read_raw_reg(reg, 32); + val &= ~GENMASK(offset + size - 1, offset); + val |= strength << offset; + + if (unlock_reg) + sh_pfc_write_raw_reg(unlock_reg, 32, ~val); + + sh_pfc_write_raw_reg(reg, 32, val); + + return 0; +} + +/* Check whether the requested parameter is supported for a pin. */ +static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, + unsigned int param) +{ + int idx = sh_pfc_get_pin_index(pfc, _pin); + const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + return pin->configs & + (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN); + + case PIN_CONFIG_BIAS_PULL_UP: + return pin->configs & SH_PFC_PIN_CFG_PULL_UP; + + case PIN_CONFIG_BIAS_PULL_DOWN: + return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; + + case PIN_CONFIG_DRIVE_STRENGTH: + return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; + + case PIN_CONFIG_POWER_SOURCE: + return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE; + + default: + return false; + } +} + +static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, + unsigned int param, unsigned int arg) +{ + struct sh_pfc *pfc = pmx->pfc; + void __iomem *pocctrl; + void __iomem *unlock_reg = + (void __iomem *)(uintptr_t)pfc->info->unlock_reg; + u32 addr, val; + int bit, ret; + + if (!sh_pfc_pinconf_validate(pfc, _pin, param)) + return -ENOTSUPP; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_DISABLE: + if (!pfc->info->ops || !pfc->info->ops->set_bias) + return -ENOTSUPP; + + pfc->info->ops->set_bias(pfc, _pin, param); + + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg); + if (ret < 0) + return ret; + + break; + + case PIN_CONFIG_POWER_SOURCE: + if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) + return -ENOTSUPP; + + bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr); + if (bit < 0) { + printf("invalid pin %#x", _pin); + return bit; + } + + if (arg != 1800 && arg != 3300) + return -EINVAL; + + pocctrl = (void __iomem *)(uintptr_t)addr; + + val = sh_pfc_read_raw_reg(pocctrl, 32); + if (arg == 3300) + val |= BIT(bit); + else + val &= ~BIT(bit); + + if (unlock_reg) + sh_pfc_write_raw_reg(unlock_reg, 32, ~val); + + sh_pfc_write_raw_reg(pocctrl, 32, val); + + break; + + default: + return -ENOTSUPP; + } + + return 0; +} + + +static int sh_pfc_pinconf_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int param, unsigned int arg) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector]; + unsigned int i; + + for (i = 0; i < grp->nr_pins; i++) + sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg); + + return 0; +} +#endif static struct pinctrl_ops sh_pfc_pinctrl_ops = { .get_pins_count = sh_pfc_pinctrl_get_pins_count, @@ -486,6 +668,11 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = { .get_functions_count = sh_pfc_pinctrl_get_functions_count, .get_function_name = sh_pfc_pinctrl_get_function_name, +#if CONFIG_IS_ENABLED(PINCONF) + .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params), + .pinconf_params = sh_pfc_pinconf_params, + .pinconf_group_set = sh_pfc_pinconf_group_set, +#endif .pinmux_group_set = sh_pfc_pinctrl_group_set, .set_state = pinctrl_generic_set_state, }; -- 2.11.0

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[U-Boot] [PATCH] rockchip: rk3399: spl: convert to using BOOT_DEVICE_BOOTROM
by Philipp Tomsich 28 Sep '17

28 Sep '17

Instead of directly calling into the back-to-bootrom code, the RK3399 common SPL implementation now uses BOOT_DEVICE_BOOTROM to trigger a transfer back into the bootrom. With this factored out, the spl_board_init function can not be customised for each RK3399 board. Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- arch/arm/mach-rockchip/rk3399-board-spl.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 3406156..1c39d9b 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -1,10 +1,12 @@ /* * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <asm/arch/bootrom.h> #include <asm/arch/clock.h> #include <asm/arch/grf_rk3399.h> #include <asm/arch/hardware.h> @@ -19,9 +21,19 @@ DECLARE_GLOBAL_DATA_PTR; +void board_return_to_bootrom(void) +{ + back_to_bootrom(); +} + u32 spl_boot_device(void) { - return BOOT_DEVICE_MMC1; + u32 boot_device = BOOT_DEVICE_MMC1; + + if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) + return BOOT_DEVICE_BOOTROM; + + return boot_device; } u32 spl_boot_mode(const u32 boot_device) @@ -156,10 +168,6 @@ void spl_board_init(void) } preloader_console_init(); -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - back_to_bootrom(); -#endif - return; err: printf("spl_board_init: Error %d\n", ret); -- 2.1.4

2 2

[U-Boot] [PATCH] rockchip: rk3036: fix grf macro define
by Kever Yang 28 Sep '17

28 Sep '17

Some of macros definition are not correct, fix them according to TRM. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h index 7625f24..d995b7d 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h @@ -209,10 +209,10 @@ enum { GPIO1A3_I2S_LRCKTX, GPIO1A2_SHIFT = 4, - GPIO1A2_MASK = 6 << GPIO1A2_SHIFT, + GPIO1A2_MASK = 3 << GPIO1A2_SHIFT, GPIO1A2_GPIO = 0, GPIO1A2_I2S_LRCKRX, - GPIO1A2_I2S_PWM1_0, + GPIO1A2_PWM1_0, GPIO1A1_SHIFT = 2, GPIO1A1_MASK = 1 << GPIO1A1_SHIFT, -- 1.9.1

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[U-Boot] [PATCH] rockchip: mkimage: add support for rk3128 soc
by Kever Yang 28 Sep '17

28 Sep '17

Add support for rk3128 package header in mkimage tool. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- tools/rkcommon.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 04e8272..1a24e16 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -73,6 +73,7 @@ struct spl_info { static struct spl_info spl_infos[] = { { "rk3036", "RK30", 0x1000, false, false }, + { "rk3128", "RK31", 0x1800, false, false }, { "rk3188", "RK31", 0x8000 - 0x800, true, false }, { "rk322x", "RK32", 0x8000 - 0x1000, false, false }, { "rk3288", "RK32", 0x8000, false, false }, -- 1.9.1

2 3

[U-Boot] [PATCH] rockchip: clk: fix typo in rk322x clock driver
by Kever Yang 28 Sep '17

28 Sep '17

Fix typo RK322X/RK3036 in rk322x clock driver. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- drivers/clk/rockchip/clk_rk322x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 431972e..6bbfde4 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -391,7 +391,7 @@ static int rk322x_clk_bind(struct udevice *dev) /* The reset driver does not have a device node, so bind it here */ ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev); if (ret) - debug("Warning: No RK3036 reset driver: ret=%d\n", ret); + debug("Warning: No RK322x reset driver: ret=%d\n", ret); return 0; } -- 1.9.1

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[U-Boot] [PATCH 1/2] pinctrl: rmobile: Add Renesas RCar pincontrol driver
by Marek Vasut 28 Sep '17

28 Sep '17

Add pinconf support to the PFC driver, so that it can handle DT props bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/pinctrl/renesas/pfc.c | 176 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 176 insertions(+) diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 63e2eeb449..53139d7a26 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -477,6 +477,177 @@ static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector done: return ret; } +#if CONFIG_IS_ENABLED(PINCONF) +static const struct pinconf_param sh_pfc_pinconf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 }, +}; + +static void __iomem * +sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin, + unsigned int *offset, unsigned int *size) +{ + const struct pinmux_drive_reg_field *field; + const struct pinmux_drive_reg *reg; + unsigned int i; + + for (reg = pfc->info->drive_regs; reg->reg; ++reg) { + for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) { + field = &reg->fields[i]; + + if (field->size && field->pin == pin) { + *offset = field->offset; + *size = field->size; + + return (void __iomem *)(uintptr_t)reg->reg; + } + } + } + + return NULL; +} + +static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, + unsigned int pin, u16 strength) +{ + unsigned int offset; + unsigned int size; + unsigned int step; + void __iomem *reg; + u32 val; + + reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); + if (!reg) + return -EINVAL; + + step = size == 2 ? 6 : 3; + + if (strength < step || strength > 24) + return -EINVAL; + + /* Convert the value from mA based on a full drive strength value of + * 24mA. We can make the full value configurable later if needed. + */ + strength = strength / step - 1; + + val = sh_pfc_read_raw_reg(reg, 32); + val &= ~GENMASK(offset + size - 1, offset); + val |= strength << offset; + + sh_pfc_write_raw_reg(reg, 32, val); + + return 0; +} + +/* Check whether the requested parameter is supported for a pin. */ +static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, + unsigned int param) +{ + int idx = sh_pfc_get_pin_index(pfc, _pin); + const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + return pin->configs & + (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN); + + case PIN_CONFIG_BIAS_PULL_UP: + return pin->configs & SH_PFC_PIN_CFG_PULL_UP; + + case PIN_CONFIG_BIAS_PULL_DOWN: + return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; + + case PIN_CONFIG_DRIVE_STRENGTH: + return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; + + case PIN_CONFIG_POWER_SOURCE: + return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE; + + default: + return false; + } +} + +static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, + unsigned int param, unsigned int arg) +{ + struct sh_pfc *pfc = pmx->pfc; + void __iomem *pocctrl; + u32 addr, val; + int bit, ret; + + if (!sh_pfc_pinconf_validate(pfc, _pin, param)) + return -ENOTSUPP; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_DISABLE: + if (!pfc->info->ops || !pfc->info->ops->set_bias) + return -ENOTSUPP; + + pfc->info->ops->set_bias(pfc, _pin, param); + + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg); + if (ret < 0) + return ret; + + break; + + case PIN_CONFIG_POWER_SOURCE: + if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) + return -ENOTSUPP; + + bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr); + if (bit < 0) { + printf("invalid pin %#x", _pin); + return bit; + } + + if (arg != 1800 && arg != 3300) + return -EINVAL; + + pocctrl = (void __iomem *)(uintptr_t)addr; + + val = sh_pfc_read_raw_reg(pocctrl, 32); + if (arg == 3300) + val |= BIT(bit); + else + val &= ~BIT(bit); + sh_pfc_write_raw_reg(pocctrl, 32, val); + + break; + + default: + return -ENOTSUPP; + } + + return 0; +} + + +static int sh_pfc_pinconf_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int param, unsigned int arg) +{ + struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev); + struct sh_pfc_pinctrl *pmx = &priv->pmx; + struct sh_pfc *pfc = &priv->pfc; + const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector]; + unsigned int i; + + for (i = 0; i < grp->nr_pins; i++) + sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg); + + return 0; +} +#endif static struct pinctrl_ops sh_pfc_pinctrl_ops = { .get_pins_count = sh_pfc_pinctrl_get_pins_count, @@ -486,6 +657,11 @@ static struct pinctrl_ops sh_pfc_pinctrl_ops = { .get_functions_count = sh_pfc_pinctrl_get_functions_count, .get_function_name = sh_pfc_pinctrl_get_function_name, +#if CONFIG_IS_ENABLED(PINCONF) + .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params), + .pinconf_params = sh_pfc_pinconf_params, + .pinconf_group_set = sh_pfc_pinconf_group_set, +#endif .pinmux_group_set = sh_pfc_pinctrl_group_set, .set_state = pinctrl_generic_set_state, }; -- 2.11.0

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[U-Boot] [PATCH 1/1] rockchip: rk3399: spl: implicit declaration back_to_bootrom
by Heinrich Schuchardt 28 Sep '17

28 Sep '17

Without #include asm/arch-rockchip/bootrom.h we get: arch/arm/mach-rockchip/rk3399-board-spl.c:162:2: warning: implicit declaration of function ‘back_to_bootrom’ [-Wimplicit-function-declaration] for CONFIG_ROCKCHIP_BACK_TO_BROM=y Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- arch/arm/mach-rockchip/rk3399-board-spl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index d6bf74f7ad..014b8afba0 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -16,6 +16,7 @@ #include <asm/arch/periph.h> #include <asm/arch/sdram.h> #include <asm/arch/timer.h> +#include <asm/arch-rockchip/bootrom.h> #include <dm/pinctrl.h> #include <power/regulator.h> -- 2.14.1

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[U-Boot] imx6qp wandboard getting stuck in U-Boot
by Fabio Estevam 27 Sep '17

27 Sep '17

Hi, With the two attached U-Boot patches plus the dts one I get the following on imx6qp wandboard: U-Boot SPL 2017.09-37395-g28ca7c0-dirty (Sep 27 2017 - 11:04:41) Trying to boot from MMC1 U-Boot 2017.09-37395-g28ca7c0-dirty (Sep 27 2017 - 11:04:41 -0300) CPU: Freescale i.MX6QP rev1.0 at 792 MHz Reset cause: POR I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1 No panel detected: default to HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Board: Wandboard rev D1 Net: FEC [PRIME] Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device Scanning mmc 0:1... Found U-Boot script /boot/boot.scr 336 bytes read in 69 ms (3.9 KiB/s) ## Executing script at 12000000 38550 bytes read in 83 ms (453.1 KiB/s) 6378872 bytes read in 367 ms (16.6 MiB/s) ## Flattened Device Tree blob at 18000000 Booting using the fdt blob at 0x18000000 Using Device Tree in place at 18000000, end 1800c695 (Hangs here) A imx6q wandboard revd1 can boot well though. Looks like an U-Boot issue. I have also tried booting a dtb + zImage from the Technexion kernel with the same result. I am using the very same DDR init from Technexion U-Boot, so not sure why imx6qp wandboard is not lauching the kernel. If you have any ideas, please met me know. Thanks, Fabio Estevam

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