September 2017 - U-Boot

[U-Boot] [PATCH 1/1] evb-rk3399: avoid redefinition of CONFIG_ENV_OFFSET
by Heinrich Schuchardt 29 Sep '17

29 Sep '17

CONFIG_ENV_OFFSET is already defined in include/configs/rockchip-common.h For CONFIG_ROCKCHIP_BACK_TO_BROM=y we redefine CONFIG_ENV_OFFSET to an unsuitable value. We were lucky to get a compiler warning. Remove the incorrect redefinition. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- include/configs/evb_rk3399.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index 015f25a774..66ead6c117 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -10,12 +10,6 @@ #include <configs/rk3399_common.h> #define CONFIG_SYS_MMC_ENV_DEV 1 -/* - * SPL @ 32k for ~36k - * ENV @ 96k - * u-boot @ 128K - */ -#define CONFIG_ENV_OFFSET (96 * 1024) #define SDRAM_BANK_SIZE (2UL << 30) -- 2.14.1

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[U-Boot] [PATCH v2 1/4] rockchip: rk3229: move usb gadget into defconfig
by Kever Yang 29 Sep '17

29 Sep '17

Use the defconfig for all usb gadget and function related option instead of define then in header file. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- Changes in v2: None configs/evb-rk3229_defconfig | 17 +++++++++++++++++ include/configs/evb_rk3229.h | 1 - include/configs/rk322x_common.h | 20 -------------------- 3 files changed, 17 insertions(+), 21 deletions(-) diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index f4ad4c2..bf5baf5 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -14,9 +14,18 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200 CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_BUF_ADDR=0x60800800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 # CONFIG_CMD_IMLS is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y @@ -41,4 +50,12 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Rockchip" +CONFIG_G_DNL_VENDOR_NUM=0x2207 +CONFIG_G_DNL_PRODUCT_NUM=0x320a CONFIG_ERRNO_STR=y diff --git a/include/configs/evb_rk3229.h b/include/configs/evb_rk3229.h index 6e1fd1c..8906c8f 100644 --- a/include/configs/evb_rk3229.h +++ b/include/configs/evb_rk3229.h @@ -40,7 +40,6 @@ #define CONFIG_PREBOOT -#define CONFIG_ANDROID_BOOT_IMAGE #define CONFIG_SYS_BOOT_RAMDISK_HIGH #undef CONFIG_BOOTCOMMAND diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index a145b74..7630bc5 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -40,28 +40,8 @@ #define SDRAM_MAX_SIZE 0x80000000 #ifndef CONFIG_SPL_BUILD -/* usb otg */ -#define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET_DWC2_OTG -#define CONFIG_USB_GADGET_VBUS_DRAW 0 - -/* fastboot */ -#define CONFIG_CMD_FASTBOOT -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_FASTBOOT_FLASH -#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 -#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 - /* usb mass storage */ #define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_CMD_USB_MASS_STORAGE - -#define CONFIG_USB_GADGET_DOWNLOAD -#define CONFIG_G_DNL_MANUFACTURER "Rockchip" -#define CONFIG_G_DNL_VENDOR_NUM 0x2207 -#define CONFIG_G_DNL_PRODUCT_NUM 0x320a /* usb host */ #ifdef CONFIG_CMD_USB -- 1.9.1

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[U-Boot] [PATCH v2 1/5] rockchip: i2c: rk3328: support i2c for rk3328 SoC
by Kever Yang 29 Sep '17

29 Sep '17

From: Elaine Zhang <zhangqing(a)rock-chips.com> Add compatible to support rk3328 i2c Signed-off-by: Elaine Zhang <zhangqing(a)rock-chips.com> Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- Changes in v2: None drivers/i2c/rk_i2c.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index 68e6653..a051893 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -396,6 +396,7 @@ static const struct udevice_id rockchip_i2c_ids[] = { { .compatible = "rockchip,rk3066-i2c" }, { .compatible = "rockchip,rk3188-i2c" }, { .compatible = "rockchip,rk3288-i2c" }, + { .compatible = "rockchip,rk3328-i2c" }, { .compatible = "rockchip,rk3399-i2c" }, { } }; -- 1.9.1

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[U-Boot] [PATCH] rockchip: pinctrl: rk3368: add pinctrl for SDMMC0
by Philipp Tomsich 29 Sep '17

29 Sep '17

Apparently, our earlier assumption that the BROM will always set up the iomux for SDcard communication does not always hold true: when booting U-Boot from the on-module (on the RK3368-uQ7) eMMC, the SDcard pins are not set up and need to be configured by the pinctrl driver to allow SD card access. This change implements support for setting up the SDMMC pins in pinctrl for the RK3368. Reported-by: Klaus Goger <klaus.goger(a)theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- drivers/pinctrl/rockchip/pinctrl_rk3368.c | 39 +++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c index b1f5704..25249e3 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c @@ -208,6 +208,29 @@ enum { GPIO2A0_FLASH_CSN0 = (1 << GPIO2A0_SHIFT), }; +/*GRF_GPIO2B_IOMUX*/ +enum { + GPIO2B3_SHIFT = 6, + GPIO2B3_MASK = GENMASK(GPIO2B3_SHIFT + 1, GPIO2B3_SHIFT), + GPIO2B3_GPIO = 0, + GPIO2B3_SDMMC0_DTECTN = (1 << GPIO2B3_SHIFT), + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = GENMASK(GPIO2B2_SHIFT + 1, GPIO2B2_SHIFT), + GPIO2B2_GPIO = 0, + GPIO2B2_SDMMC0_CMD = (1 << GPIO2B2_SHIFT), + + GPIO2B1_SHIFT = 2, + GPIO2B1_MASK = GENMASK(GPIO2B1_SHIFT + 1, GPIO2B1_SHIFT), + GPIO2B1_GPIO = 0, + GPIO2B1_SDMMC0_CLKOUT = (1 << GPIO2B1_SHIFT), + + GPIO2B0_SHIFT = 0, + GPIO2B0_MASK = GENMASK(GPIO2B0_SHIFT + 1, GPIO2B0_SHIFT), + GPIO2B0_GPIO = 0, + GPIO2B0_SDMMC0_D3 = (1 << GPIO2B0_SHIFT), +}; + /*GRF_GPIO2D_IOMUX*/ enum { GPIO2D7_SHIFT = 14, @@ -580,11 +603,17 @@ static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf, int mmc_id) GPIO2A4_EMMC_CLKOUT); break; case PERIPH_ID_SDCARD: - /* - * We assume that the BROM has already set this up - * correctly for us and that there's nothing to do - * here. - */ + debug("mmc id = %d setting registers!\n", mmc_id); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A5_MASK | GPIO2A7_MASK | + GPIO2A7_MASK, + GPIO2A5_SDMMC0_D0 | GPIO2A6_SDMMC0_D1 | + GPIO2A7_SDMMC0_D2); + rk_clrsetreg(&grf->gpio2b_iomux, + GPIO2B0_MASK | GPIO2B1_MASK | + GPIO2B2_MASK | GPIO2B3_MASK, + GPIO2B0_SDMMC0_D3 | GPIO2B1_SDMMC0_CLKOUT | + GPIO2B2_SDMMC0_CMD | GPIO2B3_SDMMC0_DTECTN); break; default: debug("mmc id = %d iomux error!\n", mmc_id); -- 2.1.4

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[U-Boot] [PATCH] rockchip: board: lion-rk3368: avoid ATF overwriting active SPL stage
by Philipp Tomsich 29 Sep '17

29 Sep '17

The RK3368-uQ7 ATF has been moved back to 0x100000 (1MB from the start of DRAM) to avoid it overwriting the active SPL stage during FIT image loading. This change adapts the .its to match up (again) with our ATF repository for the RK3368-uQ7. Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> --- board/theobroma-systems/lion_rk3368/fit_spl_atf.its | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/theobroma-systems/lion_rk3368/fit_spl_atf.its b/board/theobroma-systems/lion_rk3368/fit_spl_atf.its index 5cdad3b..e3bea5e 100644 --- a/board/theobroma-systems/lion_rk3368/fit_spl_atf.its +++ b/board/theobroma-systems/lion_rk3368/fit_spl_atf.its @@ -29,8 +29,8 @@ os = "arm-trusted-firmware"; arch = "arm64"; compression = "none"; - load = <0x00010000>; - entry = <0x00010000>; + load = <0x00100000>; + entry = <0x00100000>; }; fdt { -- 2.1.4

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[U-Boot] [PATCH] rockchip: rk322x: fix pd_bus hclk/pclk
by Kever Yang 29 Sep '17

29 Sep '17

The pd_bus hclk/pclk source is pd_bus aclk, not the PLL. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- drivers/clk/rockchip/clk_rk322x.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 6bbfde4..9e7e047 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -117,16 +117,16 @@ static void rkclk_init(struct rk322x_cru *cru) pclk_div << CORE_PERI_DIV_SHIFT); /* - * select apll as pd_bus bus clock source and + * select gpll as pd_bus bus clock source and * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); - pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; + pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); - hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; + hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); rk_clrsetreg(&cru->cru_clksel_con[0], -- 1.9.1

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[U-Boot] [PATCH v3 0/5] board: atmel: Convert to support video driver model
by Wenyou Yang 29 Sep '17

29 Sep '17

Convert the boards to support the driver model of LCD/video via enabling CONFIG_DM_VIDEO, remove CONFIG_LCD and the unnecessary code. Changes in v3: - Collect the Reviewed-by tags. Changes in v2: - Rebase the u-boot/master (5541543f686). - Drop the applied patches. - Improve the commit log. Wenyou Yang (5): board: sama5d2_xplained: Convert to CONFIG_DM_VIDEO board: sama5d3xek: Convert to CONFIG_DM_VIDEO board: sama5d4ek: Convert to CONFIG_DM_VIDEO board: sama5d4_xplained: Convert to CONFIG_DM_VIDEO board: at91sam9x5ek: Convert to CONFIG_DM_VIDEO arch/arm/dts/at91-sama5d2_xplained.dts | 60 +++++++++++++ arch/arm/dts/at91-sama5d4_xplained.dts | 25 ++++++ arch/arm/dts/at91-sama5d4ek.dts | 26 ++++++ arch/arm/dts/sama5d2.dtsi | 7 ++ arch/arm/dts/sama5d36ek_cmp.dts | 1 + arch/arm/dts/sama5d3_lcd.dtsi | 21 +---- arch/arm/dts/sama5d3xdm.dtsi | 26 ++++++ arch/arm/dts/sama5d4.dtsi | 21 +---- arch/arm/mach-at91/Kconfig | 4 + board/atmel/at91sam9x5ek/at91sam9x5ek.c | 111 ++---------------------- board/atmel/common/video_display.c | 2 +- board/atmel/sama5d2_xplained/sama5d2_xplained.c | 95 ++------------------ board/atmel/sama5d3xek/sama5d3xek.c | 83 +----------------- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 102 ++-------------------- board/atmel/sama5d4ek/sama5d4ek.c | 97 ++------------------- configs/at91sam9x5ek_dataflash_defconfig | 3 +- configs/at91sam9x5ek_mmc_defconfig | 3 +- configs/at91sam9x5ek_nandflash_defconfig | 3 +- configs/at91sam9x5ek_spiflash_defconfig | 3 +- configs/sama5d2_xplained_mmc_defconfig | 2 + configs/sama5d2_xplained_spiflash_defconfig | 2 + configs/sama5d36ek_cmp_mmc_defconfig | 3 +- configs/sama5d36ek_cmp_nandflash_defconfig | 3 +- configs/sama5d36ek_cmp_spiflash_defconfig | 3 +- configs/sama5d3xek_mmc_defconfig | 3 +- configs/sama5d3xek_nandflash_defconfig | 3 +- configs/sama5d3xek_spiflash_defconfig | 3 +- configs/sama5d4_xplained_mmc_defconfig | 2 + configs/sama5d4_xplained_nandflash_defconfig | 2 + configs/sama5d4_xplained_spiflash_defconfig | 2 + configs/sama5d4ek_mmc_defconfig | 3 +- configs/sama5d4ek_nandflash_defconfig | 3 +- configs/sama5d4ek_spiflash_defconfig | 3 +- include/configs/at91sam9x5ek.h | 10 --- include/configs/sama5d2_xplained.h | 12 --- include/configs/sama5d3xek.h | 9 -- include/configs/sama5d4_xplained.h | 11 --- include/configs/sama5d4ek.h | 9 -- 38 files changed, 217 insertions(+), 564 deletions(-) -- 2.13.0

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[U-Boot] [PATCH] usb: dwc3: add UniPhier specific glue layer
by Masahiro Yamada 29 Sep '17

29 Sep '17

Add UniPhier platform specific glue layer to support USB3 Host mode on Synopsys DWC3 IP. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> Reviewed-by: Marek Vasut <marex(a)denx.de> --- I sent amost the same one last year, and applied in u-boot-usb: http://patchwork.ozlabs.org/patch/622564/ I retracted it for some reasons, but now U-Boot has similar code as I was trying to push one year ago. I am resending the driver. drivers/usb/dwc3/Kconfig | 7 +++ drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-uniphier.c | 120 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 drivers/usb/dwc3/dwc3-uniphier.c diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index a291ceb..ae7fc1c 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -37,6 +37,13 @@ config USB_DWC3_OMAP Say 'Y' here if you have one such device +config USB_DWC3_UNIPHIER + bool "DesignWare USB3 Host Support on UniPhier Platforms" + depends on ARCH_UNIPHIER && USB_XHCI_DWC3 + help + Support of USB2/3 functionality in Socionext UniPhier platforms. + Say 'Y' here if you have one such device. + menu "PHY Subsystem" config USB_DWC3_PHY_OMAP diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 2964bae..5149776 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -9,5 +9,6 @@ dwc3-y := core.o obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o +obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o diff --git a/drivers/usb/dwc3/dwc3-uniphier.c b/drivers/usb/dwc3/dwc3-uniphier.c new file mode 100644 index 0000000..0d13770 --- /dev/null +++ b/drivers/usb/dwc3/dwc3-uniphier.c @@ -0,0 +1,120 @@ +/* + * UniPhier Specific Glue Layer for DWC3 + * + * Copyright (C) 2016-2017 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro(a)socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/sizes.h> + +#define UNIPHIER_PRO4_DWC3_RESET 0x40 +#define UNIPHIER_PRO4_DWC3_RESET_XIOMMU BIT(5) +#define UNIPHIER_PRO4_DWC3_RESET_XLINK BIT(4) +#define UNIPHIER_PRO4_DWC3_RESET_PHY_SS BIT(2) + +#define UNIPHIER_PRO5_DWC3_RESET 0x00 +#define UNIPHIER_PRO5_DWC3_RESET_PHY_S1 BIT(17) +#define UNIPHIER_PRO5_DWC3_RESET_PHY_S0 BIT(16) +#define UNIPHIER_PRO5_DWC3_RESET_XLINK BIT(15) +#define UNIPHIER_PRO5_DWC3_RESET_XIOMMU BIT(14) + +#define UNIPHIER_PXS2_DWC3_RESET 0x00 +#define UNIPHIER_PXS2_DWC3_RESET_XLINK BIT(15) + +static int uniphier_pro4_dwc3_init(void __iomem *regs) +{ + u32 tmp; + + tmp = readl(regs + UNIPHIER_PRO4_DWC3_RESET); + tmp &= ~UNIPHIER_PRO4_DWC3_RESET_PHY_SS; + tmp |= UNIPHIER_PRO4_DWC3_RESET_XIOMMU | UNIPHIER_PRO4_DWC3_RESET_XLINK; + writel(tmp, regs + UNIPHIER_PRO4_DWC3_RESET); + + return 0; +} + +static int uniphier_pro5_dwc3_init(void __iomem *regs) +{ + u32 tmp; + + tmp = readl(regs + UNIPHIER_PRO5_DWC3_RESET); + tmp &= ~(UNIPHIER_PRO5_DWC3_RESET_PHY_S1 | + UNIPHIER_PRO5_DWC3_RESET_PHY_S0); + tmp |= UNIPHIER_PRO5_DWC3_RESET_XLINK | UNIPHIER_PRO5_DWC3_RESET_XIOMMU; + writel(tmp, regs + UNIPHIER_PRO5_DWC3_RESET); + + return 0; +} + +static int uniphier_pxs2_dwc3_init(void __iomem *regs) +{ + u32 tmp; + + tmp = readl(regs + UNIPHIER_PXS2_DWC3_RESET); + tmp |= UNIPHIER_PXS2_DWC3_RESET_XLINK; + writel(tmp, regs + UNIPHIER_PXS2_DWC3_RESET); + + return 0; +} + +static int uniphier_dwc3_probe(struct udevice *dev) +{ + fdt_addr_t base; + void __iomem *regs; + int (*init)(void __iomem *regs); + int ret; + + base = devfdt_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + regs = ioremap(base, SZ_32K); + if (!regs) + return -ENOMEM; + + init = (typeof(init))dev_get_driver_data(dev); + ret = init(regs); + if (ret) + dev_err(dev, "failed to init glue layer\n"); + + iounmap(regs); + + return ret; +} + +static const struct udevice_id uniphier_dwc3_match[] = { + { + .compatible = "socionext,uniphier-pro4-dwc3", + .data = (ulong)uniphier_pro4_dwc3_init, + }, + { + .compatible = "socionext,uniphier-pro5-dwc3", + .data = (ulong)uniphier_pro5_dwc3_init, + }, + { + .compatible = "socionext,uniphier-pxs2-dwc3", + .data = (ulong)uniphier_pxs2_dwc3_init, + }, + { + .compatible = "socionext,uniphier-ld20-dwc3", + .data = (ulong)uniphier_pxs2_dwc3_init, + }, + { + .compatible = "socionext,uniphier-pxs3-dwc3", + .data = (ulong)uniphier_pxs2_dwc3_init, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(usb_xhci) = { + .name = "uniphier-dwc3", + .id = UCLASS_SIMPLE_BUS, + .of_match = uniphier_dwc3_match, + .probe = uniphier_dwc3_probe, +}; -- 2.7.4

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[U-Boot] Uboot send pull request
by uboot＠andestech.com 29 Sep '17

29 Sep '17

Hi Tom, Please pull the following patch from u-boot-nds32 into your tree. Thanks! The following changes since commit 6e9b109aa9bcdd094e77da9fb03de8b44da8eb9d: Merge git://git.denx.de/u-boot-usb (2017-09-27 09:39:48 -0400) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master for you to fetch changes up to 9c7ffc94dce3d7438a19576a833d96956ca7f3eb: nds32: Fix io.h warning message about readb (2017-09-28 13:16:54 +0800) ---------------------------------------------------------------- rick (1): nds32: Fix io.h warning message about readb arch/nds32/include/asm/io.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)

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[U-Boot] [GIT PULL] Please pull u-boot-mmc master (take 2)
by Jaehoon Chung 29 Sep '17

29 Sep '17

Dear Tom, Could you pull these patches into u-boot/master? If there is a problem, let me know, plz. I may reply late, because it will start my national holidays from Tomorrow to 10th of Oct. The following changes since commit 6e9b109aa9bcdd094e77da9fb03de8b44da8eb9d: Merge git://git.denx.de/u-boot-usb (2017-09-27 09:39:48 -0400) are available in the git repository at: git://git.denx.de/u-boot-mmc.git master for you to fetch changes up to 3d3108d459e6d034f20aab33b11f4d23537f0c27: mmc: sdhci-cadence: set timing mode register depending on frequency (2017-09-29 11:34:22 +0900) ---------------------------------------------------------------- Marek Vasut (2): mmc: uniphier-sd: Update the file to match V3 patchset mmc: uniphier-sd: Add vqmmc regulator support Masahiro Yamada (1): mmc: sdhci-cadence: set timing mode register depending on frequency Patrice Chotard (1): mmc: Add MMC support for stm32h7 Socs Seung-Woo Kim (1): spl: spl_mmc: add __maybe_unused to mmc_load_image_raw_sector() common/spl/spl_mmc.c | 5 +- drivers/mmc/Kconfig | 8 + drivers/mmc/Makefile | 1 + drivers/mmc/sdhci-cadence.c | 51 ++++ drivers/mmc/stm32_sdmmc2.c | 608 ++++++++++++++++++++++++++++++++++++++++++++ drivers/mmc/uniphier-sd.c | 96 ++++--- 6 files changed, 726 insertions(+), 43 deletions(-) create mode 100644 drivers/mmc/stm32_sdmmc2.c Best Regards, Jaehoon Chung

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