February 2017 - U-Boot

[U-Boot] [PATCH] DTS: Enable top USB port on CEI-TK1-SOM
by Peter Chubb 07 Feb '17

07 Feb '17

From: Peter Chubb <Peter.Chubb(a)data61.csiro.au> Only one of the two USB ports were enabled; this patch enables the one at the top of the board. Signed-off-by: Peter Chubb <peter.chubb(a)data61.csiro.au> --- arch/arm/dts/tegra124-cei-tk1-som.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/tegra124-cei-tk1-som.dts b/arch/arm/dts/tegra124-cei-tk1-som.dts index c4d4f9d89f..1680004c09 100644 --- a/arch/arm/dts/tegra124-cei-tk1-som.dts +++ b/arch/arm/dts/tegra124-cei-tk1-som.dts @@ -21,7 +21,8 @@ spi0 = "/spi@7000d400"; spi1 = "/spi@7000da00"; usb0 = "/usb@7d000000"; - usb1 = "/usb@7d008000"; + usb1 = "/usb@7d004000"; + usb2 = "/usb@7d008000"; }; memory { @@ -316,6 +317,14 @@ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; }; + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + }; + usb@7d008000 { status = "okay"; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; -- 2.11.0

1 0

[U-Boot] [PATCH v2 0/7] arm64: mvebu: Add support for A8K community board
by kostap＠marvell.com 06 Feb '17

06 Feb '17

From: Konstantin Porotchkin <kostap(a)marvell.com> This patch series adds initil support for A8K community board MACCHIATOBin manufactured by SolidRun. It should be applied on top of Stefan Roese patches adding support for SD/eMMC devices on Marvell A37x0/A80x0/A70x0 SoCs. The top level patch is called: "arm64: mvebu: Enable SDHCI/MMC support for the db-88f7040/8040" The default board DTS file is based on the original work of Rabeeh Khory from SolidRun. Changes for v2: - Move PCIe reset GPIO support from board-specific function to mvebu PCIe driver - Move VBUS GPIO support from board-specific function to mvebu XHCI driver - Allow MMC support for "bubt" command with and without CONFIG_BLK Konstantin Porotchkin (6): arm64: mvebu: Update bubt command MMC block device access arm64: mvebu: gpio: Add GPIO nodes to A8K family devices arm64: mvebu: dts: Add i2c1 pin definitions to CPM mvebu: usb: xhci: Add support for VBUS controlled by GPIO mvebu: pcie: Add support for GPIO reset for PCIe device arm64: mvebu: Add default configuraton for MACCHIATOBin board Rabeeh Khoury (1): arm64: mvebu: dts: Add DTS file for MACCHIATOBin board arch/arm/dts/Makefile | 1 + arch/arm/dts/armada-7040.dtsi | 1 + arch/arm/dts/armada-8040-mcbin.dts | 253 ++++++++++++++++++++++ arch/arm/dts/armada-8040.dtsi | 1 + arch/arm/dts/armada-ap806.dtsi | 8 + arch/arm/dts/armada-cp110-master.dtsi | 22 ++ arch/arm/dts/armada-cp110-slave.dtsi | 18 ++ cmd/mvebu/bubt.c | 25 ++- configs/mvebu_mcbin-88f8040_defconfig | 65 ++++++ doc/device-tree-bindings/pci/armada8k-pcie.txt | 49 +++++ doc/device-tree-bindings/usb/marvell.xhci-usb.txt | 29 +++ drivers/pci/pcie_dw_mvebu.c | 20 ++ drivers/usb/host/xhci-mvebu.c | 14 ++ 13 files changed, 503 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/armada-8040-mcbin.dts create mode 100644 configs/mvebu_mcbin-88f8040_defconfig create mode 100644 doc/device-tree-bindings/pci/armada8k-pcie.txt create mode 100644 doc/device-tree-bindings/usb/marvell.xhci-usb.txt -- 2.7.4

4 14

[U-Boot] [PATCH 1/5][v8] arch: powerpc: Move CONFIG_FSL_IFC to Kconfig
by Prabhakar Kushwaha 06 Feb '17

06 Feb '17

Enable IFC from Kconfig. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v5: Added first time Changes for v6: Sending as it is Changes for v7: Sending as it is Changes for v8: Sending as it is arch/powerpc/cpu/mpc85xx/Kconfig | 17 +++++++++++++++++ include/configs/B4860QDS.h | 1 - include/configs/BSC9131RDB.h | 1 - include/configs/BSC9132QDS.h | 1 - include/configs/C29XPCIE.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/T102xQDS.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T1040QDS.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/t4qds.h | 1 - 14 files changed, 17 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 38ea4c1..a3db014 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -374,6 +374,7 @@ config ARCH_B4420 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_B4860 bool @@ -398,6 +399,7 @@ config ARCH_B4860 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_BSC9131 bool @@ -410,6 +412,7 @@ config ARCH_BSC9131 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select FSL_IFC config ARCH_BSC9132 bool @@ -426,6 +429,7 @@ config ARCH_BSC9132 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_IFC config ARCH_C29X bool @@ -438,6 +442,7 @@ config ARCH_C29X select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_6 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_IFC config ARCH_MPC8536 bool @@ -553,6 +558,7 @@ config ARCH_P1010 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_IFC config ARCH_P1011 bool @@ -795,6 +801,7 @@ config ARCH_T1023 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select FSL_IFC config ARCH_T1024 bool @@ -811,6 +818,7 @@ config ARCH_T1024 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select FSL_IFC config ARCH_T1040 bool @@ -828,6 +836,7 @@ config ARCH_T1040 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select FSL_IFC config ARCH_T1042 bool @@ -845,6 +854,7 @@ config ARCH_T1042 select SYS_FSL_QORIQ_CHASSIS2 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 + select FSL_IFC config ARCH_T2080 bool @@ -866,6 +876,7 @@ config ARCH_T2080 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_T2081 bool @@ -885,6 +896,7 @@ config ARCH_T2081 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_T4160 bool @@ -905,6 +917,7 @@ config ARCH_T4160 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config ARCH_T4240 bool @@ -928,6 +941,7 @@ config ARCH_T4240 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_IFC config BOOKE bool @@ -1260,6 +1274,9 @@ config SYS_PPC64 config SYS_PPC_E500_USE_DEBUG_TLB bool +config FSL_IFC + bool + config SYS_PPC_E500_DEBUG_TLB int "Temporary TLB entry for external debugger" depends on SYS_PPC_E500_USE_DEBUG_TLB diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index fc99b96..2fdb869 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -63,7 +63,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 77f0927..4116234 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -46,7 +46,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_TSEC_ENET diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index f336f28..b2c8b03 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -68,7 +68,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index e1ce7ad..8f68748 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -68,7 +68,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 1d01e7f..3594e56 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -130,7 +130,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 2c3b660..0319f18 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 79c34ef..459435f 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 15a29cb..9de6185 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -51,7 +51,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 45aaf90..b778ace 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -162,7 +162,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 606c928..d6f647a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -33,7 +33,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 825bf25..53bd684 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index be18f66..2b03801 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -73,7 +73,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 15c0e89..7803a84 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -- 2.7.4

2 1

[U-Boot] [PATCH 1/2][v4] board: freescale: ls1012a: Enable secure DDR on LS1012A platforms
by Prabhakar Kushwaha 06 Feb '17

06 Feb '17

PPA binary needs to be relocated on secure DDR, hence marking out a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag is set Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: Sending as it is Changes for v3: Rebased top of the tree Changes for v4: incorporated York's comments arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ board/freescale/ls1012afrdm/ls1012afrdm.c | 29 +++++++++++++++++++++++ board/freescale/ls1012aqds/ls1012aqds.c | 29 +++++++++++++++++++++++ board/freescale/ls1012ardb/ls1012ardb.c | 29 +++++++++++++++++++++++ include/configs/ls1012a_common.h | 1 + 5 files changed, 91 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 8c426af..83f5501 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -192,6 +192,9 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + #elif defined(CONFIG_ARCH_LS1046A) #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index b03bdb8..c2432c3 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -85,3 +85,32 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + +void dram_init_banksize(void) +{ + /* + * gd->arch.secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } +} diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 88fb4ce..bdd9529 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -159,3 +159,32 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif + +void dram_init_banksize(void) +{ + /* + * gd->arch.secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } +} diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 65fa94c..2dece02 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -159,3 +159,32 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + +void dram_init_banksize(void) +{ + /* + * gd->secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } +} diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 81f8d62..0965afa 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -29,6 +29,7 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL /* Generic Timer Definitions */ #define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */ -- 2.7.4

2 1

[U-Boot] [PATCH] armv8: ls1046a: Enable workaround for erratum A-008336
by York Sun 06 Feb '17

06 Feb '17

Erratum A-008336 applies to LS1046A per latest SoC document. Signed-off-by: York Sun <york.sun(a)nxp.com> CC: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index ba411e2..2caeee7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -30,6 +30,7 @@ config ARCH_LS1046A select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 select SYS_FSL_ERRATUM_A009801 select SYS_FSL_ERRATUM_A009803 -- 2.7.4

2 1

[U-Boot] [PATCH] armv7: ls1021aqds: Set cpo_sample for erratum A-009942
by York Sun 06 Feb '17

06 Feb '17

Set cpo_sample as suggested by the driver "WARN: pls set popts->cpo_sample = 0x58 in <board>/ddr.c to optimize cpo". Signed-off-by: York Sun <york.sun(a)nxp.com> CC: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- board/freescale/ls1021aqds/ddr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 6435bf9..2f66ba9 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -96,6 +96,9 @@ found: #else popts->cswl_override = DDR_CSWL_CS0; + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x58; + /* DHC_EN =1, ODT = 75 Ohm */ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -- 2.7.4

2 1

[U-Boot] [PATCH] drivers: net: fsl-mc: Fixup MAC addresses in DPC
by Bogdan Purcareata 06 Feb '17

06 Feb '17

Fixup port_mac_address property in MC DPC with values from the u-boot environment. Since u-boot already reads the environment MAC addresses when probing the PHYs, use these values. The u-boot environment MAC addresses take precedence over any eventual ones defined in the DPC, except for the case where they are randomly assigned (no u-boot env value declared for port). The patch assumes the "/board_info/ports/" node is present in the DPC. Signed-off-by: Bogdan Purcareata <bogdan.purcareata(a)nxp.com> --- drivers/net/fsl-mc/mc.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 101 insertions(+), 2 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 2a2d3e5..cca579a 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -7,6 +7,7 @@ #include <errno.h> #include <asm/io.h> #include <libfdt.h> +#include <net.h> #include <fdt_support.h> #include <fsl-mc/fsl_mc.h> #include <fsl-mc/fsl_mc_sys.h> @@ -197,10 +198,81 @@ static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr, return 0; } +static int mc_fixup_dpc_mac_addr(void *blob, int noff, int dpmac_id, + struct eth_device *eth_dev) +{ + int nodeoffset, err = 0; + char mac_name[10]; + const char link_type_mode[] = "FIXED_LINK"; + unsigned char env_enetaddr[6]; + + sprintf(mac_name, "mac@%d", dpmac_id); + + /* node not found - create it */ + nodeoffset = fdt_subnode_offset(blob, noff, (const char *) mac_name); + if (nodeoffset < 0) { + err = fdt_increase_size(blob, 200); + if (err) { + printf("fdt_increase_size: err=%s\n", + fdt_strerror(err)); + return err; + } + + nodeoffset = fdt_add_subnode(blob, noff, mac_name); + + /* add default property of fixed link */ + err = fdt_appendprop_string(blob, nodeoffset, + "link_type", link_type_mode); + if (err) { + printf("fdt_appendprop_string: err=%s\n", + fdt_strerror(err)); + return err; + } + } + + /* port_mac_address property present in DPC */ + if (fdt_get_property(blob, nodeoffset, "port_mac_address", NULL)) { + /* MAC addr randomly assigned - leave the one in DPC */ + eth_getenv_enetaddr_by_index("eth", eth_dev->index, + env_enetaddr); + if (is_zero_ethaddr(env_enetaddr)) + return err; + + /* replace DPC MAC address with u-boot env one */ + err = fdt_setprop(blob, nodeoffset, "port_mac_address", + eth_dev->enetaddr, 6); + if (err) { + printf("fdt_setprop mac: err=%s\n", fdt_strerror(err)); + return err; + } + + return 0; + } + + /* append port_mac_address property to mac node in DPC */ + err = fdt_increase_size(blob, 80); + if (err) { + printf("fdt_increase_size: err=%s\n", fdt_strerror(err)); + return err; + } + + err = fdt_appendprop(blob, nodeoffset, + "port_mac_address", eth_dev->enetaddr, 6); + if (err) { + printf("fdt_appendprop: err=%s\n", fdt_strerror(err)); + return err; + } + + return err; +} + static int mc_fixup_dpc(u64 dpc_addr) { void *blob = (void *)dpc_addr; - int nodeoffset; + int nodeoffset, err = 0; + char ethname[10]; + struct eth_device *eth_dev; + int i; /* delete any existing ICID pools */ nodeoffset = fdt_path_offset(blob, "/resources/icid_pools"); @@ -222,9 +294,36 @@ static int mc_fixup_dpc(u64 dpc_addr) FSL_DPAA2_STREAM_ID_END - FSL_DPAA2_STREAM_ID_START + 1, 1); + /* fixup MAC addresses for dpmac ports */ + nodeoffset = fdt_path_offset(blob, "/board_info/ports"); + if (nodeoffset < 0) + goto out; + + for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { + /* port not enabled */ + if ((wriop_is_enabled_dpmac(i) != 1) || + (wriop_get_phy_address(i) == -1)) + continue; + + sprintf(ethname, "DPMAC%d@%s", i, + phy_interface_strings[wriop_get_enet_if(i)]); + + eth_dev = eth_get_dev_by_name(ethname); + if (eth_dev == NULL) + continue; + + err = mc_fixup_dpc_mac_addr(blob, nodeoffset, i, eth_dev); + if (err) { + printf("mc_fixup_dpc_mac_addr failed: err=%s\n", + fdt_strerror(err)); + goto out; + } + } + +out: flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob)); - return 0; + return err; } static int load_mc_dpc(u64 mc_ram_aligned_base_addr, size_t mc_ram_size, -- 1.9.1

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[U-Boot] [PATCH 1/2] armv8: ls1046a: added usb nodes in dts
by yuantian.tang＠nxp.com 06 Feb '17

06 Feb '17

From: Tang Yuantian <Yuantian.Tang(a)nxp.com> The LS1046A processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which supplies 5v power at up to 1.2 A. The power enable and power-fault-detect pins are connected to the LS1046A processor via CPLD for individual port management. Signed-off-by: Tang Yuantian <yuantian.tang(a)nxp.com> --- arch/arm/dts/fsl-ls1046a.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index aaf0ae9..408e81e 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -217,6 +217,27 @@ status = "disabled"; }; + usb0: usb@2f00000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <0 60 4>; + dr_mode = "host"; + }; + + usb1: usb@3000000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3000000 0x0 0x10000>; + interrupts = <0 61 4>; + dr_mode = "host"; + }; + + usb2: usb@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 63 4>; + dr_mode = "host"; + }; + pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2] armv8: ls1046aqds: added usb feature support
by yuantian.tang＠nxp.com 06 Feb '17

06 Feb '17

From: Tang Yuantian <Yuantian.Tang(a)nxp.com> The LS1046AQDS processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which supplies 5v power at up to 1.2 A. The power enable and power-fault-detect pins are connected to the LS1046A processor via CPLD for individual port management. Signed-off-by: Tang Yuantian <yuantian.tang(a)nxp.com> --- v2: - fix compiling warning. include/configs/ls1046aqds.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 3618a06..b995cd2 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -135,6 +135,18 @@ unsigned long get_board_ddr_clk(void); #define CFG_LPUART_EN 0x2 #endif +/* USB */ +#define CONFIG_HAS_FSL_XHCI_USB +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_HCD +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI -- 2.1.0.27.g96db324

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[U-Boot] where is (eg) "BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC" defined?
by Robert P. J. Day 06 Feb '17

06 Feb '17

i'm sure i'm missing something obvious, but i'm perusing "include/config_distro_bootcmd.h" for the first time, and i can understand the *principle* behind: /* * A note on error handling: It is possible for BOOT_TARGET_DEVICES to * reference a device that is not enabled in the U-Boot configuration, e.g. * it may include MMC in the list without CONFIG_CMD_MMC being enabled. Given * that BOOT_TARGET_DEVICES is a macro that's expanded by the C pre-processor * at compile time, it's not possible to detect and report such problems via * a simple #ifdef/#error combination. Still, the code needs to report errors. * The best way I've found to do this is to make BOOT_TARGET_DEVICES expand to * reference a non-existent symbol, and have the name of that symbol encode * the error message. Consequently, this file contains references to e.g. * BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC. Given the * prevalence of capitals here, this looks like a pre-processor macro and * hence seems like it should be all capitals, but it's really an error * message that includes some other pre-processor symbols in the text. */ but, still, how is that name resolved to the corresponding error message? what am i missing here? rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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