February 2017 - U-Boot

[U-Boot] [RESEND PATCH v2] ARM: at91: add default config file for sama5d36ek CMP board
by Wenyou Yang 07 Feb '17

07 Feb '17

The sama5d36ek CMP board is the variant of sama5d3xek board. It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865, and some power rail. Its main purpose is used to measure the power consumption. As those changes are done in at91bootstrap, in U-Boot, use another device tree file, no code to change. As there is additional power consumption due to the USB Host and USB Device enabled, for the power consumption measurement, disable the USB host and device. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- Changes in v2: - rebase on the patch set: [PATCH v2 0/7] board: sama5d3: convert boards to support DM/DT http://lists.denx.de/pipermail/u-boot/2017-February/280515.html configs/sama5d36ek_cmp_mmc_defconfig | 58 ++++++++++++++++++++++++++++++ configs/sama5d36ek_cmp_nandflash_defconfig | 57 +++++++++++++++++++++++++++++ configs/sama5d36ek_cmp_spiflash_defconfig | 57 +++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+) create mode 100644 configs/sama5d36ek_cmp_mmc_defconfig create mode 100644 configs/sama5d36ek_cmp_nandflash_defconfig create mode 100644 configs/sama5d36ek_cmp_spiflash_defconfig diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig new file mode 100644 index 0000000000..ee72c59afe --- /dev/null +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_LCD=y diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig new file mode 100644 index 0000000000..aabbf4a4da --- /dev/null +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent" +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_LCD=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig new file mode 100644 index 0000000000..e4131d9d2a --- /dev/null +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_LCD=y -- 2.11.0

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[U-Boot] [PATCH v2] ARM: at91: add default config file for sama5d36ek CMP board
by Wenyou Yang 07 Feb '17

07 Feb '17

The sama5d36ek CMP board is the variant of sama5d3xek board. It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865, and some power rail. Its main purpose is used to measure the power consumption. As those changes are done in at91bootstrap, in U-Boot, use another device tree file, no code to change. As there is additional power consumption due to the USB Host and USB Device enabled, for the power consumption measurement, disable the USB host and device. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- Changes in v2: - rebase on the patch set: [PATCH v2 0/7] board: sama5d3: convert boards to support DM/DT http://lists.denx.de/pipermail/u-boot/2017-February/280515.html configs/sama5d36ek_cmp_mmc_defconfig | 58 ++++++++++++++++++++++++++++++ configs/sama5d36ek_cmp_nandflash_defconfig | 57 +++++++++++++++++++++++++++++ configs/sama5d36ek_cmp_spiflash_defconfig | 57 +++++++++++++++++++++++++++++ include/configs/sama5d3xek.h | 1 + 4 files changed, 173 insertions(+) create mode 100644 configs/sama5d36ek_cmp_mmc_defconfig create mode 100644 configs/sama5d36ek_cmp_nandflash_defconfig create mode 100644 configs/sama5d36ek_cmp_spiflash_defconfig diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig new file mode 100644 index 0000000000..ee72c59afe --- /dev/null +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_LCD=y diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig new file mode 100644 index 0000000000..aabbf4a4da --- /dev/null +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent" +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_LCD=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig new file mode 100644 index 0000000000..e4131d9d2a --- /dev/null +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_LCD=y diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 7039d027b6..05848775e3 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -114,6 +114,7 @@ #define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK" #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_DOS_PARTITION #define CONFIG_FAT_WRITE #endif -- 2.11.0

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[U-Boot] [PATCH v2] ARM: dts: at91: add device tree files for at91sam9x5ek
by Wenyou Yang 07 Feb '17

07 Feb '17

The device tree source files of at91sam9x5ek board are copied from the Linux kernel, do the changes below. - Add the reg property for the pinctrl node. - Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's slibling nodes, instead of the child nodes. - Change the compatible of the spi flash to "spi-flash". - Add spi0 aliases. - Fix the compile warnings. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- Changes in v2: - Rebase on the patch set: [PATCH v3 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D3 http://lists.denx.de/pipermail/u-boot/2017-February/280475.html arch/arm/dts/Makefile | 7 + arch/arm/dts/at91sam9g15.dtsi | 29 + arch/arm/dts/at91sam9g15ek.dts | 41 ++ arch/arm/dts/at91sam9g25.dtsi | 31 + arch/arm/dts/at91sam9g25ek.dts | 69 ++ arch/arm/dts/at91sam9g35.dtsi | 30 + arch/arm/dts/at91sam9g35ek.dts | 46 ++ arch/arm/dts/at91sam9x25.dtsi | 32 + arch/arm/dts/at91sam9x25ek.dts | 30 + arch/arm/dts/at91sam9x35.dtsi | 31 + arch/arm/dts/at91sam9x35ek.dts | 45 ++ arch/arm/dts/at91sam9x5.dtsi | 1292 +++++++++++++++++++++++++++++++++++ arch/arm/dts/at91sam9x5_can.dtsi | 71 ++ arch/arm/dts/at91sam9x5_isi.dtsi | 72 ++ arch/arm/dts/at91sam9x5_lcd.dtsi | 165 +++++ arch/arm/dts/at91sam9x5_macb0.dtsi | 67 ++ arch/arm/dts/at91sam9x5_macb1.dtsi | 55 ++ arch/arm/dts/at91sam9x5_usart3.dtsi | 69 ++ arch/arm/dts/at91sam9x5cm.dtsi | 100 +++ arch/arm/dts/at91sam9x5dm.dtsi | 101 +++ arch/arm/dts/at91sam9x5ek.dtsi | 165 +++++ 21 files changed, 2548 insertions(+) create mode 100644 arch/arm/dts/at91sam9g15.dtsi create mode 100644 arch/arm/dts/at91sam9g15ek.dts create mode 100644 arch/arm/dts/at91sam9g25.dtsi create mode 100644 arch/arm/dts/at91sam9g25ek.dts create mode 100644 arch/arm/dts/at91sam9g35.dtsi create mode 100644 arch/arm/dts/at91sam9g35ek.dts create mode 100644 arch/arm/dts/at91sam9x25.dtsi create mode 100644 arch/arm/dts/at91sam9x25ek.dts create mode 100644 arch/arm/dts/at91sam9x35.dtsi create mode 100644 arch/arm/dts/at91sam9x35ek.dts create mode 100644 arch/arm/dts/at91sam9x5.dtsi create mode 100644 arch/arm/dts/at91sam9x5_can.dtsi create mode 100644 arch/arm/dts/at91sam9x5_isi.dtsi create mode 100644 arch/arm/dts/at91sam9x5_lcd.dtsi create mode 100644 arch/arm/dts/at91sam9x5_macb0.dtsi create mode 100644 arch/arm/dts/at91sam9x5_macb1.dtsi create mode 100644 arch/arm/dts/at91sam9x5_usart3.dtsi create mode 100644 arch/arm/dts/at91sam9x5cm.dtsi create mode 100644 arch/arm/dts/at91sam9x5dm.dtsi create mode 100644 arch/arm/dts/at91sam9x5ek.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 18db8c8f79..fce84b4e12 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -325,6 +325,13 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ + at91sam9g15ek.dtb \ + at91sam9g25ek.dtb \ + at91sam9g35ek.dtb \ + at91sam9x25ek.dtb \ + at91sam9x35ek.dtb + dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ at91-sama5d2_xplained.dtb diff --git a/arch/arm/dts/at91sam9g15.dtsi b/arch/arm/dts/at91sam9g15.dtsi new file mode 100644 index 0000000000..27de7dc0f0 --- /dev/null +++ b/arch/arm/dts/at91sam9g15.dtsi @@ -0,0 +1,29 @@ +/* + * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> + * + * Licensed under GPLv2. + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" + +/ { + model = "Atmel AT91SAM9G15 SoC"; + compatible = "atmel,at91sam9g15", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe0399f 0x00000000 /* pioA */ + 0x00040000 0x00047e3f 0x00000000 /* pioB */ + 0xfdffffff 0x00000000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g15ek.dts b/arch/arm/dts/at91sam9g15ek.dts new file mode 100644 index 0000000000..d1d2b400f1 --- /dev/null +++ b/arch/arm/dts/at91sam9g15ek.dts @@ -0,0 +1,41 @@ +/* + * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre <nicolas.ferre(a)atmel.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9g15.dtsi" +#include "at91sam9x5dm.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9G15-EK"; + compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + hlcdc: hlcdc@f8038000 { + status = "okay"; + }; + }; + }; + + backlight: backlight { + status = "okay"; + }; + + bl_reg: backlight_regulator { + status = "okay"; + }; + + panel: panel { + status = "okay"; + }; + + panel_reg: panel_regulator { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/at91sam9g25.dtsi b/arch/arm/dts/at91sam9g25.dtsi new file mode 100644 index 0000000000..a7da0dd0c9 --- /dev/null +++ b/arch/arm/dts/at91sam9g25.dtsi @@ -0,0 +1,31 @@ +/* + * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> + * + * Licensed under GPLv2. + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_isi.dtsi" +#include "at91sam9x5_usart3.dtsi" +#include "at91sam9x5_macb0.dtsi" + +/ { + model = "Atmel AT91SAM9G25 SoC"; + compatible = "atmel,at91sam9g25", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe0399f 0xc000001c /* pioA */ + 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */ + 0x80000000 0x07c0ffff 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g25ek.dts b/arch/arm/dts/at91sam9g25ek.dts new file mode 100644 index 0000000000..91a7177447 --- /dev/null +++ b/arch/arm/dts/at91sam9g25ek.dts @@ -0,0 +1,69 @@ +/* + * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre <nicolas.ferre(a)atmel.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9g25.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9G25-EK"; + compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + spi0: spi@f0000000 { + status = "disabled"; + }; + + mmc1: mmc@f000c000 { + status = "disabled"; + }; + + i2c0: i2c@f8010000 { + ov2640: camera@0x30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>; + clocks = <&pck0>; + clock-names = "xvclk"; + assigned-clocks = <&pck0>; + assigned-clock-rates = <25000000>; + status = "okay"; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; + }; + + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + + isi: isi@f8048000 { + status = "okay"; + port { + isi_0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g35.dtsi b/arch/arm/dts/at91sam9g35.dtsi new file mode 100644 index 0000000000..ff4115886f --- /dev/null +++ b/arch/arm/dts/at91sam9g35.dtsi @@ -0,0 +1,30 @@ +/* + * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> + * + * Licensed under GPLv2. + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" +#include "at91sam9x5_macb0.dtsi" + +/ { + model = "Atmel AT91SAM9G35 SoC"; + compatible = "atmel,at91sam9g35", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe0399f 0xc000000c /* pioA */ + 0x000406ff 0x00047e3f 0x00000000 /* pioB */ + 0xfdffffff 0x00000000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9g35ek.dts b/arch/arm/dts/at91sam9g35ek.dts new file mode 100644 index 0000000000..23ec8b13f3 --- /dev/null +++ b/arch/arm/dts/at91sam9g35ek.dts @@ -0,0 +1,46 @@ +/* + * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre <nicolas.ferre(a)atmel.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9g35.dtsi" +#include "at91sam9x5dm.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9G35-EK"; + compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + + hlcdc: hlcdc@f8038000 { + status = "okay"; + }; + }; + }; + + backlight: backlight { + status = "okay"; + }; + + bl_reg: backlight_regulator { + status = "okay"; + }; + + panel: panel { + status = "okay"; + }; + + panel_reg: panel_regulator { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/at91sam9x25.dtsi b/arch/arm/dts/at91sam9x25.dtsi new file mode 100644 index 0000000000..3c5fa33889 --- /dev/null +++ b/arch/arm/dts/at91sam9x25.dtsi @@ -0,0 +1,32 @@ +/* + * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> + * + * Licensed under GPLv2. + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_usart3.dtsi" +#include "at91sam9x5_macb0.dtsi" +#include "at91sam9x5_macb1.dtsi" +#include "at91sam9x5_can.dtsi" + +/ { + model = "Atmel AT91SAM9X25 SoC"; + compatible = "atmel,at91sam9x25", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe03fff 0xc000001c /* pioA */ + 0x0007ffff 0x00047e3f 0x00000000 /* pioB */ + 0x80000000 0xfffd0000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x25ek.dts b/arch/arm/dts/at91sam9x25ek.dts new file mode 100644 index 0000000000..494864836e --- /dev/null +++ b/arch/arm/dts/at91sam9x25ek.dts @@ -0,0 +1,30 @@ +/* + * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre <nicolas.ferre(a)atmel.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9x25.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9X25-EK"; + compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + + macb1: ethernet@f8030000 { + phy-mode = "rmii"; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x35.dtsi b/arch/arm/dts/at91sam9x35.dtsi new file mode 100644 index 0000000000..d9054e8167 --- /dev/null +++ b/arch/arm/dts/at91sam9x35.dtsi @@ -0,0 +1,31 @@ +/* + * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> + * + * Licensed under GPLv2. + */ + +#include "at91sam9x5.dtsi" +#include "at91sam9x5_lcd.dtsi" +#include "at91sam9x5_macb0.dtsi" +#include "at91sam9x5_can.dtsi" + +/ { + model = "Atmel AT91SAM9X35 SoC"; + compatible = "atmel,at91sam9x35", "atmel,at91sam9x5"; + + ahb { + apb { + pinctrl@fffff400 { + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe03fff 0xc000000c /* pioA */ + 0x000406ff 0x00047e3f 0x00000000 /* pioB */ + 0xfdffffff 0x00000000 0xb83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x35ek.dts b/arch/arm/dts/at91sam9x35ek.dts new file mode 100644 index 0000000000..fcb67180ea --- /dev/null +++ b/arch/arm/dts/at91sam9x35ek.dts @@ -0,0 +1,45 @@ +/* + * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre <nicolas.ferre(a)atmel.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "at91sam9x35.dtsi" +#include "at91sam9x5dm.dtsi" +#include "at91sam9x5ek.dtsi" + +/ { + model = "Atmel AT91SAM9X35-EK"; + compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + hlcdc: hlcdc@f8038000 { + status = "okay"; + }; + }; + }; + + backlight: backlight { + status = "okay"; + }; + + bl_reg: backlight_regulator { + status = "okay"; + }; + + panel: panel { + status = "okay"; + }; + + panel_reg: panel_regulator { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/at91sam9x5.dtsi b/arch/arm/dts/at91sam9x5.dtsi new file mode 100644 index 0000000000..a5f836a5ac --- /dev/null +++ b/arch/arm/dts/at91sam9x5.dtsi @@ -0,0 +1,1292 @@ +/* + * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC + * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, + * AT91SAM9X25, AT91SAM9X35 SoC + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre <nicolas.ferre(a)atmel.com> + * + * Licensed under GPLv2 or later. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/at91.h> + +/ { + model = "Atmel AT91SAM9x5 family SoC"; + compatible = "atmel,at91sam9x5"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + ssc0 = &ssc0; + pwm0 = &pwm0; + spi0 = &spi0; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + memory { + reg = <0x20000000 0x10000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + sram: sram@00300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x8000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <31>; + }; + + ramc0: ramc@ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + clocks = <&ddrck>; + clock-names = "ddrck"; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91sam9x5-pmc", "syscon"; + reg = <0xfffffc00 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; + clock-frequency = <12000000>; + clock-accuracy = <50000000>; + }; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; + clocks = <&main_rc_osc>, <&main_osc>; + }; + + plla: pllack@0 { + compatible = "atmel,at91rm9200-clk-pll"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <2000000 32000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <745000000 800000000 0 0 + 695000000 750000000 1 0 + 645000000 700000000 2 0 + 595000000 650000000 3 0 + 545000000 600000000 0 1 + 495000000 555000000 1 1 + 445000000 500000000 2 1 + 400000000 450000000 3 1>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_LOCKU>; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupts-extended = <&pmc AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <0 133333333>; + atmel,clk-divisors = <1 2 4 3>; + atmel,master-clk-have-div3-pres; + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: prog@0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: prog@1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + }; + + smd: smdclk { + compatible = "atmel,at91sam9x5-clk-smd"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck@2 { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + smdck: smdck@4 { + #clock-cells = <0>; + reg = <4>; + clocks = <&smd>; + }; + + uhpck: uhpck@6 { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck@7 { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0@8 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1@9 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + }; + + periphck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + pioAB_clk: pioAB_clk@2 { + #clock-cells = <0>; + reg = <2>; + }; + + pioCD_clk: pioCD_clk@3 { + #clock-cells = <0>; + reg = <3>; + }; + + smd_clk: smd_clk@4 { + #clock-cells = <0>; + reg = <4>; + }; + + usart0_clk: usart0_clk@5 { + #clock-cells = <0>; + reg = <5>; + }; + + usart1_clk: usart1_clk@6 { + #clock-cells = <0>; + reg = <6>; + }; + + usart2_clk: usart2_clk@7 { + #clock-cells = <0>; + reg = <7>; + }; + + twi0_clk: twi0_clk@9 { + reg = <9>; + #clock-cells = <0>; + }; + + twi1_clk: twi1_clk@10 { + #clock-cells = <0>; + reg = <10>; + }; + + twi2_clk: twi2_clk@11 { + #clock-cells = <0>; + reg = <11>; + }; + + mci0_clk: mci0_clk@12 { + #clock-cells = <0>; + reg = <12>; + }; + + spi0_clk: spi0_clk@13 { + #clock-cells = <0>; + reg = <13>; + }; + + spi1_clk: spi1_clk@14 { + #clock-cells = <0>; + reg = <14>; + }; + + uart0_clk: uart0_clk@15 { + #clock-cells = <0>; + reg = <15>; + }; + + uart1_clk: uart1_clk@16 { + #clock-cells = <0>; + reg = <16>; + }; + + tcb0_clk: tcb0_clk@17 { + #clock-cells = <0>; + reg = <17>; + }; + + pwm_clk: pwm_clk@18 { + #clock-cells = <0>; + reg = <18>; + }; + + adc_clk: adc_clk@19 { + #clock-cells = <0>; + reg = <19>; + }; + + dma0_clk: dma0_clk@20 { + #clock-cells = <0>; + reg = <20>; + }; + + dma1_clk: dma1_clk@21 { + #clock-cells = <0>; + reg = <21>; + }; + + uhphs_clk: uhphs_clk@22 { + #clock-cells = <0>; + reg = <22>; + }; + + udphs_clk: udphs_clk@23 { + #clock-cells = <0>; + reg = <23>; + }; + + mci1_clk: mci1_clk@26 { + #clock-cells = <0>; + reg = <26>; + }; + + ssc0_clk: ssc0_clk@28 { + #clock-cells = <0>; + reg = <28>; + }; + }; + }; + + rstc@fffffe00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; + }; + + shdwc@fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&mck>; + }; + + sckc@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc>, <&slow_osc>; + }; + }; + + tcb0: timer@f8008000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8008000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + tcb1: timer@f800c000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf800c000 0x100>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + dma0: dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; + }; + + dma1: dma-controller@ffffee00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffee00 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&dma1_clk>; + clock-names = "dma_clk"; + }; + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff400 0xfffff400 0x800>; + reg = <0xfffff400 0x200 /* pioA */ + 0xfffff600 0x200 /* pioB */ + 0xfffff800 0x200 /* pioC */ + 0xfffffa00 0x200 /* pioD */ + >; + + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */ + }; + + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = + <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ + }; + + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = + <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ + }; + + pinctrl_usart0_sck: usart0_sck-0 { + atmel,pins = + <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */ + }; + + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = + <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */ + }; + + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = + <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */ + }; + + pinctrl_usart1_sck: usart1_sck-0 { + atmel,pins = + <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ + }; + + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ + }; + + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = + <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ + }; + + pinctrl_usart2_sck: usart2_sck-0 { + atmel,pins = + <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */ + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */ + AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */ + AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */ + }; + }; + + nand { + pinctrl_nand: nand-0 { + atmel,pins = + <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */ + AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */ + AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */ + AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */ + AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */ + AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */ + AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */ + AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */ + AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */ + AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */ + AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */ + AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */ + AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */ + AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */ + }; + + pinctrl_nand_16bits: nand_16bits-0 { + atmel,pins = + <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */ + AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */ + AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */ + AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */ + AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */ + AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */ + AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */ + AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */ + }; + }; + + mmc0 { + pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { + atmel,pins = + <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ + }; + + pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { + atmel,pins = + <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ + }; + }; + + mmc1 { + pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { + atmel,pins = + <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */ + AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ + AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */ + }; + + pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { + atmel,pins = + <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */ + AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */ + AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx-0 { + atmel,pins = + <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ + AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ + AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ + }; + + pinctrl_ssc0_rx: ssc0_rx-0 { + atmel,pins = + <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ + AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ + AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ + AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ + AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */ + AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */ + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */ + AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */ + }; + }; + + i2c2 { + pinctrl_i2c2: i2c2-0 { + atmel,pins = + <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */ + AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */ + }; + }; + + i2c_gpio0 { + pinctrl_i2c_gpio0: i2c_gpio0-0 { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */ + AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */ + }; + }; + + i2c_gpio1 { + pinctrl_i2c_gpio1: i2c_gpio1-0 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */ + AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */ + }; + }; + + i2c_gpio2 { + pinctrl_i2c_gpio2: i2c_gpio2-0 { + atmel,pins = + <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */ + AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */ + }; + }; + + pwm0 { + pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { + atmel,pins = + <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { + atmel,pins = + <AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { + atmel,pins = + <AT91_PIOC 18 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { + atmel,pins = + <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { + atmel,pins = + <AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { + atmel,pins = + <AT91_PIOC 19 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { + atmel,pins = + <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { + atmel,pins = + <AT91_PIOC 20 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { + atmel,pins = + <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { + atmel,pins = + <AT91_PIOC 21 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + }; + + tcb0 { + pinctrl_tcb0_tclk0: tcb0_tclk0-0 { + atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk1: tcb0_tclk1-0 { + atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tclk2: tcb0_tclk2-0 { + atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa0: tcb0_tioa0-0 { + atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa1: tcb0_tioa1-0 { + atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tioa2: tcb0_tioa2-0 { + atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob0: tcb0_tiob0-0 { + atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob1: tcb0_tiob1-0 { + atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb0_tiob2: tcb0_tiob2-0 { + atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + tcb1 { + pinctrl_tcb1_tclk0: tcb1_tclk0-0 { + atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk1: tcb1_tclk1-0 { + atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tclk2: tcb1_tclk2-0 { + atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa0: tcb1_tioa0-0 { + atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa1: tcb1_tioa1-0 { + atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tioa2: tcb1_tioa2-0 { + atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob0: tcb1_tiob0-0 { + atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob1: tcb1_tiob1-0 { + atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + + pinctrl_tcb1_tiob2: tcb1_tiob2-0 { + atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; + }; + }; + }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <19>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + }; + + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <22>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + }; + + ssc0: ssc@f0010000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf0010000 0x4000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(14)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + mmc0: mmc@f0008000 { + compatible = "atmel,hsmci"; + reg = <0xf0008000 0x600>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmc1: mmc@f000c000 { + compatible = "atmel,hsmci"; + reg = <0xf000c000 0x600>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dbgu: serial@fffff200 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&mck>; + clock-names = "usart"; + status = "disabled"; + }; + + usart0: serial@f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>, + <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + i2c0: i2c@f8010000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8010000 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(8)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + i2c1: i2c@f8014000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8014000 0x100>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>, + <&dma1 1 AT91_DMA_CFG_PER_ID(6)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&twi1_clk>; + status = "disabled"; + }; + + i2c2: i2c@f8018000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8018000 0x100>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(10)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&twi2_clk>; + status = "disabled"; + }; + + uart0: serial@f8040000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8040000 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + uart1: serial@f8044000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8044000 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + adc0: adc@f804c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9x5-adc"; + reg = <0xf804c000 0x100>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&adc_clk>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-use-external-triggers; + atmel,adc-channels-used = <0xffff>; + atmel,adc-vref = <3300>; + atmel,adc-startup-time = <40>; + atmel,adc-sample-hold-time = <11>; + atmel,adc-res = <8 10>; + atmel,adc-res-names = "lowres", "highres"; + atmel,adc-use-res = "highres"; + + trigger0 { + trigger-name = "external-rising"; + trigger-value = <0x1>; + trigger-external; + }; + + trigger1 { + trigger-name = "external-falling"; + trigger-value = <0x2>; + trigger-external; + }; + + trigger2 { + trigger-name = "external-any"; + trigger-value = <0x3>; + trigger-external; + }; + + trigger3 { + trigger-name = "continuous"; + trigger-value = <0x6>; + }; + }; + + spi0: spi@f0000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0000000 0x100>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>, + <&dma0 1 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi1: spi@f0004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0004000 0x100>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>, + <&dma1 1 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + usb2: gadget@f803c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9g45-udc"; + reg = <0x00500000 0x80000 + 0xf803c000 0x400>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&utmi>, <&udphs_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + + ep@0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep@1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep@2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep@3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep@4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep@5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep@6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + }; + + watchdog@fffffe40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffe40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + rtc@fffffeb0 { + compatible = "atmel,at91sam9x5-rtc"; + reg = <0xfffffeb0 0x40>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + pwm0: pwm@f8034000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xf8034000 0x300>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; + clocks = <&pwm_clk>; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + nand0: nand@40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x10000000 + 0xffffe000 0x600 /* PMECC Registers */ + 0xffffe600 0x200 /* PMECC Error Location Registers */ + 0x00108000 0x18000 /* PMECC looup table in ROM code */ + >; + atmel,pmecc-lookup-table-offset = <0x0 0x8000>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + gpios = <&pioD 5 GPIO_ACTIVE_HIGH + &pioD 4 GPIO_ACTIVE_HIGH + 0 + >; + status = "disabled"; + }; + + usb0: ohci@00600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb1: ehci@00700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */ + &pioA 31 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio0>; + status = "disabled"; + }; + + i2c-gpio-1 { + compatible = "i2c-gpio"; + gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */ + &pioC 1 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio1>; + status = "disabled"; + }; + + i2c-gpio-2 { + compatible = "i2c-gpio"; + gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */ + &pioB 5 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/at91sam9x5_can.dtsi b/arch/arm/dts/at91sam9x5_can.dtsi new file mode 100644 index 0000000000..9727b771d1 --- /dev/null +++ b/arch/arm/dts/at91sam9x5_can.dtsi @@ -0,0 +1,71 @@ +/* + * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 + * Ethernet interface. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon(a)overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pmc: pmc@fffffc00 { + periphck { + can0_clk: can0_clk@29 { + #clock-cells = <0>; + reg = <29>; + }; + + can1_clk: can1_clk@30 { + #clock-cells = <0>; + reg = <30>; + }; + }; + }; + + can0: can@f8000000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8000000 0x300>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + clocks = <&can0_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + + can1: can@f8004000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8004000 0x300>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + clocks = <&can1_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + + pinctrl@fffff400 { + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0, conflicts with DRXD */ + AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX0, conflicts with DTXD */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1, conflicts with RXD1 */ + AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX1, conflicts with TXD1 */ + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5_isi.dtsi b/arch/arm/dts/at91sam9x5_isi.dtsi new file mode 100644 index 0000000000..2c5075f8c3 --- /dev/null +++ b/arch/arm/dts/at91sam9x5_isi.dtsi @@ -0,0 +1,72 @@ +/* + * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an + * Image Sensor Interface. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon(a)overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff400 { + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D0, conflicts with LCDDAT0 */ + AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D1, conflicts with LCDDAT1 */ + AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D2, conflicts with LCDDAT2 */ + AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D3, conflicts with LCDDAT3 */ + AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D4, conflicts with LCDDAT4 */ + AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D5, conflicts with LCDDAT5 */ + AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D6, conflicts with LCDDAT6 */ + AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D7, conflicts with LCDDAT7 */ + AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_PCK, conflicts with LCDDAT12 */ + AT91_PIOC 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_HSYNC, conflicts with LCDDAT14 */ + AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* ISI_VSYNC, conflicts with LCDDAT13 */ + }; + + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D8, conflicts with LCDDAT8 */ + AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with LCDDAT9 */ + }; + + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* ISI_D10, conflicts with LCDDAT10 */ + AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with LCDDAT11 */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + isi_clk: isi_clk@25 { + #clock-cells = <0>; + reg = <25>; + }; + }; + }; + + isi: isi@f8048000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf8048000 0x4000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&isi_clk>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5_lcd.dtsi b/arch/arm/dts/at91sam9x5_lcd.dtsi new file mode 100644 index 0000000000..41e87589fb --- /dev/null +++ b/arch/arm/dts/at91sam9x5_lcd.dtsi @@ -0,0 +1,165 @@ +/* + * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an + * LCD controller. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon(a)overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + hlcdc: hlcdc@f8038000 { + compatible = "atmel,at91sam9x5-hlcdc"; + reg = <0xf8038000 0x4000>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + + pinctrl@fffff400 { + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ + AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */ + AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ + AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ + }; + + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */ + }; + + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */ + }; + + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ + AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ + AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ + AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ + AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ + AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ + AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ + AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + lcdc_clk: lcdc_clk@25 { + #clock-cells = <0>; + reg = <25>; + }; + }; + + systemck { + lcdck: lcdck@3 { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5_macb0.dtsi b/arch/arm/dts/at91sam9x5_macb0.dtsi new file mode 100644 index 0000000000..1540e60232 --- /dev/null +++ b/arch/arm/dts/at91sam9x5_macb0.dtsi @@ -0,0 +1,67 @@ +/* + * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 + * Ethernet interface. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon(a)overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff400 { + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ + }; + + pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { + atmel,pins = + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */ + AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + macb0_clk: macb0_clk@24 { + #clock-cells = <0>; + reg = <24>; + }; + }; + }; + + macb0: ethernet@f802c000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5_macb1.dtsi b/arch/arm/dts/at91sam9x5_macb1.dtsi new file mode 100644 index 0000000000..be2eab4b9c --- /dev/null +++ b/arch/arm/dts/at91sam9x5_macb1.dtsi @@ -0,0 +1,55 @@ +/* + * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2 + * Ethernet interfaces. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon(a)overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff400 { + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */ + AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */ + AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */ + AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */ + AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */ + AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */ + AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */ + AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */ + AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */ + AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + macb1_clk: macb1_clk@27 { + #clock-cells = <0>; + reg = <27>; + }; + }; + }; + + macb1: ethernet@f8030000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xf8030000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + clocks = <&macb1_clk>, <&macb1_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5_usart3.dtsi b/arch/arm/dts/at91sam9x5_usart3.dtsi new file mode 100644 index 0000000000..5259219077 --- /dev/null +++ b/arch/arm/dts/at91sam9x5_usart3.dtsi @@ -0,0 +1,69 @@ +/* + * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with + * 4 USART. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon(a)overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + aliases { + serial4 = &usart3; + }; + + ahb { + apb { + pinctrl@fffff400 { + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */ + AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */ + }; + + pinctrl_usart3_rts: usart3_rts-0 { + atmel,pins = + <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ + }; + + pinctrl_usart3_cts: usart3_cts-0 { + atmel,pins = + <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ + }; + + pinctrl_usart3_sck: usart3_sck-0 { + atmel,pins = + <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + usart3_clk: usart3_clk@8 { + #clock-cells = <0>; + reg = <8>; + }; + }; + }; + + usart3: serial@f8028000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + clocks = <&usart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9x5cm.dtsi b/arch/arm/dts/at91sam9x5cm.dtsi new file mode 100644 index 0000000000..b098ad8cd9 --- /dev/null +++ b/arch/arm/dts/at91sam9x5cm.dtsi @@ -0,0 +1,100 @@ +/* + * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre <nicolas.ferre(a)atmel.com> + * + * Licensed under GPLv2 or later. + */ + +/ { + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + pinctrl@fffff400 { + 1wire_cm { + pinctrl_1wire_cm: 1wire_cm-0 { + atmel,pins = <AT91_PIOB 18 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB18 multidrive, conflicts with led */ + }; + }; + }; + + rtc@fffffeb0 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; /* Enable PMECC */ + atmel,pmecc-cap = <2>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0x80000>; + }; + + ubootenv@c0000 { + label = "U-Boot Env"; + reg = <0xc0000 0x140000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pb18 { + label = "pb18"; + gpios = <&pioB 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + pd21 { + label = "pd21"; + gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; + }; + }; + + 1wire_cm { + compatible = "w1-gpio"; + gpios = <&pioB 18 GPIO_ACTIVE_HIGH>; + linux,open-drain; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_1wire_cm>; + status = "okay"; + }; + +}; diff --git a/arch/arm/dts/at91sam9x5dm.dtsi b/arch/arm/dts/at91sam9x5dm.dtsi new file mode 100644 index 0000000000..34c089fe0b --- /dev/null +++ b/arch/arm/dts/at91sam9x5dm.dtsi @@ -0,0 +1,101 @@ +/* + * at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module + * + * Copyright (C) 2014 Atmel, + * 2014 Free Electrons + * + * Author: Boris Brezillon <boris.brezillon(a)free-electrons.com> + * + * Licensed under GPLv2 or later. + */ + +/ { + ahb { + apb { + i2c0: i2c@f8010000 { + qt1070: keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioA>; + interrupts = <7 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; + }; + }; + + hlcdc: hlcdc@f8038000 { + hlcdc-display-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; + + port@0 { + hlcdc_panel_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + adc0: adc@f804c000 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + pinctrl@fffff400 { + board { + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + }; + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&hlcdc_pwm 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <&bl_reg>; + status = "disabled"; + }; + + bl_reg: backlight_regulator { + compatible = "regulator-fixed"; + regulator-name = "backlight-power-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "disabled"; + }; + + panel: panel { + compatible = "foxlink,fl500wvr00-a0t", "simple-panel"; + backlight = <&backlight>; + power-supply = <&panel_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + }; + + panel_reg: panel_regulator { + compatible = "regulator-fixed"; + regulator-name = "panel-power-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/at91sam9x5ek.dtsi b/arch/arm/dts/at91sam9x5ek.dtsi new file mode 100644 index 0000000000..0f1fcd9c28 --- /dev/null +++ b/arch/arm/dts/at91sam9x5ek.dtsi @@ -0,0 +1,165 @@ +/* + * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre <nicolas.ferre(a)atmel.com> + * + * Licensed under GPLv2 or later. + */ +#include "at91sam9x5cm.dtsi" + +/ { + model = "Atmel AT91SAM9X5-EK"; + compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; + stdout-path = "serial0:115200n8"; + }; + + ahb { + apb { + mmc0: mmc@f0008000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; + }; + }; + + mmc1: mmc@f000c000 { + pinctrl-0 = < + &pinctrl_board_mmc1 + &pinctrl_mmc1_slot0_clk_cmd_dat0 + &pinctrl_mmc1_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + usart0: serial@f801c000 { + status = "okay"; + }; + + usb2: gadget@f803c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_board_usb2>; + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + i2c0: i2c@f8010000 { + status = "okay"; + + wm8731: wm8731@1a { + compatible = "wm8731"; + reg = <0x1a>; + }; + }; + + adc0: adc@f804c000 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + pinctrl@fffff400 { + camera_sensor { + pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 { + atmel,pins = + <AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_MCK */ + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + <AT91_PIOA 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + }; + + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */ + }; + }; + + mmc1 { + pinctrl_board_mmc1: mmc1-board { + atmel,pins = + <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD14 gpio CD pin pull up and deglitch */ + }; + }; + + usb2 { + pinctrl_board_usb2: usb2-board { + atmel,pins = + <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PB16 gpio vbus sense, deglitch */ + }; + }; + }; + + spi0: spi@f0000000 { + status = "okay"; + cs-gpios = <&pioA 14 0>, <0>, <0>, <0>; + spi_flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + + ssc0: ssc@f0010000 { + status = "okay"; + }; + }; + + usb0: ohci@00600000 { + status = "okay"; + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */ + &pioD 19 GPIO_ACTIVE_LOW + &pioD 20 GPIO_ACTIVE_LOW + >; + }; + + usb1: ehci@00700000 { + status = "okay"; + }; + }; + + sound { + compatible = "atmel,sam9x5-wm8731-audio"; + + atmel,model = "wm8731 @ AT91SAM9X5EK"; + + atmel,audio-routing = + "Headphone Jack", "RHPOUT", + "Headphone Jack", "LHPOUT", + "LLINEIN", "Line In Jack", + "RLINEIN", "Line In Jack"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8731>; + }; +}; -- 2.11.0

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[U-Boot] [PATCH v3 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D3
by Wenyou Yang 07 Feb '17

07 Feb '17

The purpose of the patchset is add the dts files for boards, sama5d3 Xplained board and sama5d3xek board. It is based on the patch set: [PATCH v4 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D4 http://lists.denx.de/pipermail/u-boot/2017-February/280471.html Changes in v3: - Rebase on the master branch on git://git.denx.de/u-boot-atmel.git commit: 0ff27d4a94637d4b1937c625d33212375bd118d9 Changes in v2: - Fix spi flash compatible using "spi-flash". Wenyou Yang (2): ARM: at91: dt: add dts files for sama5d3ek board ARM: at91: dt: add dts file for sama5d3 Xplained arch/arm/dts/Makefile | 7 + arch/arm/dts/at91-sama5d3_xplained.dts | 341 ++++++++ arch/arm/dts/sama5d3.dtsi | 1505 ++++++++++++++++++++++++++++++++ arch/arm/dts/sama5d31.dtsi | 16 + arch/arm/dts/sama5d31ek.dts | 52 ++ arch/arm/dts/sama5d33.dtsi | 14 + arch/arm/dts/sama5d33ek.dts | 45 + arch/arm/dts/sama5d34.dtsi | 16 + arch/arm/dts/sama5d34ek.dts | 62 ++ arch/arm/dts/sama5d35.dtsi | 18 + arch/arm/dts/sama5d35ek.dts | 55 ++ arch/arm/dts/sama5d36.dtsi | 20 + arch/arm/dts/sama5d36ek.dts | 57 ++ arch/arm/dts/sama5d36ek_cmp.dts | 55 ++ arch/arm/dts/sama5d3_can.dtsi | 74 ++ arch/arm/dts/sama5d3_emac.dtsi | 55 ++ arch/arm/dts/sama5d3_gmac.dtsi | 88 ++ arch/arm/dts/sama5d3_lcd.dtsi | 215 +++++ arch/arm/dts/sama5d3_mci2.dtsi | 59 ++ arch/arm/dts/sama5d3_tcb1.dtsi | 39 + arch/arm/dts/sama5d3_uart.dtsi | 79 ++ arch/arm/dts/sama5d3xcm.dtsi | 123 +++ arch/arm/dts/sama5d3xcm_cmp.dtsi | 166 ++++ arch/arm/dts/sama5d3xdm.dtsi | 41 + arch/arm/dts/sama5d3xmb.dtsi | 221 +++++ arch/arm/dts/sama5d3xmb_cmp.dtsi | 230 +++++ 26 files changed, 3653 insertions(+) create mode 100644 arch/arm/dts/at91-sama5d3_xplained.dts create mode 100644 arch/arm/dts/sama5d3.dtsi create mode 100644 arch/arm/dts/sama5d31.dtsi create mode 100644 arch/arm/dts/sama5d31ek.dts create mode 100644 arch/arm/dts/sama5d33.dtsi create mode 100644 arch/arm/dts/sama5d33ek.dts create mode 100644 arch/arm/dts/sama5d34.dtsi create mode 100644 arch/arm/dts/sama5d34ek.dts create mode 100644 arch/arm/dts/sama5d35.dtsi create mode 100644 arch/arm/dts/sama5d35ek.dts create mode 100644 arch/arm/dts/sama5d36.dtsi create mode 100644 arch/arm/dts/sama5d36ek.dts create mode 100644 arch/arm/dts/sama5d36ek_cmp.dts create mode 100644 arch/arm/dts/sama5d3_can.dtsi create mode 100644 arch/arm/dts/sama5d3_emac.dtsi create mode 100644 arch/arm/dts/sama5d3_gmac.dtsi create mode 100644 arch/arm/dts/sama5d3_lcd.dtsi create mode 100644 arch/arm/dts/sama5d3_mci2.dtsi create mode 100644 arch/arm/dts/sama5d3_tcb1.dtsi create mode 100644 arch/arm/dts/sama5d3_uart.dtsi create mode 100644 arch/arm/dts/sama5d3xcm.dtsi create mode 100644 arch/arm/dts/sama5d3xcm_cmp.dtsi create mode 100644 arch/arm/dts/sama5d3xdm.dtsi create mode 100644 arch/arm/dts/sama5d3xmb.dtsi create mode 100644 arch/arm/dts/sama5d3xmb_cmp.dtsi -- 2.11.0

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[U-Boot] [PATCH v2] armv8: fsl-lsch2: add workaround for erratum A-010635
by yuantian.tang＠nxp.com 07 Feb '17

07 Feb '17

From: Tang Yuantian <Yuantian.Tang(a)nxp.com> Read DMA operations causes CRC error on armv8 chassis 2 platforms due to the erratum A-010635. In order to support sata on these platforms, ECC needs to be disabled. Signed-off-by: Tang Yuantian <yuantian.tang(a)nxp.com> --- v2: - refine the commit message arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 9489f85..b54a937 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -233,10 +233,8 @@ int sata_init(void) { struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; -#ifdef CONFIG_ARCH_LS1046A /* Disable SATA ECC */ out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); -#endif out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v4 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D4
by Wenyou Yang 07 Feb '17

07 Feb '17

The purpose of the patchset is add the dts files for boards, sama5d4 Xplained board and sama5d4ek board. Changes in v4: - Rebase on the master branch on git://git.denx.de/u-boot-atmel.git commit: 0ff27d4a94637d4b1937c625d33212375bd118d9 Changes in v3: - Fix the compatible of spi flash, use "spi-flash". - Fix the compatible of spi flash, use "spi-flash". Changes in v2: - Remove unneeded the pinctrl node for cs pin of spi0. - Remove unneeded the pinctrl node for cs pin of spi0. Wenyou Yang (2): ARM: dts: at91: add dts files for sama5d4 Xplained ARM: dts: at91: add dts file for sama5d4ek arch/arm/dts/Makefile | 6 + arch/arm/dts/at91-sama5d4_xplained.dts | 279 +++++ arch/arm/dts/at91-sama5d4ek.dts | 334 ++++++ arch/arm/dts/sama5d4.dtsi | 1910 ++++++++++++++++++++++++++++++++ 4 files changed, 2529 insertions(+) create mode 100644 arch/arm/dts/at91-sama5d4_xplained.dts create mode 100644 arch/arm/dts/at91-sama5d4ek.dts create mode 100644 arch/arm/dts/sama5d4.dtsi -- 2.11.0

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[U-Boot] [PATCH v3 0/3] gpio: at91_gpio: Add option and clock support
by Wenyou Yang 07 Feb '17

07 Feb '17

The CONFIG_AT91_GPIO option is added in Kconfig to be used to select the AT91 PIO GPIO driver, and the clock is supported. Changes in v3: - Rebase on the master branch on git://git.denx.de/u-boot-atmel.git commit: 0ff27d4a94637d4b1937c625d33212375bd118d9 - Add Reviewed-by tag. Changes in v2: - Add Reviewed-by tag. Wenyou Yang (3): gpio: Kconfig: Add CONFIG_AT91_GPIO option gpio: at91_gpio: Add the device tree support gpio: at91_gpio: Add the clock support drivers/gpio/Kconfig | 13 +++++++++++++ drivers/gpio/at91_gpio.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) -- 2.11.0

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[U-Boot] [PATCH v3] x86: make LOAD_FROM_32_BIT visible for platforms
by Andy Shevchenko 07 Feb '17

07 Feb '17

This option is useful not only for development, but for the platforms where U-Boot is run from custom ROM bootloader. For example, Intel Edison is that board. Make this option visible that platforms can select it if needed. Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- - remove 'default n' - fix spelling in commit message arch/x86/Kconfig | 8 ++++++++ arch/x86/cpu/start.S | 12 ++---------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0884af22a7..07d0a6876b 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -109,6 +109,14 @@ config SYS_X86_START16 depends on X86_RESET_VECTOR default 0xfffff800 +config X86_LOAD_FROM_32_BIT + bool "Boot from a 32-bit program" + help + Define this to boot U-Boot from a 32-bit program which sets + the GDT differently. This can be used to boot directly from + any stage of coreboot, for example, bypassing the normal + payload-loading feature. + config BOARD_ROMSIZE_KB_512 bool config BOARD_ROMSIZE_KB_1024 diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index a5cba1cf2a..8de55a0af1 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -18,14 +18,6 @@ #include <generated/generic-asm-offsets.h> #include <generated/asm-offsets.h> -/* - * Define this to boot U-Boot from a 32-bit program which sets the GDT - * differently. This can be used to boot directly from any stage of coreboot, - * for example, bypassing the normal payload-loading feature. - * This is only useful for development. - */ -#undef LOAD_FROM_32_BIT - .section .text .code32 .globl _start @@ -76,7 +68,7 @@ _start: /* Save table pointer */ movl %ecx, %esi -#ifdef LOAD_FROM_32_BIT +#ifdef CONFIG_X86_LOAD_FROM_32_BIT lgdt gdt_ptr2 #endif @@ -233,7 +225,7 @@ multiboot_header: /* entry addr */ .long CONFIG_SYS_TEXT_BASE -#ifdef LOAD_FROM_32_BIT +#ifdef CONFIG_X86_LOAD_FROM_32_BIT /* * The following Global Descriptor Table is just enough to get us into * 'Flat Protected Mode' - It will be discarded as soon as the final -- 2.11.0

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[U-Boot] [PATCH 00/14] x86: qemu: Add 64-bit U-Boot support
by Bin Meng 07 Feb '17

07 Feb '17

This brings U-Boot x86 64-bit support on QEMU target. This series is available at u-boot-x86/qemu64-working for testing. Bin Meng (14): x86: qemu: Add missing DECLARE_GLOBAL_DATA_PTR in e820.c x86: Wrap print_ch() with config option x86: spl: Add weak arch_cpu_init_dm() x86: Compile irq.c for 64-bit x86: qemu: Hide arch_cpu_init() and print_cpuinfo() for U-Boot proper x86: qemu: Fix compiler warnings for 64-bit x86: qemu: Set up device tree for SPL x86: qemu: Mark ucode as optional for SPL in u-boot.dtsi tools: binman: Call correct init for Entry_u_boot_spl_with_ucode_ptr tools: binman: Handle optional microcode case in SPL image spl: Add a LF to the loading message x86: qemu: Add a text base for 64-bit U-Boot x86: qemu: Add build options for SPL x86: qemu: Add a config for 64-bit U-Boot arch/x86/cpu/Makefile | 2 +- arch/x86/cpu/irq.c | 6 +- arch/x86/cpu/qemu/e820.c | 2 + arch/x86/cpu/qemu/qemu.c | 7 ++- arch/x86/cpu/x86_64/cpu.c | 2 + arch/x86/dts/emulation-u-boot.dtsi | 6 ++ arch/x86/dts/qemu-x86_i440fx.dts | 4 ++ arch/x86/dts/qemu-x86_q35.dts | 4 ++ arch/x86/lib/spl.c | 5 ++ board/emulation/Kconfig | 7 +++ board/emulation/qemu-x86/Kconfig | 6 +- board/emulation/qemu-x86/MAINTAINERS | 7 +++ common/spl/spl.c | 2 +- configs/qemu-x86_64_defconfig | 80 +++++++++++++++++++++++++ include/configs/qemu-x86.h | 9 +++ tools/binman/etype/u_boot_spl_with_ucode_ptr.py | 2 +- tools/binman/etype/u_boot_ucode.py | 6 ++ 17 files changed, 146 insertions(+), 11 deletions(-) create mode 100644 configs/qemu-x86_64_defconfig -- 2.9.2

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[U-Boot] [PATCH v3 00/62] x86: Add initial support for 64-bit U-Boot
by Simon Glass 07 Feb '17

07 Feb '17

At present U-Boot runs entirely in 32-bit mode on x86, except for the initial switch from 16-bit mode. On 64-bit machines it is possible to run in 64-bit mode. This series starts the process of adding this support. The main benefit of 64-bit mode for a boot loader is direct access to all available memory. There are also more registers, but this makes very little difference. This feature is implemented by putting all of the 32-bit code in an SPL build. SPL then runs through all the init that has to be done in 32-bit mode, changes to 64-bit mode and then jumps to U-Boot proper. Typically the total code size increases slightly. For example, on link in 32-bit mode, U-Boot has around 480KB of code (admittedly with a large number of features enabled). In 64-bit mode, U-Boot falls to around 460KB, but SPL adds another 60KB, for a net increase of 40KB. Partly this is due to code duplication and partly it is due to the worse code density of 64-bit code on x86. Many major features are not implemented yet, for example: - SDRAM sizing - Booting linux - FSP support - EFI support - SCSI device init - Running video ROMs Still, this is a big step forward towards full 64-bit support. To enable it, select CONFIG_X86_RUN_64BIT. This series is available at u-boot-x86/64-working Changes in v3: - update iomux.c and usb_kbd.c also - Drop WIP tag as this patch is actually needed - Use tab instead of space in Kconfig help line - Fix s/32-bit init/16-bit init/ and expand the comment - Drop unused headers - Drop unused board_debug_uart_init function - Use call instead of callq - Move 'const' change into its own patch - Add new patch to use static const for the board_f/r init sequences - Add a TODO to board_init_r() regarding the use of the new_gd parameter - Mention the commit ID containing information about the need for reloc checks - Drop the pre-panic printf() of the relocation addresses - Update copyright year - Drop duplicate line in header commment - Add a comment about stack position to x86_spl_init() - Add a parameter to the use of the SPL_LOAD_IMAGE_METHOD() macro - Fix printf() warning in spl_board_load_image() - Drop blank line at end of arch/x86/cpu/x86_64/interrupts.c - Drop #include of debug_uart.h - Add a TODO to look at using a fixed register for gd on x86_64 - Expand the TODO about the necessary printch() call - Add a required debug_uart.h #include in this patch - Fix 'skipt' typo in the subject - Put dummy misc_init_r() and print_cpuinfo() functions into cpu.c - Drop duplicate comment line in header - Add a TODO indicating that booting 32- and 64-bit kernels should be supported - Expand pre-reloc malloc() size in this patch to prevent boot failure - Remove duplicate CONFIG_VIDEO_IVYBRIDGE_IGD in defconfig file - Drop the unnecessary defconfig changes for chromebook_link - Drop patch 'x86: Add basic support for U-Boot as a 64-bit EFI application' - Drop patch 'Mention the MRC region in the README' - Drop patch 'x86: link: Add build options for SPL' - Drop unnecessary defconfig options for chromebook_link64 - Avoid including helloworld.efi in the 64-bit U-Boot Changes in v2: - Show the error value in spl_spi_load_image() - Move table-related changes from a later patch - Rebase to mainline - Drop the write_smbios_table_wrapper() function - Drop change to gma.c - Output error code values in debug() statements - Fix cast in bd82x6x_video_probe() also - Fix cast in get_guid_hob_data() also - Move table-related changes to an earlier patch - Add the 'val' parameter to longjmp() - Drop patch 'video: Use ulong for video frame buffer address' - Add a new 64-bit link config instead of changing the existing one Simon Glass (62): console: Don't enable CONFIG-CONSOLE_MUX, etc. in SPL spl: spi: Add a debug message if loading fails spl: Makefile: Define SPL_ earlier spl: Allow CPU drivers to be used in SPL spl: Allow PCI drivers to be used in SPL spl: Allow RTC drivers to be used in SPL spl: Allow timer drivers to be used in SPL spl: Allow PCH drivers to be used in SPL spl: Don't create a BSS padding when it is separate x86: Use unsigned long for address in table generation x86: Update mpspec to build on 64-bit machines x86: ivybridge: Declare global data where it is used x86: ivybridge: Add more debugging for failures x86: ivybridge: Fix types for 64-bit compilation x86: dts: Mark serial as needed before relocation x86: fsp: Fix cast for 64-bit compilation x86: lib: Fix types and casts for 64-bit compilation x86: Add Kconfig options to build 64-bit U-Boot x86: Kconfig: Add location options for 16/32-bit init x86: Use X86_16BIT_INIT instead of X86_RESET_VECTOR x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR x86: ivybridge: Allow 32-bit init to move to SPL x86: Add 64-bit start-up code x86: board_f: Update init sequence for 64-bit startup board_f/r: Use static const for the init sequences x86: board_r: Set the global data pointer after relocation x86: Do relocation before clearing BSS x86: Refactor relocation to prepare for 64-bit x86: Add support for 64-bit relocation x86: Tidy up use of size_t in relocation x86: Add an SPL implementation x86: Move the i386 code into its own directory x86: Add cpu code for x86_64 x86: Support global_data on x86_64 x86: Fix up CONFIG_X86_64 check x86: Add a link script for 64-bit x86 x86: Add a link script for SPL x86: Add SPL build rules for start-up code x86: Fix up byteorder.h for x86_64 x86: Drop flag_is_changable() on x86_64 x86: Fix up type sizes for 64-bit x86: ivybridge: Skip SATA init in SPL x86: ivybridge: Provide a dummy SDRAM init for 64-bit x86: Don't try to run the VGA BIOS in 64-bit mode x86: Don't build call64 and setjmp on 64-bit x86: Don't build cpu files which are not supported on 64-bit x86: Don't build 32-bit efi files on x86_64 x86: Don't try to boot Linux from SPL x86: Drop interrupt support in 64-bit mode x86: Support jumping from SPL to U-Boot x86: Move pirq_routing_table to global_data x86: Move turbo_state to global_data x86: Change irq_already_routed to a local variable x86: Move call64 to the i386 directory x86: Move setjmp to the i386 directory x86: Add a dummy setjmp implementation for x86_64 x86: link: Add a text base for 64-bit U-Boot x86: link: Add SPL declarations to the binman image x86: link: Set up device tree for SPL x86: link: Add build options for SPL x86: Update compile/link flags to support 64-bit U-Boot x86: link: Add a config for 64-bit U-Boot Makefile | 7 +- arch/x86/Kconfig | 86 ++++ arch/x86/Makefile | 9 +- arch/x86/config.mk | 30 +- arch/x86/cpu/Makefile | 24 +- arch/x86/cpu/config.mk | 8 +- arch/x86/cpu/cpu.c | 504 -------------------- arch/x86/cpu/i386/Makefile | 9 + arch/x86/cpu/{ => i386}/call64.S | 3 + arch/x86/cpu/i386/cpu.c | 599 ++++++++++++++++++++++++ arch/x86/cpu/{interrupts.c => i386/interrupt.c} | 6 +- arch/x86/cpu/{ => i386}/setjmp.S | 0 arch/x86/cpu/intel_common/Makefile | 10 +- arch/x86/cpu/irq.c | 14 +- arch/x86/cpu/ivybridge/Makefile | 9 +- arch/x86/cpu/ivybridge/bd82x6x.c | 2 + arch/x86/cpu/ivybridge/cpu.c | 4 +- arch/x86/cpu/ivybridge/lpc.c | 2 + arch/x86/cpu/ivybridge/model_206ax.c | 2 + arch/x86/cpu/ivybridge/northbridge.c | 2 + arch/x86/cpu/ivybridge/sata.c | 4 +- arch/x86/cpu/ivybridge/sdram.c | 37 +- arch/x86/cpu/ivybridge/sdram_nop.c | 18 + arch/x86/cpu/start64.S | 28 ++ arch/x86/cpu/turbo.c | 8 +- arch/x86/cpu/u-boot-64.lds | 76 +++ arch/x86/cpu/u-boot-spl.lds | 74 +++ arch/x86/cpu/u-boot.lds | 2 +- arch/x86/cpu/x86_64/Makefile | 6 + arch/x86/cpu/x86_64/cpu.c | 71 +++ arch/x86/cpu/x86_64/interrupts.c | 29 ++ arch/x86/cpu/x86_64/setjmp.c | 20 + arch/x86/dts/chromebook_link.dts | 15 +- arch/x86/dts/serial.dtsi | 1 + arch/x86/dts/u-boot.dtsi | 19 + arch/x86/include/asm/acpi_table.h | 2 +- arch/x86/include/asm/byteorder.h | 17 +- arch/x86/include/asm/cpu.h | 12 + arch/x86/include/asm/fsp/fsp_hob.h | 4 +- arch/x86/include/asm/global_data.h | 9 +- arch/x86/include/asm/mp.h | 3 + arch/x86/include/asm/mpspec.h | 10 +- arch/x86/include/asm/posix_types.h | 5 + arch/x86/include/asm/sfi.h | 2 +- arch/x86/include/asm/spl.h | 8 + arch/x86/include/asm/tables.h | 2 +- arch/x86/include/asm/types.h | 5 + arch/x86/lib/Makefile | 11 + arch/x86/lib/acpi_table.c | 4 +- arch/x86/lib/bios.c | 4 +- arch/x86/lib/bootm.c | 7 + arch/x86/lib/init_helpers.c | 2 +- arch/x86/lib/interrupts.c | 5 + arch/x86/lib/mpspec.c | 14 +- arch/x86/lib/pinctrl_ich6.c | 2 +- arch/x86/lib/pirq_routing.c | 14 +- arch/x86/lib/relocate.c | 100 +++- arch/x86/lib/sfi.c | 6 +- arch/x86/lib/spl.c | 153 ++++++ arch/x86/lib/tables.c | 11 +- arch/x86/lib/zimage.c | 2 +- board/google/Kconfig | 7 + board/google/chromebook_link/Kconfig | 5 +- board/google/chromebook_link/MAINTAINERS | 7 + common/board_f.c | 16 +- common/board_r.c | 12 +- common/console.c | 30 +- common/iomux.c | 4 +- common/spl/Kconfig | 47 ++ common/spl/spl_spi.c | 5 +- common/usb_kbd.c | 6 +- configs/chromebook_link64_defconfig | 89 ++++ configs/chromebook_link_defconfig | 4 +- drivers/Makefile | 5 + drivers/misc/qfw.c | 4 +- drivers/pci/pci_rom.c | 2 +- drivers/video/ivybridge_igd.c | 6 +- include/configs/chromebook_link.h | 9 + include/smbios.h | 4 +- lib/smbios.c | 22 +- scripts/Makefile.spl | 18 +- 81 files changed, 1773 insertions(+), 681 deletions(-) create mode 100644 arch/x86/cpu/i386/Makefile rename arch/x86/cpu/{ => i386}/call64.S (98%) create mode 100644 arch/x86/cpu/i386/cpu.c rename arch/x86/cpu/{interrupts.c => i386/interrupt.c} (99%) rename arch/x86/cpu/{ => i386}/setjmp.S (100%) create mode 100644 arch/x86/cpu/ivybridge/sdram_nop.c create mode 100644 arch/x86/cpu/start64.S create mode 100644 arch/x86/cpu/u-boot-64.lds create mode 100644 arch/x86/cpu/u-boot-spl.lds create mode 100644 arch/x86/cpu/x86_64/Makefile create mode 100644 arch/x86/cpu/x86_64/cpu.c create mode 100644 arch/x86/cpu/x86_64/interrupts.c create mode 100644 arch/x86/cpu/x86_64/setjmp.c create mode 100644 arch/x86/include/asm/spl.h create mode 100644 arch/x86/lib/spl.c create mode 100644 configs/chromebook_link64_defconfig -- 2.11.0.483.g087da7b7c-goog

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