February 2017 - U-Boot

[U-Boot] [PATCH] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus
by Ashish Kumar 07 Feb '17

07 Feb '17

CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new CONFIG defination and move existing register space definaton of CCI-400 bus from from immap_lsch2 to fsl_immap, so that it can be used for both chasis 2 and chasis 3. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- README | 9 ++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 1 + .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 48 -------------------- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + include/fsl_immap.h | 51 ++++++++++++++++++++++ 7 files changed, 69 insertions(+), 48 deletions(-) diff --git a/README b/README index a95348a..f70ad49 100644 --- a/README +++ b/README @@ -315,6 +315,15 @@ Many of the options are named exactly as the corresponding Linux kernel configuration options. The intention is to make it easier to build a config tool - later. +- ARM Platform Bus Type(CCI): + CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which + provides full cache coherency between two clusters of multi-core + CPUs and I/O coherency for devices and I/O masters + + CONFIG_SYS_FSL_HAS_CCI400 + + Defined For SoC that has cache coherent interconnect + CCN-400 The following options need to be configured: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 47897f4..0ea43c6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -7,6 +7,7 @@ config ARCH_LS1012A select SYS_FSL_ERRATUM_A010315 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_FSL_HAS_CCI400 config ARCH_LS1043A bool @@ -26,6 +27,7 @@ config ARCH_LS1043A select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_FSL_HAS_CCI400 config ARCH_LS1046A bool @@ -44,6 +46,7 @@ config ARCH_LS1046A select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_FSL_HAS_CCI400 config ARCH_LS2080A bool @@ -184,6 +187,9 @@ config SYS_FSL_IFC_BANK_COUNT config SYS_FSL_HAS_DP_DDR bool +config SYS_FSL_HAS_CCI400 + bool + config SYS_FSL_SRDS_1 bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 335f225..a1ac4a0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -29,6 +29,7 @@ #ifdef CONFIG_SYS_FSL_DDR #include <fsl_ddr.h> #endif +#include <fsl_immap.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 9489f85..d64fe7b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <fsl_immap.h> #include <fsl_ifc.h> #include <ahci.h> #include <scsi.h> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8ad199f..5210b8c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -543,54 +543,6 @@ struct ccsr_serdes { u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ }; -#define CCI400_CTRLORD_TERM_BARRIER 0x00000008 -#define CCI400_CTRLORD_EN_BARRIER 0 -#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 -#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 -#define CCI400_SNOOP_REQ_EN 0x00000001 - -/* CCI-400 registers */ -struct ccsr_cci400 { - u32 ctrl_ord; /* Control Override */ - u32 spec_ctrl; /* Speculation Control */ - u32 secure_access; /* Secure Access */ - u32 status; /* Status */ - u32 impr_err; /* Imprecise Error */ - u8 res_14[0x100 - 0x14]; - u32 pmcr; /* Performance Monitor Control */ - u8 res_104[0xfd0 - 0x104]; - u32 pid[8]; /* Peripheral ID */ - u32 cid[4]; /* Component ID */ - struct { - u32 snoop_ctrl; /* Snoop Control */ - u32 sha_ord; /* Shareable Override */ - u8 res_1008[0x1100 - 0x1008]; - u32 rc_qos_ord; /* read channel QoS Value Override */ - u32 wc_qos_ord; /* read channel QoS Value Override */ - u8 res_1108[0x110c - 0x1108]; - u32 qos_ctrl; /* QoS Control */ - u32 max_ot; /* Max OT */ - u8 res_1114[0x1130 - 0x1114]; - u32 target_lat; /* Target Latency */ - u32 latency_regu; /* Latency Regulation */ - u32 qos_range; /* QoS Range */ - u8 res_113c[0x2000 - 0x113c]; - } slave[5]; /* Slave Interface */ - u8 res_6000[0x9004 - 0x6000]; - u32 cycle_counter; /* Cycle counter */ - u32 count_ctrl; /* Count Control */ - u32 overflow_status; /* Overflow Flag Status */ - u8 res_9010[0xa000 - 0x9010]; - struct { - u32 event_select; /* Event Select */ - u32 event_count; /* Event Count */ - u32 counter_ctrl; /* Counter Control */ - u32 overflow_status; /* Overflow Flag Status */ - u8 res_a010[0xb000 - 0xa010]; - } pcounter[4]; /* Performance Counter */ - u8 res_e004[0x10000 - 0xe004]; -}; - /* MMU 500 */ #define SMMU_SCR0 (SMMU_BASE + 0x0) #define SMMU_SCR1 (SMMU_BASE + 0x4) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 5ea9130..b0097b0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -10,6 +10,7 @@ #define __ARCH_FSL_LSCH3_IMMAP_H_ #define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x3090000) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 diff --git a/include/fsl_immap.h b/include/fsl_immap.h index b1c4fe7..4f5a19c 100644 --- a/include/fsl_immap.h +++ b/include/fsl_immap.h @@ -133,4 +133,55 @@ struct ccsr_ddr { u8 res_e5c[164]; u32 debug[64]; /* debug_1 to debug_64 */ }; + +#ifdef CONFIG_SYS_FSL_HAS_CCI400 +#define CCI400_CTRLORD_TERM_BARRIER 0x00000008 +#define CCI400_CTRLORD_EN_BARRIER 0 +#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 + +/* CCI-400 registers */ +struct ccsr_cci400 { + u32 ctrl_ord; /* Control Override */ + u32 spec_ctrl; /* Speculation Control */ + u32 secure_access; /* Secure Access */ + u32 status; /* Status */ + u32 impr_err; /* Imprecise Error */ + u8 res_14[0x100 - 0x14]; + u32 pmcr; /* Performance Monitor Control */ + u8 res_104[0xfd0 - 0x104]; + u32 pid[8]; /* Peripheral ID */ + u32 cid[4]; /* Component ID */ + struct { + u32 snoop_ctrl; /* Snoop Control */ + u32 sha_ord; /* Shareable Override */ + u8 res_1008[0x1100 - 0x1008]; + u32 rc_qos_ord; /* read channel QoS Value Override */ + u32 wc_qos_ord; /* read channel QoS Value Override */ + u8 res_1108[0x110c - 0x1108]; + u32 qos_ctrl; /* QoS Control */ + u32 max_ot; /* Max OT */ + u8 res_1114[0x1130 - 0x1114]; + u32 target_lat; /* Target Latency */ + u32 latency_regu; /* Latency Regulation */ + u32 qos_range; /* QoS Range */ + u8 res_113c[0x2000 - 0x113c]; + } slave[5]; /* Slave Interface */ + u8 res_6000[0x9004 - 0x6000]; + u32 cycle_counter; /* Cycle counter */ + u32 count_ctrl; /* Count Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_9010[0xa000 - 0x9010]; + struct { + u32 event_select; /* Event Select */ + u32 event_count; /* Event Count */ + u32 counter_ctrl; /* Counter Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_a010[0xb000 - 0xa010]; + } pcounter[4]; /* Performance Counter */ + u8 res_e004[0x10000 - 0xe004]; +}; +#endif + #endif /* __FSL_IMMAP_H */ -- 1.9.1

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[U-Boot] [PATCH] armv8: fsl-lsch3: Conditionally Remove errata a0009203 from lsch3 init
by Ashish Kumar 07 Feb '17

07 Feb '17

This i2c errata is only valid for ls2080 and ls2088 SoC Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 0ea43c6..d383cc9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -71,6 +71,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 + select SYS_FSL_ERRATUM_A009203 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F @@ -278,6 +279,9 @@ config SYS_FSL_SDHC_CLK_DIV clock, in another word SDHC_clk = Platform_clk / this_divider. endmenu +config SYS_FSL_ERRATUM_A009203 + bool + config SYS_FSL_ERRATUM_A008336 bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d64fe7b..1e95540 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -153,6 +153,7 @@ static void erratum_rcw_src(void) * This erratum requires setting glitch_en bit to enable * digital glitch filter to improve clock stability. */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009203 static void erratum_a009203(void) { u8 __iomem *ptr; @@ -179,6 +180,7 @@ static void erratum_a009203(void) #endif #endif } +#endif void bypass_smmu(void) { @@ -192,7 +194,9 @@ void fsl_lsch3_early_init_f(void) { erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009203 erratum_a009203(); +#endif erratum_a008514(); erratum_a008336(); #ifdef CONFIG_CHAIN_OF_TRUST -- 1.9.1

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[U-Boot] [PATCH] armv8: fsl-lsch3: Put TZASC configuration in hash define
by Ashish Kumar 07 Feb '17

07 Feb '17

Number of TZASC instances may vary across NXP SoCs. So put TZASC configuration under instance specific defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ++++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 24 +++++++++++++----------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index d383cc9..c1528e5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -61,6 +61,8 @@ config ARCH_LS2080A select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2 + select FSL_TZASC_1 + select FSL_TZASC_2 select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 select SYS_FSL_ERRATUM_A008514 @@ -200,6 +202,12 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool +config FSL_TZASC_1 + bool + +config FSL_TZASC_2 + bool + endmenu menu "Layerscape clock tree configuration" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index a2185f2..79d1637 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -229,38 +229,40 @@ ENTRY(lowlevel_init) * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just * placeholders. */ +#ifdef CONFIG_FSL_TZASC_1 ldr x1, =TZASC_GATE_KEEPER(0) ldr w0, [x1] /* Filter 0 Gate Keeper Register */ orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ str w0, [x1] - ldr x1, =TZASC_GATE_KEEPER(1) - ldr w0, [x1] /* Filter 0 Gate Keeper Register */ - orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ - str w0, [x1] - ldr x1, =TZASC_REGION_ATTRIBUTES_0(0) ldr w0, [x1] /* Region-0 Attributes Register */ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ str w0, [x1] + ldr x1, =TZASC_REGION_ID_ACCESS_0(0) + ldr w0, [x1] /* Region-0 Access Register */ + mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ + str w0, [x1] +#endif +#ifdef CONFIG_FSL_TZASC_2 + ldr x1, =TZASC_GATE_KEEPER(1) + ldr w0, [x1] /* Filter 0 Gate Keeper Register */ + orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ + str w0, [x1] + ldr x1, =TZASC_REGION_ATTRIBUTES_0(1) ldr w0, [x1] /* Region-1 Attributes Register */ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ str w0, [x1] - ldr x1, =TZASC_REGION_ID_ACCESS_0(0) - ldr w0, [x1] /* Region-0 Access Register */ - mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ - str w0, [x1] - ldr x1, =TZASC_REGION_ID_ACCESS_0(1) ldr w0, [x1] /* Region-1 Attributes Register */ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ str w0, [x1] - +#endif isb dsb sy #endif -- 1.9.1

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[U-Boot] latest u-boot on Technexion LS1021A-IOT v1.0
by Leon Brits 07 Feb '17

07 Feb '17

Hi all, I've compiled u-boot 2017.01 for the TechNexion LS1021A-IOT v1.0 but there is no output of the u-boot boot process. The serial port application does report that it is connected. I have a 700-28203 REV X2 / SCH-28203 REV B3 unit which shows, when booted with its default u-boot from 2014, as v1.0. The u-boot is working fine on the v2.0 unit. Can any body help me? Regards LJB

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[U-Boot] [PATCH v3 00/13] sunxi: Allwinner H5 and OrangePi PC2 support
by Andre Przywara 07 Feb '17

07 Feb '17

Hi, some small changes as requested by reviewers (many thanks for that!) Maxime, Jagan, given I get some ACKs or RBs on the remaining patches, is this good to go for 2017.03 still? Cheers, Andre. -------------------------- This series introduces support for the Allwinner H5 SoC with four Cortex-A53 cores. The SoC's peripherals are very similar to the H3, although the cores and the BROM/SRAM layout resembles the A64. The first 8 patches contain some fixes and refactoring, to make code sharing between the three mentioned SoCs easier. Patch 09/13 adds support for the H5 DRAM controller, by extending the already existing combined H3/A64 DRAM code. Patch 10/13 renames the existing CONFIG_MACH_SUN8I_H3 config symbol to let it be used by all peripheral code that can be shared between the H3 and H5. Patch 11/13 introduces the H5 SoC config option into Kconfig, which defines this shared symbol as well. Patch 12/13 adds an easy device tree, which actually uses the H3 .dtsi and overwrites nodes which are different. This is good enough for U-Boot, the DT will be changed anyway once we get the DT merged into the Linux kernel. The final patch then adds the defconfig for the OrangePi PC2 board. Since this board comes with soldered SPI flash, we enable support for it in the SPL. This has been tested by writing the SPI flash with some special sunxi-fel version. The BROM loaded and executed the SPL, which in turn loaded and executed U-Boot proper. Both parts are 64-bit only for now. Ethernet support is enabled, but fails at the moment since the EMAC driver does not support setting a GPIO to enable the external Gigabit PHY. At the moment this build suffers from the same problem as the A64: the ATF is missing, so Linux won't boot easily. With the RFC version of the SPL FIT extension series on the list, applied on top of this one this should now be solved. This series is on top of origin/master. Please have a look and let me know your opinion! Cheers, Andre. Changelog v2..v3: - Adding ACKs and RBs - remove not needed CONFIG_MACH_SUN50I_H5_64 - move ARM_CORTEX_CPU_IS_UP to arch/arm/Kconfig Changelog v1..v2: - Adding Maxime's ACKs - new patch 2 and 3 to rename CONFIG_TIMER_CLK_FREQ to COUNTER_FREQUENCY - renaming CONFIG symbol name for single core SoCs - fixing one checkpatch issue (some are left, though) - mentioning methodology and reason for missing data in DRAM driver - renaming shared config symbol to CONFIG_MACH_SUNXI_H3_H5 - updated to lastest origin/master Andre Przywara (13): sunxi: fix ACTLR.SMP assembly routine ARM: rename CONFIG_TIMER_CLK_FREQ to COUNTER_FREQUENCY fsl: ls102x: remove redundant GENERIC_TIMER_CLK sunxi: simplify ACTLR.SMP bit set #ifdef sunxi: configs: merge sun9i and sun50i SPL memory definitions sunxi: Kconfig: introduce CONFIG_SUNXI_HIGH_SRAM sunxi: provide ARMv8 mem_map for every ARM64 board SPI: SPL: sunxi: fix 64-bit build sunxi: DRAM: add Allwinner H5 support sunxi: prepare for sharing MACH_SUN8I_H3 config symbol sunxi: introduce Allwinner H5 config option sunxi: dts: add basic OrangePi PC 2 device tree file sunxi: configs: add basic OrangePi PC 2 defconfig arch/arm/Kconfig | 4 + arch/arm/cpu/armv7/ls102xa/psci.S | 2 +- arch/arm/cpu/armv7/ls102xa/timer.c | 2 +- arch/arm/cpu/armv7/nonsec_virt.S | 4 +- arch/arm/cpu/armv7/sunxi/psci.c | 2 +- arch/arm/dts/Makefile | 2 + arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 147 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 +- arch/arm/include/asm/arch-sunxi/cpu.h | 1 + arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 4 +- arch/arm/include/asm/arch-sunxi/dram.h | 2 +- arch/arm/include/asm/arch-sunxi/spl.h | 2 +- arch/arm/mach-sunxi/Makefile | 2 +- arch/arm/mach-sunxi/board.c | 12 +-- arch/arm/mach-sunxi/clock_sun6i.c | 6 +- arch/arm/mach-sunxi/cpu_info.c | 2 + arch/arm/mach-sunxi/dram_sun8i_h3.c | 97 ++++++++++++++--- arch/arm/mach-sunxi/usb_phy.c | 4 +- board/sunxi/Kconfig | 28 ++++- board/sunxi/MAINTAINERS | 5 + board/sunxi/board.c | 6 +- configs/orangepi_pc2_defconfig | 16 +++ drivers/mtd/spi/Kconfig | 2 +- drivers/mtd/spi/sunxi_spi_spl.c | 16 +-- drivers/net/sun8i_emac.c | 2 +- drivers/power/Kconfig | 4 +- drivers/usb/host/ehci-sunxi.c | 2 +- include/configs/exynos-common.h | 2 +- include/configs/ls1021aiot.h | 7 +- include/configs/ls1021aqds.h | 7 +- include/configs/ls1021atwr.h | 7 +- include/configs/mx7_common.h | 2 +- include/configs/sun50i.h | 1 - include/configs/sunxi-common.h | 24 ++--- scripts/config_whitelist.txt | 1 - 35 files changed, 332 insertions(+), 99 deletions(-) create mode 100644 arch/arm/dts/sun50i-h5-orangepi-pc2.dts create mode 100644 configs/orangepi_pc2_defconfig -- 2.8.2

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[U-Boot] [PATCH] arm: dts: dra7: add qspi register map for control module
by Jean-Jacques Hiblot 07 Feb '17

07 Feb '17

Add qspi control module register maps to device tree. This register map had been removed by error when syncing the DTS with the latest linux at the time (commit 7aa1a4087 "ARM: dts: dra7xx: sync DT with latest Linux"). Without this entry the driver do not support memory-mapped access and the data read from the SF is invalid. Signed-off-by: Jean-Jacques Hiblot <jjhiblot(a)ti.com> --- arch/arm/dts/dra7.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index 5570e30..46febc5 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -1302,9 +1302,10 @@ qspi: qspi@4b300000 { compatible = "ti,dra7xxx-qspi"; reg = <0x4b300000 0x100>, - <0x5c000000 0x4000000>; - reg-names = "qspi_base", "qspi_mmap"; - syscon-chipselects = <&scm_conf 0x558>; + <0x5c000000 0x4000000>, + <0x4a002558 0x4>; + reg-names = "qspi_base", "qspi_mmap", + "qspi_ctrlmod"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; -- 1.9.1

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[U-Boot] [PATCH] armv7m: Make reset_cpu() weak
by Phil Edworthy 07 Feb '17

07 Feb '17

Some devices/boards have their own way to reset the cpu. Signed-off-by: Phil Edworthy <phil.edworthy(a)renesas.com> --- arch/arm/cpu/armv7m/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index 58cde93..c3e4734 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -24,7 +24,7 @@ int cleanup_before_linux(void) /* * Perform the low-level reset. */ -void reset_cpu(ulong addr) +__weak void reset_cpu(ulong addr) { /* * Perform reset but keep priority group unchanged. -- 2.7.4

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[U-Boot] [PATCH v2 0/7] Add STMicroelectronics STiH410-B2260 board support
by patrice.chotard＠st.com 07 Feb '17

07 Feb '17

From: Patrice Chotard <patrice.chotard(a)st.com> This board is a 96board based on STiH410 SoC. This series adds basic support with serial, mmc and pinctrl support. v2: _ fix remarks from Jaechon Chung on SDHCI patch _ fix remarks from Antonio Borneo on board patch _ replace some macro by U-boot generic's one _ add missing maintainers in recipients Patrice Chotard (7): arm: Add support for STMicroelectronics STiH410 soc board: Add STMicroelectronics STiH410-B2260 support STiH410: Add STi serial driver STiH410: Add STi SDHCI driver STiH410: add STi pinctrl driver STiH410-B2260: add device tree STIH410-B2260: Add STiH410-B2260 defconfig arch/arm/Kconfig | 13 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/st-pincfg.h | 71 ++ arch/arm/dts/stih407-clock.dtsi | 326 ++++++ arch/arm/dts/stih407-family.dtsi | 977 +++++++++++++++ arch/arm/dts/stih407-pinctrl.dtsi | 1303 +++++++++++++++++++++ arch/arm/dts/stih410-b2260.dts | 225 ++++ arch/arm/dts/stih410-clock.dtsi | 347 ++++++ arch/arm/dts/stih410-pinctrl.dtsi | 34 + arch/arm/dts/stih410.dtsi | 454 +++++++ arch/arm/include/asm/arch-stih410/gpio.h | 20 + arch/arm/include/asm/arch-stih410/sdhci.h | 69 ++ arch/arm/include/asm/arch-stih410/sti.h | 20 + arch/arm/include/asm/arch-stih410/syscfg.h | 20 + arch/arm/mach-sti/Kconfig | 31 + arch/arm/mach-sti/Makefile | 8 + arch/arm/mach-sti/cpu.c | 16 + arch/arm/mach-sti/timer.c | 47 + board/st/stih410-b2260/Kconfig | 19 + board/st/stih410-b2260/MAINTAINERS | 6 + board/st/stih410-b2260/Makefile | 8 + board/st/stih410-b2260/board.c | 40 + configs/stih410-b2260_defconfig | 22 + drivers/mmc/Kconfig | 7 + drivers/mmc/Makefile | 1 + drivers/mmc/sti_sdhci.c | 140 +++ drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-sti.c | 315 +++++ drivers/serial/Kconfig | 7 + drivers/serial/Makefile | 1 + drivers/serial/serial_sti_asc.c | 219 ++++ include/configs/stih410-b2260.h | 59 + include/dm/platform_data/serial_sti_asc.h | 17 + include/dt-bindings/clock/stih407-clks.h | 90 ++ include/dt-bindings/clock/stih410-clks.h | 25 + include/dt-bindings/interrupt-controller/irq-st.h | 30 + include/dt-bindings/mfd/st-lpc.h | 16 + include/dt-bindings/reset/stih407-resets.h | 65 + 40 files changed, 5082 insertions(+) create mode 100644 arch/arm/dts/st-pincfg.h create mode 100644 arch/arm/dts/stih407-clock.dtsi create mode 100644 arch/arm/dts/stih407-family.dtsi create mode 100644 arch/arm/dts/stih407-pinctrl.dtsi create mode 100644 arch/arm/dts/stih410-b2260.dts create mode 100644 arch/arm/dts/stih410-clock.dtsi create mode 100644 arch/arm/dts/stih410-pinctrl.dtsi create mode 100644 arch/arm/dts/stih410.dtsi create mode 100644 arch/arm/include/asm/arch-stih410/gpio.h create mode 100644 arch/arm/include/asm/arch-stih410/sdhci.h create mode 100644 arch/arm/include/asm/arch-stih410/sti.h create mode 100644 arch/arm/include/asm/arch-stih410/syscfg.h create mode 100644 arch/arm/mach-sti/Kconfig create mode 100644 arch/arm/mach-sti/Makefile create mode 100644 arch/arm/mach-sti/cpu.c create mode 100644 arch/arm/mach-sti/timer.c create mode 100644 board/st/stih410-b2260/Kconfig create mode 100644 board/st/stih410-b2260/MAINTAINERS create mode 100644 board/st/stih410-b2260/Makefile create mode 100644 board/st/stih410-b2260/board.c create mode 100644 configs/stih410-b2260_defconfig create mode 100644 drivers/mmc/sti_sdhci.c create mode 100644 drivers/pinctrl/pinctrl-sti.c create mode 100644 drivers/serial/serial_sti_asc.c create mode 100644 include/configs/stih410-b2260.h create mode 100644 include/dm/platform_data/serial_sti_asc.h create mode 100644 include/dt-bindings/clock/stih407-clks.h create mode 100644 include/dt-bindings/clock/stih410-clks.h create mode 100644 include/dt-bindings/interrupt-controller/irq-st.h create mode 100644 include/dt-bindings/mfd/st-lpc.h create mode 100644 include/dt-bindings/reset/stih407-resets.h -- 1.9.1

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[U-Boot] [PATCH v1] Add single register pin controller driver
by Felix Brack 07 Feb '17

07 Feb '17

This patch adds a pin controller driver supporting devices using a single configuration register per pin. Signed-off-by: Felix Brack <fb(a)ltec.ch> --- drivers/pinctrl/Kconfig | 10 +++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-single.c | 138 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 149 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-single.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index efcb4c0..32bda65 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -175,6 +175,16 @@ config PIC32_PINCTRL by a device tree node which contains both GPIO defintion and pin control functions. +config PINCTRL_SINGLE + bool "Single register pin-control and pin-multiplex driver" + depends on DM + help + This enables pinctrl driver for systems using a single register for + pin configuration and multiplexing. TI's AM335X SoCs are examples of + such systems. + Depending on the platform make sure to also enable OF_TRANSLATE and + eventually SPL_OF_TRANSLATE to get correct address translations. + endif source "drivers/pinctrl/meson/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 512112a..f148f94 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/ +obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c new file mode 100644 index 0000000..f9e04f0 --- /dev/null +++ b/drivers/pinctrl/pinctrl-single.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack(a)eets.ch> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm/device.h> +#include <dm/pinctrl.h> +#include <libfdt.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct single_pdata { + fdt_addr_t base; /* first configuration register */ + int offset; /* index of last configuration register */ + u32 mask; /* configuration-value mask bits */ + int width; /* configuration register bit width */ +}; + +struct single_fdt_pin_cfg { + fdt32_t reg; + fdt32_t val; +}; + +static int single_configure_pins(struct udevice *dev, + const struct single_fdt_pin_cfg *pins, + int size) +{ + struct single_pdata *pdata = dev->platdata; + int count = size / sizeof(struct single_fdt_pin_cfg); + int n, reg; + u32 val; + + for (n = 0; n < count; n++) { + reg = fdt32_to_cpu(pins->reg); + if ((reg < 0) || (reg > pdata->offset)) { + dev_dbg(dev, " invalid register offset 0x%08x\n", reg); + pins++; + continue; + } + reg += pdata->base; + switch (pdata->width) { + case 32: { + val = readl(reg) & ~pdata->mask; + val |= fdt32_to_cpu(pins->val) & pdata->mask; + writel(val, reg); + dev_dbg(dev, " reg/val 0x%08x/0x%08x\n", + reg, val); + break; + } + default: { + dev_warn(dev, "unsupported register width %i\n", + pdata->width); + } + } + pins++; + } + return 0; +} + +static int single_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + const void *fdt = gd->fdt_blob; + const struct single_fdt_pin_cfg *prop; + int len; + int offset; + const char *name; + + offset = fdt_first_property_offset(fdt, periph->of_offset); + if (offset < 0) + return offset; + prop = fdt_getprop_by_offset(fdt, offset, &name, &len); + if (!prop) + return len; + + if (!strcmp(name, "pinctrl-single,pins")) { + dev_dbg(dev, "configuring pins for %s\n", periph->name); + if (len % sizeof(struct single_fdt_pin_cfg)) { + dev_dbg(dev, " invalid pin configuration in fdt\n"); + return -FDT_ERR_BADSTRUCTURE; + } + single_configure_pins(dev, prop, len); + } + + return 0; +} + +static int single_ofdata_to_platdata(struct udevice *dev) +{ + fdt_addr_t addr; + u32 of_reg[2]; + int res; + struct single_pdata *pdata = dev->platdata; + + pdata->width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "pinctrl-single,register-width", 0); + + res = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, + "reg", of_reg, 2); + if (res) + return res; + pdata->offset = of_reg[1] - pdata->width / 8; + + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) { + dev_dbg(dev, "no valid base register address\n"); + return -FDT_ERR_BADSTRUCTURE; + } + pdata->base = addr; + + pdata->mask = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "pinctrl-single,function-mask", + 0xffffffff); + return 0; +} + +const struct pinctrl_ops single_pinctrl_ops = { + .set_state_simple = single_set_state_simple, + .set_state = pinctrl_generic_set_state, +}; + +static const struct udevice_id single_pinctrl_match[] = { + { .compatible = "pinctrl-single" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(pcs_pinctrl) = { + .name = "single-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = single_pinctrl_match, + .ops = &single_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, + .platdata_auto_alloc_size = sizeof(struct single_pdata), + .ofdata_to_platdata = single_ofdata_to_platdata, +}; -- 2.7.4

2 2

[U-Boot] [PATCH v5] dm/mmc: gen_atmel_mci: Add driver model support for mci
by Wenyou Yang 07 Feb '17

07 Feb '17

Add the driver model support for Atmel mci while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v5: - Add the Reviewed-by tag. - Rebase Changes in v4: - Remove unneeded #ifdef CONFIG_DM_MMC. Changes in v3: - Use unified #ifdef CONFIG_DM_MMC #else...#endif, instead of #ifndef CONFIG_DM_MMC #else...#endif. Changes in v2: - Change the return type of atmel_mci_setup_cfg() from int to void. - Add comments on the features depends on the IP version. - Add the error handle path of clock. - Fix the missing use priv->bus_clk_rate. - Return from mmc_bind() directly, instead of checking its return. drivers/mmc/Kconfig | 9 +++ drivers/mmc/gen_atmel_mci.c | 161 +++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 169 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 0c07781115..70e3c8cf81 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -36,6 +36,15 @@ config DM_MMC_OPS if MMC +config GENERIC_ATMEL_MCI + bool "Atmel Multimedia Card Interface support" + depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91 + help + This enables support for Atmel High Speed Multimedia Card Interface + (HSMCI), which supports the MultiMedia Card (MMC) Specification V4.3, + the SD Memory Card Specification V2.0, the SDIO V2.0 specification + and CE-ATA V1.1. + config SPL_MMC_TINY bool "Tiny MMC framework in SPL" help diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 7dc4a5de74..0ca68c05be 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -10,6 +10,7 @@ */ #include <common.h> +#include <clk.h> #include <mmc.h> #include <part.h> #include <malloc.h> @@ -18,8 +19,11 @@ #include <asm/byteorder.h> #include <asm/arch/clk.h> #include <asm/arch/hardware.h> +#include <dm/device.h> #include "atmel_mci.h" +DECLARE_GLOBAL_DATA_PTR; + #ifndef CONFIG_SYS_MMC_CLK_OD # define CONFIG_SYS_MMC_CLK_OD 150000 #endif @@ -37,6 +41,10 @@ struct atmel_mci_priv { struct atmel_mci *mci; unsigned int initialized:1; unsigned int curr_clk; +#ifdef CONFIG_DM_MMC + struct mmc mmc; + ulong bus_clk_rate; +#endif }; /* Read Atmel MCI IP version */ @@ -58,11 +66,19 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg) } /* Setup for MCI Clock and Block Size */ +#ifdef CONFIG_DM_MMC +static void mci_set_mode(struct atmel_mci_priv *priv, u32 hz, u32 blklen) +{ + struct mmc *mmc = &priv->mmc; + u32 bus_hz = priv->bus_clk_rate; +#else static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) { struct atmel_mci_priv *priv = mmc->priv; - atmel_mci_t *mci = priv->mci; u32 bus_hz = get_mci_clk_rate(); +#endif + + atmel_mci_t *mci = priv->mci; u32 clkdiv = 255; unsigned int version = atmel_mci_get_version(mci); u32 clkodd = 0; @@ -202,10 +218,18 @@ io_fail: * Sends a command out on the bus and deals with the block data. * Takes the mmc pointer, a command pointer, and an optional data pointer. */ +#ifdef CONFIG_DM_MMC +static int atmel_mci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else static int mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct atmel_mci_priv *priv = mmc->priv; +#endif atmel_mci_t *mci = priv->mci; u32 cmdr; u32 error_flags = 0; @@ -335,17 +359,29 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) return 0; } +#ifdef CONFIG_DM_MMC +static int atmel_mci_set_ios(struct udevice *dev) +{ + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else /* Entered into mmc structure during driver init */ static int mci_set_ios(struct mmc *mmc) { struct atmel_mci_priv *priv = mmc->priv; +#endif + atmel_mci_t *mci = priv->mci; int bus_width = mmc->bus_width; unsigned int version = atmel_mci_get_version(mci); int busw; /* Set the clock speed */ +#ifdef CONFIG_DM_MMC + mci_set_mode(priv, mmc->clock, MMC_DEFAULT_BLKLEN); +#else mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN); +#endif /* * set the bus width and select slot for this interface @@ -374,10 +410,17 @@ static int mci_set_ios(struct mmc *mmc) return 0; } + +#ifdef CONFIG_DM_MMC +static int atmel_mci_hw_init(struct atmel_mci_priv *priv) +{ +#else /* Entered into mmc structure during driver init */ static int mci_init(struct mmc *mmc) { struct atmel_mci_priv *priv = mmc->priv; +#endif + atmel_mci_t *mci = priv->mci; /* Initialize controller */ @@ -392,11 +435,16 @@ static int mci_init(struct mmc *mmc) writel(~0UL, &mci->idr); /* Set default clocks and blocklen */ +#ifdef CONFIG_DM_MMC + mci_set_mode(priv, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); +#else mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); +#endif return 0; } +#ifndef CONFIG_DM_MMC static const struct mmc_ops atmel_mci_ops = { .send_cmd = mci_send_cmd, .set_ios = mci_set_ios, @@ -456,3 +504,114 @@ int atmel_mci_init(void *regs) return 0; } +#endif + +#ifdef CONFIG_DM_MMC +static const struct dm_mmc_ops atmel_mci_mmc_ops = { + .send_cmd = atmel_mci_send_cmd, + .set_ios = atmel_mci_set_ios, +}; + +static void atmel_mci_setup_cfg(struct atmel_mci_priv *priv) +{ + struct mmc_config *cfg; + u32 version; + + cfg = &priv->cfg; + cfg->name = "Atmel mci"; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + + /* + * If the version is above 3.0, the capabilities of the 8-bit + * bus width and high speed are supported. + */ + version = atmel_mci_get_version(priv->mci); + if ((version & 0xf00) >= 0x300) { + cfg->host_caps = MMC_MODE_8BIT | + MMC_MODE_HS | MMC_MODE_HS_52MHz; + } + + cfg->host_caps |= MMC_MODE_4BIT; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + cfg->f_min = priv->bus_clk_rate / (2 * 256); + cfg->f_max = priv->bus_clk_rate / 2; +} + +static int atmel_mci_enable_clk(struct udevice *dev) +{ + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct clk clk; + ulong clk_rate; + int ret = 0; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) { + ret = -EINVAL; + goto failed; + } + + ret = clk_enable(&clk); + if (ret) + goto failed; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) { + ret = -EINVAL; + goto failed; + } + + priv->bus_clk_rate = clk_rate; + +failed: + clk_free(&clk); + + return ret; +} + +static int atmel_mci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct mmc *mmc; + int ret; + + ret = atmel_mci_enable_clk(dev); + if (ret) + return ret; + + priv->mci = (struct atmel_mci *)dev_get_addr_ptr(dev); + + atmel_mci_setup_cfg(priv); + + mmc = &priv->mmc; + mmc->cfg = &priv->cfg; + mmc->dev = dev; + upriv->mmc = mmc; + + atmel_mci_hw_init(priv); + + return 0; +} + +static int atmel_mci_bind(struct udevice *dev) +{ + struct atmel_mci_priv *priv = dev_get_priv(dev); + + return mmc_bind(dev, &priv->mmc, &priv->cfg); +} + +static const struct udevice_id atmel_mci_ids[] = { + { .compatible = "atmel,hsmci" }, + { } +}; + +U_BOOT_DRIVER(atmel_mci) = { + .name = "atmel-mci", + .id = UCLASS_MMC, + .of_match = atmel_mci_ids, + .bind = atmel_mci_bind, + .probe = atmel_mci_probe, + .priv_auto_alloc_size = sizeof(struct atmel_mci_priv), + .ops = &atmel_mci_mmc_ops, +}; +#endif -- 2.11.0

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