February 2017 - U-Boot

[U-Boot] [PATCH 3/3] armv8: ls1088aqds: Add support of LS1088AQDS
by Ashish Kumar 15 Feb '17

15 Feb '17

This patch add support of LS1088AQDS platform. The LS1088A QorIQTM Development System (QDS) is a high-performance computing, evaluation, and development platform that supports the LS1088A QorIQ Architecture processor. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie(a)nxp.com> --- arch/arm/Kconfig | 11 + arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 21 + arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 2 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1088a-qds.dts | 70 +++ board/freescale/ls1088a/Kconfig | 16 + board/freescale/ls1088a/MAINTAINERS | 10 +- board/freescale/ls1088a/Makefile | 1 + board/freescale/ls1088a/ddr.c | 119 +--- board/freescale/ls1088a/ddr.h | 9 +- board/freescale/ls1088a/eth_ls1088aqds.c | 650 +++++++++++++++++++++ board/freescale/ls1088a/ls1088a.c | 106 +++- board/freescale/ls1088a/ls1088a_qixis.h | 5 + configs/ls1088aqds_qspi_defconfig | 27 + configs/ls1088ardb_qspi_defconfig | 6 - include/configs/ls1088a_common.h | 8 +- include/configs/ls1088aqds.h | 403 +++++++++++++ 19 files changed, 1321 insertions(+), 147 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1088a-qds.dts create mode 100644 board/freescale/ls1088a/eth_ls1088aqds.c create mode 100644 configs/ls1088aqds_qspi_defconfig create mode 100644 include/configs/ls1088aqds.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0c63dfe..435a8f8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -776,6 +776,17 @@ config TARGET_LS2080A_SIMU development platform that supports the QorIQ LS2080A Layerscape Architecture processor. +config TARGET_LS1088AQDS + bool "Support ls1088aqds" + select ARCH_LS1088A + select ARM64 + select ARMV8_MULTIENTRY + help + Support for NXP LS1088AQDS platform + The LS1088A Development System (QDS) is a high-performance + development platform that supports the QorIQ LS1088A + Layerscape Architecture processor. + config TARGET_LS2080AQDS bool "Support ls2080aqds" select ARCH_LS2080A diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 630bb78..b3565a5 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -88,7 +88,7 @@ config PSCI_RESET depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \ !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \ !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \ - !TARGET_LS1088ARDB && \ + !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \ !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a418c91..bf48918 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -229,6 +229,27 @@ config FSL_TZASC_1 config FSL_TZASC_2 bool +config SYS_FSL_ERRATUM_A008336 + bool + +config SYS_FSL_ERRATUM_A009801 + bool + +config SYS_FSL_ERRATUM_A009803 + bool + +config SYS_FSL_ERRATUM_A009942 + bool + +config SYS_FSL_ERRATUM_A010165 + bool + +config SYS_FSL_ERRATUM_A008511 + bool + +config SYS_FSL_ERRATUM_A008850 + bool + endmenu menu "Layerscape clock tree configuration" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c index 9f89bd0..9f5cdd5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c @@ -30,6 +30,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x20, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 2, 2 } }, {0x35, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 3 } }, {0x36, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 3 } }, + {0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } }, {} }; static struct serdes_config serdes2_cfg_tbl[] = { @@ -39,6 +40,7 @@ static struct serdes_config serdes2_cfg_tbl[] = { {0x0E, {PCIE1, PCIE1, PCIE2, SATA1 }, {7, 7, 6, 9 } }, {0x13, {PCIE1, PCIE1, PCIE3, PCIE3 }, {7, 7, 7, 7 } }, {0x14, {PCIE1, PCIE2, PCIE3, PCIE3 }, {5, 5, 7, 7 } }, + {0x3C, {NONE, PCIE2, NONE, PCIE3 }, {0, 5, 0, 6 } }, {} }; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 337d99d..f5a22ba 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -24,6 +24,7 @@ #ifdef CONFIG_CHAIN_OF_TRUST #include <fsl_validate.h> #endif +#include <fsl_immap.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5ac8ea3..2ec5c12 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -164,6 +164,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \ ls1021a-iot-duart.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-rdb.dtb \ + fsl-ls1088a-qds.dtb \ fsl-ls1088a-rdb.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts new file mode 100644 index 0000000..9b7bef4 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds.dts @@ -0,0 +1,70 @@ +/* + * NXP ls1088a QDS board device tree source + * + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "fsl-ls1088a.dtsi" + +/ { + model = "NXP Layerscape 1088a QDS Board"; + compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; + aliases { + spi0 = &qspi; + spi1 = &dspi; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <1000000>; /* input clock */ + }; + + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3500000>; + reg = <1>; + }; + + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3500000>; + reg = <2>; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fs512s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + + qflash1: s25fs512s@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <1>; + }; +}; diff --git a/board/freescale/ls1088a/Kconfig b/board/freescale/ls1088a/Kconfig index a4d8223..1ada661 100644 --- a/board/freescale/ls1088a/Kconfig +++ b/board/freescale/ls1088a/Kconfig @@ -1,3 +1,19 @@ +if TARGET_LS1088AQDS + +config SYS_BOARD + default "ls1088a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1088aqds" + +endif + if TARGET_LS1088ARDB config SYS_BOARD diff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS index 1abbf91..e1e6d4b 100644 --- a/board/freescale/ls1088a/MAINTAINERS +++ b/board/freescale/ls1088a/MAINTAINERS @@ -5,5 +5,11 @@ S: Maintained F: board/freescale/ls1088a/ F: include/configs/ls1088ardb.h F: configs/ls1088ardb_qspi_defconfig -F: configs/ls1088ardb_sdcard_defconfig -F: configs/ls1088ardb_sdcard_qspi_defconfig + +LS1088AQDS BOARD +M: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> +M: Ashish Kumar <Ashish.Kumar(a)nxp.com> +S: Maintained +F: board/freescale/ls1088a/ +F: include/configs/ls1088aqds.h +F: configs/ls1088aqds_qspi_defconfig diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile index e997cf1..bdcce9e 100644 --- a/board/freescale/ls1088a/Makefile +++ b/board/freescale/ls1088a/Makefile @@ -6,4 +6,5 @@ obj-y += ls1088a.o obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o +obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o obj-y += ddr.o diff --git a/board/freescale/ls1088a/ddr.c b/board/freescale/ls1088a/ddr.c index 8903ff0..61b6212 100644 --- a/board/freescale/ls1088a/ddr.c +++ b/board/freescale/ls1088a/ddr.c @@ -25,19 +25,14 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (!pdimm->n_ranks) return; - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - pbsp = udimms[ctrl_num]; + pbsp = udimms[0]; /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; @@ -63,51 +58,18 @@ void fsl_ddr_board_options(memctl_options_t *popts, panic("DIMM is not supported by this board"); } found: -#if defined(CONFIG_EMU) debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); -#else - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - - pdimm[0].dq_mapping[0] = 0x15; - pdimm[0].dq_mapping[1] = 0x35; - pdimm[0].dq_mapping[2] = 0x0b; - pdimm[0].dq_mapping[3] = 0x2c; - pdimm[0].dq_mapping[4] = 0x15; - pdimm[0].dq_mapping[5] = 0x35; - pdimm[0].dq_mapping[6] = 0x15; - pdimm[0].dq_mapping[7] = 0x35; - pdimm[0].dq_mapping[8] = 0xc; - pdimm[0].dq_mapping[9] = 0; - pdimm[0].dq_mapping[10] = 0; - pdimm[0].dq_mapping[11] = 0; - pdimm[0].dq_mapping[12] = 0; - pdimm[0].dq_mapping[13] = 0; - pdimm[0].dq_mapping[14] = 0; - pdimm[0].dq_mapping[15] = 0; - pdimm[0].dq_mapping[16] = 0; - pdimm[0].dq_mapping[17] = 0; - - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; + + popts->data_bus_width = 0; /* 64b data bus */ popts->otf_burst_chop_en = 0; popts->burst_length = DDR_BL8; - popts->bstopre = 0; /* enable auto precharge */ -#endif + popts->bstopre = 0; /* enable auto precharge */ - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ -#if defined(CONFIG_EMU) - popts->half_strength_driver_enable = 1; -#else popts->half_strength_driver_enable = 0; -#endif /* * Write leveling override */ @@ -122,10 +84,10 @@ found: /* Enable ZQ calibration */ popts->zq_en = 1; -#if defined(CONFIG_EMU) +#if defined(CONFIG_TARGET_LS1088AQDS) popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ + DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; #else popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) | @@ -134,73 +96,6 @@ found: popts->cpo_sample = 0x6d; } -#ifdef CONFIG_SYS_DDR_RAW_TIMING -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 4294967296u, - .capacity = 4294967296u, - .primary_sdram_width = 64, - .ec_sdram_width = 8, - .registered_dimm = 0, - .mirrored_dimm = 1, - .n_row_addr = 15, - .n_col_addr = 10, - .bank_addr_bits = 0, - .bank_group_bits = 2, - .edc_config = 2, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 938, - .tckmax_ps = 1500, - .caslat_x = 0x000DFA00, - .taa_ps = 13500, - .trcd_ps = 13500, - .trp_ps = 13500, - .tras_ps = 33000, - .trc_ps = 46500, - .trfc1_ps = 260000, - .trfc2_ps = 160000, - .trfc4_ps = 110000, - .tfaw_ps = 21000, - .trrds_ps = 3700, - .trrdl_ps = 5300, - .tccdl_ps = 5355, - .refresh_rate_ps = 7800000, - .dq_mapping[0] = 0x00, - .dq_mapping[1] = 0x00, - .dq_mapping[2] = 0x00, - .dq_mapping[3] = 0x00, - .dq_mapping[4] = 0x00, - .dq_mapping[5] = 0x00, - .dq_mapping[6] = 0x00, - .dq_mapping[7] = 0x00, - .dq_mapping[8] = 0x00, - .dq_mapping[9] = 0x00, - .dq_mapping[10] = 0x00, - .dq_mapping[11] = 0x00, - .dq_mapping[12] = 0x00, - .dq_mapping[13] = 0x00, - .dq_mapping[14] = 0x00, - .dq_mapping[15] = 0x00, - .dq_mapping[16] = 0x00, - .dq_mapping[17] = 0x00, - .dq_mapping_ors = 1, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - static const char dimm_model[] = "Fixed DDR on board"; - - if (dimm_number == 0) - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - - return 0; -} -#endif phys_size_t initdram(int board_type) { diff --git a/board/freescale/ls1088a/ddr.h b/board/freescale/ls1088a/ddr.h index 1658c22..bfc5dae 100644 --- a/board/freescale/ls1088a/ddr.h +++ b/board/freescale/ls1088a/ddr.h @@ -33,9 +33,14 @@ static const struct board_specific_parameters udimm0[] = { {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, {2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,}, {} +#elif defined(CONFIG_TARGET_LS1088AQDS) + {2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,}, + {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,}, + {} #else - {2, 2140, 0, 4, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, + {2, 2140, 0, 8, 4, 0x0, 0x0}, + {1, 2140, 0, 8, 4, 0x0, 0x0}, {} #endif }; diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c new file mode 100644 index 0000000..3e78ac7 --- /dev/null +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -0,0 +1,650 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/fsl_serdes.h> +#include <hwconfig.h> +#include <fsl_mdio.h> +#include <malloc.h> +#include <fm_eth.h> +#include <i2c.h> +#include <miiphy.h> +#include <fsl-mc/ldpaa_wriop.h> + +#include "../common/qixis.h" + +#include "ls1088a_qixis.h" + +#define MC_BOOT_ENV_VAR "mcinitcmd" + +#ifdef CONFIG_FSL_MC_ENET + +#define SFP_TX 0 + + /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks. + * Bank 1 -> Lanes A, B, C, D, + * Bank 2 -> Lanes A,B, C, D, + */ + + /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here + * means that the mapping must be determined dynamically, or that the lane + * maps to something other than a board slot. + */ + +static u8 lane_to_slot_fsm1[] = { + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs + * housed. + */ + +static int xqsgii_riser_phy_addr[] = { + XQSGMII_CARD_PHY1_PORT0_ADDR, + XQSGMII_CARD_PHY2_PORT0_ADDR, + XQSGMII_CARD_PHY3_PORT0_ADDR, + XQSGMII_CARD_PHY4_PORT0_ADDR, + XQSGMII_CARD_PHY3_PORT2_ADDR, + XQSGMII_CARD_PHY1_PORT2_ADDR, + XQSGMII_CARD_PHY4_PORT2_ADDR, + XQSGMII_CARD_PHY2_PORT2_ADDR, +}; + +static int sgmii_riser_phy_addr[] = { + SGMII_CARD_PORT1_PHY_ADDR, + SGMII_CARD_PORT2_PHY_ADDR, + SGMII_CARD_PORT3_PHY_ADDR, + SGMII_CARD_PORT4_PHY_ADDR, +}; + +/* Slot2 does not have EMI connections */ +#define EMI_NONE 0xFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 + +static const char * const mdio_names[] = { + "LS1088A_QDS_MDIO0", + "LS1088A_QDS_MDIO1", + "LS1088A_QDS_MDIO2", + DEFAULT_WRIOP_MDIO2_NAME, +}; + +struct ls1088a_qds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void sgmii_configure_repeater(int dpmac) +{ + struct mii_dev *bus; + uint8_t a = 0xf; + int i, j, ret; + unsigned short value; + const char *dev = "LS1088A_QDS_MDIO2"; + int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; + int i2c_phy_addr = 0; + int phy_addr = 0; + + uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; + uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; + uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + + /* Set I2c to Slot 1 */ + i2c_write(0x77, 0, 0, &a, 1); + + switch (dpmac) { + case 1: + i2c_phy_addr = i2c_addr[1]; + phy_addr = 4; + break; + case 2: + i2c_phy_addr = i2c_addr[0]; + phy_addr = 0; + break; + case 3: + i2c_phy_addr = i2c_addr[3]; + phy_addr = 0xc; + break; + case 7: + i2c_phy_addr = i2c_addr[2]; + phy_addr = 8; + break; + } + + /* Check the PHY status */ + ret = miiphy_set_current_dev(dev); + if (ret > 0) + goto error; + + bus = mdio_get_current_dev(); + debug("Reading from bus %s\n", bus->name); + + ret = miiphy_write(dev, phy_addr, 0x1f, 3); + if (ret > 0) + goto error; + + mdelay(10); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + if (ret > 0) + goto error; + + mdelay(10); + + if ((value & 0xfff) == 0x401) { + miiphy_write(dev, phy_addr, 0x1f, 0); + printf("DPMAC %d:PHY is ..... Configured\n", dpmac); + return; + } + + for (i = 0; i < 4; i++) { + for (j = 0; j < 4; j++) { + a = 0x18; + i2c_write(i2c_phy_addr, 6, 1, &a, 1); + a = 0x38; + i2c_write(i2c_phy_addr, 4, 1, &a, 1); + a = 0x4; + i2c_write(i2c_phy_addr, 8, 1, &a, 1); + + i2c_write(i2c_phy_addr, 0xf, 1, + &ch_a_eq[i], 1); + i2c_write(i2c_phy_addr, 0x11, 1, + &ch_a_ctl2[j], 1); + + i2c_write(i2c_phy_addr, 0x16, 1, + &ch_b_eq[i], 1); + i2c_write(i2c_phy_addr, 0x18, 1, + &ch_b_ctl2[j], 1); + + a = 0x14; + i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); + a = 0xb5; + i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); + a = 0x20; + i2c_write(i2c_phy_addr, 4, 1, &a, 1); + mdelay(100); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + if (ret > 0) + goto error; + + mdelay(100); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + if (ret > 0) + goto error; + + if ((value & 0xfff) == 0x401) { + printf("DPMAC %d :PHY is configured ", + dpmac); + printf("after setting repeater 0x%x\n", + value); + i = 5; + j = 5; + } else { + printf("DPMAC %d :PHY is failed to ", + dpmac); + printf("configure the repeater 0x%x\n", value); + } + } + } + miiphy_write(dev, phy_addr, 0x1f, 0); +error: + if (ret) + printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac); + return; +} + +static void qsgmii_configure_repeater(int dpmac) +{ + uint8_t a = 0xf; + int i, j; + int i2c_phy_addr = 0; + int phy_addr = 0; + int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; + + uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; + uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; + uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + + const char *dev = mdio_names[EMI1_SLOT1]; + int ret = 0; + unsigned short value; + + /* Set I2c to Slot 1 */ + i2c_write(0x77, 0, 0, &a, 1); + + switch (dpmac) { + case 7: + case 8: + case 9: + case 10: + i2c_phy_addr = i2c_addr[2]; + phy_addr = 8; + break; + + case 3: + case 4: + case 5: + case 6: + i2c_phy_addr = i2c_addr[3]; + phy_addr = 0xc; + break; + } + + /* Check the PHY status */ + ret = miiphy_set_current_dev(dev); + ret = miiphy_write(dev, phy_addr, 0x1f, 3); + mdelay(10); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + mdelay(10); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + mdelay(10); + if ((value & 0xf) == 0xf) { + miiphy_write(dev, phy_addr, 0x1f, 0); + printf("DPMAC %d :PHY is ..... Configured\n", dpmac); + return; + } + + for (i = 0; i < 4; i++) { + for (j = 0; j < 4; j++) { + a = 0x18; + i2c_write(i2c_phy_addr, 6, 1, &a, 1); + a = 0x38; + i2c_write(i2c_phy_addr, 4, 1, &a, 1); + a = 0x4; + i2c_write(i2c_phy_addr, 8, 1, &a, 1); + + i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); + i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); + + i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); + i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); + + a = 0x14; + i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); + a = 0xb5; + i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); + a = 0x20; + i2c_write(i2c_phy_addr, 4, 1, &a, 1); + mdelay(100); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + if (ret > 0) + goto error; + mdelay(1); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + if (ret > 0) + goto error; + mdelay(10); + if ((value & 0xf) == 0xf) { + miiphy_write(dev, phy_addr, 0x1f, 0); + printf("DPMAC %d :PHY is ..... Configured\n", + dpmac); + return; + } + } + } +error: + printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac); + return; +} + +static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name = ls1088a_qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +static void ls1088a_qds_enable_SFP_TX(u8 muxval) +{ + u8 brdcfg9; + + brdcfg9 = QIXIS_READ(brdcfg[9]); + brdcfg9 &= ~BRDCFG9_SFPTX_MASK; + brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT); + QIXIS_WRITE(brdcfg[9], brdcfg9); +} + +static void ls1088a_qds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + + if (muxval <= 5) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr, + int devad, int regnum) +{ + struct ls1088a_qds_mdio *priv = bus->priv; + + ls1088a_qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct ls1088a_qds_mdio *priv = bus->priv; + + ls1088a_qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int ls1088a_qds_mdio_reset(struct mii_dev *bus) +{ + struct ls1088a_qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval) +{ + struct ls1088a_qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate ls1088a_qds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate ls1088a_qds private data\n"); + free(bus); + return -1; + } + + bus->read = ls1088a_qds_mdio_read; + bus->write = ls1088a_qds_mdio_write; + bus->reset = ls1088a_qds_mdio_reset; + sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +/* + * Initialize the dpmac_info array. + * + */ +static void initialize_dpmac_to_slot(void) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 serdes1_prtcl, cfg; + + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & + FSL_CHASSIS3_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; + serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); + + switch (serdes1_prtcl) { + case 0x12: + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", + serdes1_prtcl); + lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1; + lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1; + lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1; + lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1; + break; + case 0x15: + case 0x1D: + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", + serdes1_prtcl); + lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1; + lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1; + lane_to_slot_fsm1[2] = EMI_NONE; + lane_to_slot_fsm1[3] = EMI_NONE; + break; + case 0x1E: + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", + serdes1_prtcl); + lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1; + lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1; + lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1; + lane_to_slot_fsm1[3] = EMI_NONE; + break; + case 0x3A: + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", + serdes1_prtcl); + lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1; + lane_to_slot_fsm1[1] = EMI_NONE; + lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1; + lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1; + break; + + default: + printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", + __func__, serdes1_prtcl); + break; + } +} + +void ls1088a_handle_phy_interface_sgmii(int dpmac_id) +{ + struct mii_dev *bus; + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 serdes1_prtcl, cfg; + + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & + FSL_CHASSIS3_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; + serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); + + int *riser_phy_addr; + char *env_hwconfig = getenv("hwconfig"); + + if (hwconfig_f("xqsgmii", env_hwconfig)) + riser_phy_addr = &xqsgii_riser_phy_addr[0]; + else + riser_phy_addr = &sgmii_riser_phy_addr[0]; + + switch (serdes1_prtcl) { + case 0x12: + case 0x15: + case 0x1E: + case 0x3A: + switch (dpmac_id) { + case 1: + wriop_set_phy_address(dpmac_id, riser_phy_addr[1]); + break; + case 2: + wriop_set_phy_address(dpmac_id, riser_phy_addr[0]); + break; + case 3: + wriop_set_phy_address(dpmac_id, riser_phy_addr[3]); + break; + case 7: + wriop_set_phy_address(dpmac_id, riser_phy_addr[2]); + break; + default: + printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id); + break; + } + break; + default: + printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", + __func__, serdes1_prtcl); + return; + } + dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; + bus = mii_dev_for_muxval(EMI1_SLOT1); + wriop_set_mdio(dpmac_id, bus); +} + +void ls1088a_handle_phy_interface_qsgmii(int dpmac_id) +{ + struct mii_dev *bus; + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 serdes1_prtcl, cfg; + + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & + FSL_CHASSIS3_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; + serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); + + switch (serdes1_prtcl) { + case 0x1D: + case 0x1E: + switch (dpmac_id) { + case 3: + case 4: + case 5: + case 6: + wriop_set_phy_address(dpmac_id, dpmac_id + 9); + break; + case 7: + case 8: + case 9: + case 10: + wriop_set_phy_address(dpmac_id, dpmac_id + 1); + break; + } + + dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; + bus = mii_dev_for_muxval(EMI1_SLOT1); + wriop_set_mdio(dpmac_id, bus); + break; + default: + printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", + serdes1_prtcl); + break; + } +} + +void ls1088a_handle_phy_interface_xsgmii(int i) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 serdes1_prtcl, cfg; + + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & + FSL_CHASSIS3_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; + serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg); + + switch (serdes1_prtcl) { + case 0x15: + case 0x1D: + case 0x1E: + wriop_set_phy_address(i, i + 26); + ls1088a_qds_enable_SFP_TX(SFP_TX); + break; + default: + printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", + serdes1_prtcl); + break; + } +} +#endif + +int board_eth_init(bd_t *bis) +{ + int error = 0, i; + char *mc_boot_env_var; +#ifdef CONFIG_FSL_MC_ENET + struct memac_mdio_info *memac_mdio0_info; + char *env_hwconfig = getenv("hwconfig"); + + initialize_dpmac_to_slot(); + + memac_mdio0_info = (struct memac_mdio_info *)malloc( + sizeof(struct memac_mdio_info)); + memac_mdio0_info->regs = + (struct memac_mdio_controller *) + CONFIG_SYS_FSL_WRIOP1_MDIO1; + memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME; + + /* Register the real MDIO1 bus */ + fm_memac_mdio_init(bis, memac_mdio0_info); + + /* Register the muxing front-ends to the MDIO buses */ + ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1); + ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2); + ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1); + + for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { + switch (wriop_get_enet_if(i)) { + case PHY_INTERFACE_MODE_QSGMII: + ls1088a_handle_phy_interface_qsgmii(i); + break; + case PHY_INTERFACE_MODE_SGMII: + ls1088a_handle_phy_interface_sgmii(i); + break; + case PHY_INTERFACE_MODE_XGMII: + ls1088a_handle_phy_interface_xsgmii(i); + break; + default: + break; + + if (i == 16) + i = NUM_WRIOP_PORTS; + } + } + + mc_boot_env_var = getenv(MC_BOOT_ENV_VAR); + if (mc_boot_env_var) + run_command_list(mc_boot_env_var, -1, 0); + error = cpu_eth_init(bis); + + if (hwconfig_f("xqsgmii", env_hwconfig)) { + for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { + switch (wriop_get_enet_if(i)) { + case PHY_INTERFACE_MODE_QSGMII: + qsgmii_configure_repeater(i); + break; + case PHY_INTERFACE_MODE_SGMII: + sgmii_configure_repeater(i); + break; + default: + break; + } + + if (i == 16) + i = NUM_WRIOP_PORTS; + } + } +#endif + error = pci_eth_init(bis); + return error; +} diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index b3ade52..0c8c2a5 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -49,11 +49,18 @@ int checkboard(void) "100 separate SSCG"}; int clock; +#ifdef CONFIG_TARGET_LS1088AQDS + printf("Board: LS1088A-QDS, "); +#else printf("Board: LS1088A-RDB, "); - +#endif sw = QIXIS_READ(arch); printf("Board Arch: V%d, ", sw >> 4); +#ifdef CONFIG_TARGET_LS1088AQDS printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); +#else + printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); +#endif memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); @@ -64,7 +71,27 @@ int checkboard(void) puts("SD card\n"); #endif switch (sw) { +#ifdef CONFIG_TARGET_LS1088AQDS case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + printf("vBank: %d\n", sw); + break; + case 8: + puts("PromJet\n"); + break; + case 15: + puts("IFCCard\n"); + break; + case 14: +#else + case 0: +#endif puts("QSPI:"); sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; @@ -81,11 +108,15 @@ int checkboard(void) break; } +#ifdef CONFIG_TARGET_LS1088AQDS printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); /* the timestamp string contains "\n" at the end */ printf(" on %s", qixis_read_time(buf)); +#else + printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); +#endif /* * Display the actual SERDES reference clocks as configured by the @@ -113,9 +144,13 @@ int checkboard(void) bool if_board_diff_clk(void) { +#ifdef CONFIG_TARGET_LS1088AQDS + u8 diff_conf = QIXIS_READ(brdcfg[11]); + return diff_conf & 0x40; +#else u8 diff_conf = QIXIS_READ(dutcfg[11]); - return diff_conf & 0x80; +#endif } unsigned long get_board_sys_clk(void) @@ -177,7 +212,7 @@ void board_retimer_init(void) { u8 reg; - /* Retimer is connected to I2C1_CH7_CH5 */ + /* Retimer is connected to I2C1_CH5 */ select_i2c_ch_pca9547(I2C_MUX_CH5); /* Access to Control/Shared register */ @@ -197,26 +232,10 @@ void board_retimer_init(void) reg |= 0x4; i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1); - /* Enable override divider select and Enable Override Output Mux */ - i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1); - reg |= 0x24; - i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1); - - /* Select VCO Divider to full rate (000) */ - i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1); - reg &= 0x8f; - i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1); - - /* Selects active PFD MUX Input as Re-timed Data (001) */ - i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1); - reg &= 0x3f; - reg |= 0x20; - i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1); - /* Set data rate as 10.3125 Gbps */ - reg = 0x0; + reg = 0x90; i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1); - reg = 0xb0; + reg = 0xb3; i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1); reg = 0x90; i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1); @@ -225,6 +244,51 @@ void board_retimer_init(void) reg = 0xcd; i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1); + /* Select VCO Divider to full rate (000) */ + i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1); + reg &= 0x0f; + reg |= 0x70; + i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1); + +#ifdef CONFIG_TARGET_LS1088AQDS + /* Retimer is connected to I2C1_CH5 */ + select_i2c_ch_pca9547(I2C_MUX_CH5); + + /* Access to Control/Shared register */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1); + + /* Read device revision and ID */ + i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast. All writes target all channel register sets */ + reg = 0x0c; + i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1); + + /* Reset Channel Registers */ + i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1); + reg |= 0x4; + i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x90; + i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1); + reg = 0xb3; + i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1); + reg = 0x90; + i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1); + reg = 0xb3; + i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1); + reg = 0xcd; + i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1); + + /* Select VCO Divider to full rate (000) */ + i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1); + reg &= 0x0f; + reg |= 0x70; + i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1); +#endif /*return the default channel*/ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); } diff --git a/board/freescale/ls1088a/ls1088a_qixis.h b/board/freescale/ls1088a/ls1088a_qixis.h index 9757d1b..4790461 100644 --- a/board/freescale/ls1088a/ls1088a_qixis.h +++ b/board/freescale/ls1088a/ls1088a_qixis.h @@ -31,4 +31,9 @@ #define QIXIS_SDCLK1_165 0x2 #define QIXIS_SDCLK1_100_SP 0x3 +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 +#define BRDCFG9_SFPTX_MASK 0x10 +#define BRDCFG9_SFPTX_SHIFT 4 + #endif diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig new file mode 100644 index 0000000..3511d92 --- /dev/null +++ b/configs/ls1088aqds_qspi_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1088AQDS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y + +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 223d581..a0559a7 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -9,19 +9,13 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT" -CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y -CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 5f976b8..f882d6a 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -33,9 +33,6 @@ #define CONFIG_SPI_FLASH_BAR #define CONFIG_SKIP_LOWLEVEL_INIT -/* Flat Device Tree Definitions */ -/* #define CONFIG_OF_LIBFDT */ - #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ #define CONFIG_VERY_BIG_RAM @@ -140,6 +137,11 @@ unsigned long long get_qixis_addr(void); /* Command line configuration */ #define CONFIG_CMD_ENV +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h new file mode 100644 index 0000000..b1189ea --- /dev/null +++ b/include/configs/ls1088aqds.h @@ -0,0 +1,403 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1088A_QDS_H +#define __LS1088A_QDS_H + +#include "ls1088a_common.h" + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_DISPLAY_BOARDINFO_LATE +#else +#define CONFIG_DISPLAY_BOARDINFO +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET (2 * 1024 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x20000 +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_QIXIS_I2C_ACCESS +#define SYS_NO_FLASH +#define CONFIG_SYS_I2C_EARLY_INIT /* swap get_board_sys_clk else part here*/ +#undef CONFIG_CMD_IMLS +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#else +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#endif + +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +#define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 + + +/* + * IFC Definitions + */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) + +#define CONFIG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#ifndef SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ + CONFIG_SYS_FLASH_BASE + 0x40000000} +#endif +#endif + +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_FSL_QIXIS +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_QMAP_MASK 0xe0 +#define QIXIS_QMAP_SHIFT 5 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x0e +#define QIXIS_LBMAP_ALTBANK 0x2e +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_SD_QSPI 0x0e +#define QIXIS_LBMAP_QSPI 0x0e +#define QIXIS_RCW_SRC_SD 0x40 +#define QIXIS_RCW_SRC_QSPI 0x62 +#define QIXIS_RST_CTL_RESET 0x41 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_RST_FORCE_MEM 0x01 +#define QIXIS_STAT_PRES1 0xb +#define QIXIS_SDID_MASK 0x07 +#define QIXIS_ESDHC_NO_ADAPTER 0x7 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) + +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) +#if defined(CONFIG_QSPI_BOOT) +#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) +#else +#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) +#endif +/* QIXIS Timing parameters*/ +#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0x3E)) +#define SYS_FPGA_CS_FTIM3 0x0 + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL +#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY +#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3 +#endif + +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 +#define I2C_RETIMER_ADDR2 0x19 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH5 0xD + +/* +* RTC configuration +*/ +#define RTC +#define CONFIG_RTC_PCF8563 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CONFIG_CMD_DATE + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* QSPI device */ +#if defined(CONFIG_QSPI_BOOT) +#define CONFIG_FSL_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define FSL_QSPI_FLASH_SIZE (1 << 26) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SYS_FSL_QSPI_AHB +#endif + +#ifdef CONFIG_FSL_DSPI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_EON +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 +#endif +#endif + +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_FSL_MEMAC + +/* MMC */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ + QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) + +/* Initial environment variables */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x90100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x1100000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "mcinitcmd=sf probe 0:0;sf read 0x80000000 0x300000 0x100000;" \ + "sf read 0x80100000 0x800000 0x100000;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" \ + "mcmemsize=0x70000000 \0" + +#ifdef CONFIG_FSL_MC_ENET +#define CONFIG_FSL_MEMAC +#define CONFIG_PHYLIB +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_TERANETICS +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1d +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F + +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe +#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "DPMAC1@xgmii" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#endif + +#undef CONFIG_CMDLINE_EDITING +#include <config_distro_defaults.h> +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) +#include <config_distro_bootcmd.h> + +#include <asm/fsl_secure_boot.h> + +#endif /* __LS1088A_QDS_H */ -- 1.9.1

1 0

[U-Boot] [PATCH v2 1/6] arm: am57xx: reintroduce the CONFIG_AM57XX symbol
by Uri Mashiach 15 Feb '17

15 Feb '17

The SOC family symbol CONFIG_AM57XX was removed by the commit 3891a54: "ARM: DRA7x/AM57xx: Get rid of CONFIG_AM57XX". The symbol is needed by the XHCI OMAP USB driver. Without the symbol all the AM57x targets symbols should be ored in the ifdef'ery. Signed-off-by: Uri Mashiach <uri.mashiach(a)compulab.co.il> --- V1 -> V2: Replace the commit "fix XHCI registers base address". include/configs/am57xx_evm.h | 1 + include/configs/cl-som-am57x.h | 1 + include/linux/usb/xhci-omap.h | 2 +- scripts/config_whitelist.txt | 1 + 4 files changed, 4 insertions(+), 1 deletion(-) diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 3d8b996..2896628 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -15,6 +15,7 @@ #include <environment/ti/dfu.h> #define CONFIG_DRA7XX +#define CONFIG_AM57XX #ifdef CONFIG_SPL_BUILD #define CONFIG_IODELAY_RECALIBRATION diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h index e1f724b..4d1ceff 100644 --- a/include/configs/cl-som-am57x.h +++ b/include/configs/cl-som-am57x.h @@ -12,6 +12,7 @@ #define __CONFIG_CL_SOM_AM57X_H #define CONFIG_DRA7XX +#define CONFIG_AM57XX #define CONFIG_NR_DRAM_BANKS 2 diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h index 9de80d7..ba21d60 100644 --- a/include/linux/usb/xhci-omap.h +++ b/include/linux/usb/xhci-omap.h @@ -14,7 +14,7 @@ #define OMAP_XHCI_BASE 0x488d0000 #define OMAP_OCP1_SCP_BASE 0x4A081000 #define OMAP_OTG_WRAPPER_BASE 0x488c0000 -#elif defined CONFIG_TARGET_AM57XX_EVM +#elif defined CONFIG_AM57XX #define OMAP_XHCI_BASE 0x48890000 #define OMAP_OCP1_SCP_BASE 0x4A084c00 #define OMAP_OTG_WRAPPER_BASE 0x48880000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d21589b..7c7f372 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -85,6 +85,7 @@ CONFIG_AM335X_USB0_MODE CONFIG_AM335X_USB1 CONFIG_AM335X_USB1_MODE CONFIG_AM437X_USB2PHY2_HOST +CONFIG_AM57XX CONFIG_AMBAPP_IOAREA CONFIG_AMCC_DEF_ENV CONFIG_AMCC_DEF_ENV_NOR_UPD -- 2.7.4

5 8

Re: [U-Boot] [PATCH 1/3] mx6sx: udoo_neo: Define the default serial console
by Breno Matheus Lima 15 Feb '17

15 Feb '17

Hi Peter, 2017-02-14 11:10 GMT-02:00 Peter Robinson <pbrobinson(a)gmail.com>: > From: Peter Robinson <pbrobinson(a)gmail.com> > Date: Tue, Feb 14, 2017 at 11:10 AM > Subject: [U-Boot] [PATCH 1/3] mx6sx: udoo_neo: Define the default serial console > To: Breno Lima <breno.lima(a)nxp.com>, Francesco Montefoschi > <francesco.montefoschi(a)udoo.org>, Stefano Babic <sbabic(a)denx.de>, > u-boot(a)lists.denx.de > > > Standard boot processes including distro boot generally expect the > default console to be defined. > > Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> For the entire series: Tested-by: Breno Lima <breno.lima(a)nxp.com> Thanks Best Regards, -- Breno Matheus Lima

1 0

[U-Boot] [PATCH v2] splash: fix splash source flags check
by Anatolij Gustschin 15 Feb '17

15 Feb '17

From: "tomas.melin(a)vaisala.com" <tomas.melin(a)vaisala.com> SPLASH_STORAGE_RAW is defined as 0, so a check against & will never be true. These flags are never combined so do a check against == instead. Signed-off-by: Tomas Melin <tomas.melin(a)vaisala.com> Reviewed-by: Tom Rini <trini(a)konsulko.com> --- Changes in v2: - rebased on u-boot-video/master common/splash_source.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/splash_source.c b/common/splash_source.c index 4c64f10..a5eeb3f 100644 --- a/common/splash_source.c +++ b/common/splash_source.c @@ -395,9 +395,9 @@ int splash_source_load(struct splash_location *locations, uint size) if (!splash_location) return -EINVAL; - if (splash_location->flags & SPLASH_STORAGE_RAW) + if (splash_location->flags == SPLASH_STORAGE_RAW) return splash_load_raw(splash_location, bmp_load_addr); - else if (splash_location->flags & SPLASH_STORAGE_FS) + else if (splash_location->flags == SPLASH_STORAGE_FS) return splash_load_fs(splash_location, bmp_load_addr); #ifdef CONFIG_FIT else if (splash_location->flags == SPLASH_STORAGE_FIT) -- 2.7.4

3 3

[U-Boot] [PATCH v1] mmc: tangier: Add Intel Tangier eMMC/SDHCI driver
by Andy Shevchenko 15 Feb '17

15 Feb '17

From: Felipe Balbi <felipe.balbi(a)linux.intel.com> This patch adds Intel Tangier eMMC/SDHCI driver. Signed-off-by: Vincent Tinelli <vincent.tinelli(a)intel.com> Signed-off-by: Felipe Balbi <felipe.balbi(a)linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- drivers/mmc/Kconfig | 5 ++++ drivers/mmc/Makefile | 1 + drivers/mmc/tangier_sdhci.c | 73 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) create mode 100644 drivers/mmc/tangier_sdhci.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 01d1dbfb1b..42a44f9888 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -310,6 +310,11 @@ config MMC_SDHCI_XENON If unsure, say N. +config MMC_SDHCI_TANGIER + bool "Tangier SDHCI controller supprt" + depends on DM_MMC && BLK && DM_MMC_OPS + depends on MMC_SDHCI + config MMC_SDHCI_TEGRA bool "SDHCI platform support for the Tegra SD/MMC Controller" depends on TEGRA diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index ef27d55088..019b587441 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_MMC_SDHCI_PIC32) += pic32_sdhci.o obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o obj-$(CONFIG_MMC_SDHCI_SPEAR) += spear_sdhci.o +obj-$(CONFIG_MMC_SDHCI_TANGIER) += tangier_sdhci.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o diff --git a/drivers/mmc/tangier_sdhci.c b/drivers/mmc/tangier_sdhci.c new file mode 100644 index 0000000000..6a8a6270a9 --- /dev/null +++ b/drivers/mmc/tangier_sdhci.c @@ -0,0 +1,73 @@ +#include <common.h> +#include <linux/io.h> +#include <linux/sizes.h> +#include <mmc.h> +#include <dm.h> +#include <dm/device.h> +#include <malloc.h> +#include <sdhci.h> + +struct sdhci_tangier_plat { + struct mmc_config cfg; + struct mmc mmc; + void __iomem *ioaddr; +}; + +static int sdhci_tangier_bind(struct udevice *dev) +{ + struct sdhci_tangier_plat *plat = dev_get_platdata(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + +static int sdhci_tangier_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct sdhci_tangier_plat *plat = dev_get_platdata(dev); + struct sdhci_host *host = dev_get_priv(dev); + fdt_addr_t base; + int ret; + + base = dev_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->ioaddr = devm_ioremap(dev, base, SZ_1K); + if (!plat->ioaddr) + return -ENOMEM; + + host->name = dev->name; + host->ioaddr = plat->ioaddr; + host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | + SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | + SDHCI_QUIRK_WAIT_SEND_CMD; + + /* MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195 */ + host->voltages = MMC_VDD_165_195; + + ret = sdhci_setup_cfg(&plat->cfg, host, 200000000, 400000); + if (ret) + return ret; + + upriv->mmc = &plat->mmc; + host->mmc = &plat->mmc; + host->mmc->priv = host; + + return sdhci_probe(dev); +} + +static const struct udevice_id sdhci_tangier_match[] = { + { .compatible = "intel,sdhci-tangier" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sdhci_tangier) = { + .name = "sdhci-tangier", + .id = UCLASS_MMC, + .of_match = sdhci_tangier_match, + .bind = sdhci_tangier_bind, + .probe = sdhci_tangier_probe, + .ops = &sdhci_ops, + .priv_auto_alloc_size = sizeof(struct sdhci_host), + .platdata_auto_alloc_size = sizeof(struct sdhci_tangier_plat), +}; -- 2.11.0

3 2

[U-Boot] [PATCH v1] mmc: pci: only compile on platforms that need it
by Andy Shevchenko 15 Feb '17

15 Feb '17

From: Felipe Balbi <felipe.balbi(a)linux.intel.com> We should only compile pci_mmc.c on platforms that actually need this. Some platforms are using generic sdhci through driver model. Signed-off-by: Felipe Balbi <felipe.balbi(a)linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- drivers/mmc/Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 49413dfaf1..26db92e582 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -36,7 +36,9 @@ obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o obj-$(CONFIG_MMC_MXC) += mxcmmc.o obj-$(CONFIG_MMC_MXS) += mxsmmc.o -obj-$(CONFIG_X86) += pci_mmc.o +obj-$(CONFIG_INTEL_BAYTRAIL) += pci_mmc.o +obj-$(CONFIG_INTEL_QUARK) += pci_mmc.o +obj-$(CONFIG_INTEL_QUEENSBAY) += pci_mmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_S3C_SDI) += s3c_sdi.o -- 2.11.0

3 2

[U-Boot] Assigning u-boot environment variables from memory
by brendan 15 Feb '17

15 Feb '17

I am storing some information regarding my board within EEPROM (in memory after I use the >eeprom read command) and I was wondering if it was possible for me to somehow read from memory and store the values into an environment variable. I have done a search but could not find anything of relevance. Thanks -- View this message in context: http://u-boot.10912.n7.nabble.com/Assigning-u-boot-environment-variables-fr… Sent from the U-Boot mailing list archive at Nabble.com.

3 2

[U-Boot] [ANN] U-Boot v2017.03-rc2 released
by Tom Rini 14 Feb '17

14 Feb '17

Hey all, It's release day and v2017.03-rc2 is out. I think my patchwork queue is looking good currently but I'm open to being told there's important stuff outstanding. I'm probably going to grab some Kconfig things and perhaps other cleanups I can mechanically confirm are correct. Things are on track for -rc3 on the 27th. Thanks all! -- Tom

5 11

[U-Boot] [PATCH] arm: socfpga: fix issue with warm reset when CSEL is 0
by Dalon Westergreen 14 Feb '17

14 Feb '17

When CSEL=0x0 the socfpga bootrom does not touch the clock configuration for the device. This can lead to a boot failure on warm resets. To address this, the bootrom is configured to run a bit of code in the last 4KB of onchip ram on a warm reset. This code puts the PLLs in bypass, disables the bootrom configuration to run the code snippet, and issues a warm reset to run the bootrom. Signed-off-by: Dalon Westergreen <dwesterg(a)gmail.com> --- arch/arm/mach-socfpga/Makefile | 2 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 22 ++++++- arch/arm/mach-socfpga/include/mach/reset_manager.h | 4 ++ .../arm/mach-socfpga/include/mach/system_manager.h | 7 ++- arch/arm/mach-socfpga/misc.c | 29 +++++++++ arch/arm/mach-socfpga/reset_clock_manager.S | 71 ++++++++++++++++++++++ 6 files changed, 132 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 809cd47..6876ccf 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -8,7 +8,7 @@ # obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ - fpga_manager.o board.o + fpga_manager.o board.o reset_clock_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 803c926..dd58c20 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -21,7 +21,6 @@ const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); /* Clock configuration accessors */ const struct cm_config * const cm_get_default_config(void); -#endif struct cm_config { /* main group */ @@ -127,6 +126,19 @@ struct socfpga_clock_manager { struct socfpga_clock_manager_altera altera; u32 _pad_0xe8_0x200[70]; }; +#endif + +#define CLKMGR_CTRL_ADDRESS 0x0 +#define CLKMGR_BYPASS_ADDRESS 0x4 +#define CLKMGR_INTER_ADDRESS 0x8 +#define CLKMGR_INTREN_ADDRESS 0xc +#define CLKMGR_DBCTRL_ADDRESS 0x10 +#define CLKMGR_STAT_ADDRESS 0x14 +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS 0x54 +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS 0x58 +#define CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS 0x90 +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS 0x94 + #define CLKMGR_CTRL_SAFEMODE (1 << 0) #define CLKMGR_CTRL_SAFEMODE_OFFSET 0 @@ -314,4 +326,12 @@ struct socfpga_clock_manager { #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 +/* Bypass Main and Per PLL, bypass source per input mux */ +#define CLKMGR_BYPASS_MAIN_PER_PLL_MASK 0x19 + +#define CLKMGR_MAINQSPICLK_RESET_VALUE 0x3 +#define CLKMGR_MAINNANDSDMMCCLK_RESET_VALUE 0x3 +#define CLKMGR_PERQSPICLK_RESET_VALUE 0x1 +#define CLKMGR_PERNANDSDMMCCLK_RESET_VALUE 0x1 + #endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 2f070f2..58d77fb 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -7,6 +7,7 @@ #ifndef _RESET_MANAGER_H_ #define _RESET_MANAGER_H_ +#ifndef __ASSEMBLY__ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); @@ -28,6 +29,8 @@ struct socfpga_reset_manager { u32 padding2[12]; u32 tstscratch; }; +#endif + #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 @@ -40,6 +43,7 @@ struct socfpga_reset_manager { * and reset ID can be extracted using the subsequent macros * RSTMGR_RESET() and RSTMGR_BANK(). */ +#define RSTMGR_CTRL_OFFSET 4 #define RSTMGR_BANK_OFFSET 8 #define RSTMGR_BANK_MASK 0x7 #define RSTMGR_RESET_OFFSET 0 diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index c45edea..d04fa2f 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -13,7 +13,6 @@ void sysmgr_pinmux_init(void); void sysmgr_config_warmrstcfgio(int enable); void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); -#endif struct socfpga_system_manager { /* System Manager Module */ @@ -115,6 +114,12 @@ struct socfpga_system_manager { u32 _pad_0x734; u32 spim0usefpga; /* 0x738 */ }; +#endif + +#define CONFIG_SYSMGR_WARMRAMGRP_ENABLE (SOCFPGA_SYSMGR_ADDRESS + 0xe0) + +#define SYSMGR_BOOTINFO_CSEL_MASK 0x18 +#define SYSMGR_BOOTINFO_CSEL_LSB 3 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index dd6b53b..4d41420 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -22,6 +22,9 @@ #include <dt-bindings/reset/altr,rst-mgr.h> +void reset_clock_manager(void); +extern unsigned reset_clock_manager_size; + DECLARE_GLOBAL_DATA_PTR; static struct pl310_regs *const pl310 = @@ -356,6 +359,32 @@ static uint32_t iswgrp_handoff[8]; int arch_early_init_r(void) { int i; + unsigned csel, ramboot_addr; + + /* Check the CSEL value */ + csel = (readl(&sysmgr_regs->bootinfo) & SYSMGR_BOOTINFO_CSEL_MASK) >> + SYSMGR_BOOTINFO_CSEL_LSB; + + /* + * For CSEL = 0 the bootrom does not configure the clocks which can + * result in a boot failure on warm resets. To remedy this a small + * bit of code is placed at the end of the onchip ram and run on + * a warm reset. It puts the PLLs in bypass and issues another warm + * reset to get back to the bootrom. + */ + if(!csel) { + /* Put the code snippet in the last 4KB of the onchip ram */ + ramboot_addr = CONFIG_SYS_INIT_RAM_ADDR + + CONFIG_SYS_INIT_RAM_SIZE - 0x1000; + + /* Copy the code to the onchip ramlocation */ + memcpy((void *)ramboot_addr, reset_clock_manager, + reset_clock_manager_size); + + /* Set the bootrom to run the code snippet on reset */ + writel(ramboot_addr, + &sysmgr_regs->romcodegrp_warmramgrp_execution); + } /* * Write magic value into magic register to unlock support for diff --git a/arch/arm/mach-socfpga/reset_clock_manager.S b/arch/arm/mach-socfpga/reset_clock_manager.S new file mode 100644 index 0000000..1818b2d --- /dev/null +++ b/arch/arm/mach-socfpga/reset_clock_manager.S @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2017, Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/clock_manager.h> + +/* + */ +ENTRY(reset_clock_manager) + /* Put Main PLL and Peripheral PLL in bypass */ + ldr r0, SOCFPGA_CLKMGR + mov r1, #CLKMGR_BYPASS_ADDRESS + mov r2, #CLKMGR_BYPASS_MAIN_PER_PLL_MASK + add r3, r0, r1 + ldr r4, [r3] + orr r5, r4, r2 + str r5, [r3] + dsb + isb + mov r1, #CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS + mov r2, #CLKMGR_MAINQSPICLK_RESET_VALUE + add r3, r0, r1 + str r2, [r3] + mov r1, #CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS + mov r2, #CLKMGR_MAINNANDSDMMCCLK_RESET_VALUE + add r3, r0, r1 + str r2, [r3] + mov r1, #CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS + mov r2, #CLKMGR_PERQSPICLK_RESET_VALUE + add r3, r0, r1 + str r2, [r3] + mov r1, #CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS + mov r2, #CLKMGR_PERNANDSDMMCCLK_RESET_VALUE + add r3, r0, r1 + str r2, [r3] + + /* Disable the RAM boot */ + ldr r0, SOCFPGA_RSTMGR + ldr r1, SYSMGR_WARMRAMGRP_ENABLE + mov r2, #0 + str r2, [r1] + + /* Trigger warm reset to continue boot normally */ + mov r1, #RSTMGR_CTRL_OFFSET + add r2, r0, r1 + mov r3, #1 + mov r3, r3, LSL #RSTMGR_CTRL_SWWARMRSTREQ_LSB + ldr r4, [r2] + orr r4, r3, r4 + str r4, [r2] + +reset_clock_manager_loop: + dsb + isb + b reset_clock_manager_loop +ENDPROC(reset_clock_manager) + +SOCFPGA_CLKMGR: .word SOCFPGA_CLKMGR_ADDRESS +SOCFPGA_RSTMGR: .word SOCFPGA_RSTMGR_ADDRESS +SYSMGR_WARMRAMGRP_ENABLE: .word CONFIG_SYSMGR_WARMRAMGRP_ENABLE + +.globl reset_clock_manager_size +reset_clock_manager_size: + .word . - reset_clock_manager + -- 2.7.4

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[U-Boot] [PATCH 0/9] Rewrite ARMv8 layerscape MMU
by York Sun 14 Feb '17

14 Feb '17

A recent debug revealed MMU for DDR shouldn't be enabled before DDR is initialized. Otherwise, a "normal memory" mapping may cause speculative access which may hang the system if accessing to DDR is not allowed at time. For Layerscape platforms, we have early MMU setup to speed up execution on emulators. The solution is to update MMU after DDR is ready. The same idea goes to final MMU as well. Actual DDR size is used to create the mappings. Non-exist address should be marked as "fault", i.e. invalid to avoid unwanted speculative access. Aside from the DDR size, reserved memory used for secure RAM and Management Complex (MC) makes things more complicated. To simplify it, a new global is added to track the reserved RAM. Secure RAM is excluded from U-Boot MMU. The reserved RAM is still mapped under U-Boot since we will need to copy data into it. Reserved RAM is excluded when device tree is fixed up so OS won't see it. Some MC configurations are moved to Kconfig. York Sun (9): armv8: Add global variable resv_ram armv8: ls2080a: Move CONFIG_FSL_MC_ENET to Kconfig armv8: ls2080a: Move CONFIG_SYS_MC_RSV_MEM_ALIGN to Kconfig armv8: layerscape: Rewrite memory reservation driver: net: fsl-mc: Update calculation of MC RAM armv8: layerscape: Update MMU mapping with actual DDR size armv8: layerscape: Flush MMU tables after creattion armv8: mmu: Add a function to change mapping attributes armv8: layerscape: Update early MMU for DDR after initialization arch/arm/cpu/armv8/cache_v8.c | 72 +++++- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 22 ++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 292 +++++++++++++++++++++- arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 +- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 +- arch/arm/include/asm/arch-fsl-layerscape/mmu.h | 2 +- arch/arm/include/asm/armv8/mmu.h | 5 + arch/arm/include/asm/global_data.h | 3 + arch/arm/include/asm/system.h | 1 + board/freescale/ls1012afrdm/ls1012afrdm.c | 34 +-- board/freescale/ls1012aqds/ls1012aqds.c | 34 +-- board/freescale/ls1012ardb/ls1012ardb.c | 34 +-- board/freescale/ls1043aqds/ddr.c | 29 --- board/freescale/ls1043aqds/ls1043aqds.c | 5 + board/freescale/ls1043ardb/ddr.c | 29 --- board/freescale/ls1043ardb/ls1043ardb.c | 7 - board/freescale/ls1046aqds/ddr.c | 29 --- board/freescale/ls1046aqds/ls1046aqds.c | 5 + board/freescale/ls1046ardb/ddr.c | 29 --- board/freescale/ls1046ardb/ls1046ardb.c | 7 - board/freescale/ls2080a/ddr.c | 55 ---- board/freescale/ls2080a/ls2080a.c | 17 +- board/freescale/ls2080aqds/ddr.c | 55 ---- board/freescale/ls2080aqds/ls2080aqds.c | 17 +- board/freescale/ls2080ardb/ddr.c | 55 ---- board/freescale/ls2080ardb/ls2080ardb.c | 18 +- cmd/bdinfo.c | 4 + common/board_f.c | 32 +-- drivers/net/fsl-mc/mc.c | 75 +----- include/configs/ls2080a_common.h | 2 - scripts/config_whitelist.txt | 2 - 31 files changed, 473 insertions(+), 514 deletions(-) -- 2.7.4

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