February 2017 - U-Boot

[U-Boot] [PATCH] ARM: uniphier: disable CONFIG_MTD_NOR_FLASH
by Masahiro Yamada 17 Feb '17

17 Feb '17

This feature is seldom used these days on UniPhier boards. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- configs/uniphier_ld11_defconfig | 1 - configs/uniphier_ld20_defconfig | 1 - configs/uniphier_ld4_sld8_defconfig | 1 - configs/uniphier_pro4_defconfig | 1 - configs/uniphier_pxs2_ld6b_defconfig | 1 - configs/uniphier_sld3_defconfig | 1 - configs/uniphier_v8_defconfig | 1 - 7 files changed, 7 deletions(-) diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig index f14ae04..deddac4 100644 --- a/configs/uniphier_ld11_defconfig +++ b/configs/uniphier_ld11_defconfig @@ -31,7 +31,6 @@ CONFIG_I2C_EEPROM=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig index c065bf2..272304f 100644 --- a/configs/uniphier_ld20_defconfig +++ b/configs/uniphier_ld20_defconfig @@ -31,7 +31,6 @@ CONFIG_I2C_EEPROM=y CONFIG_MMC_UNIPHIER=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index b9a9524..dad0a34 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -32,7 +32,6 @@ CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_MMC_UNIPHIER=y -CONFIG_MTD_NOR_FLASH=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig index 0b83a1b..36f9743 100644 --- a/configs/uniphier_pro4_defconfig +++ b/configs/uniphier_pro4_defconfig @@ -31,7 +31,6 @@ CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_MMC_UNIPHIER=y -CONFIG_MTD_NOR_FLASH=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig index 7e6f0a0..5e3b044 100644 --- a/configs/uniphier_pxs2_ld6b_defconfig +++ b/configs/uniphier_pxs2_ld6b_defconfig @@ -32,7 +32,6 @@ CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_MMC_UNIPHIER=y -CONFIG_MTD_NOR_FLASH=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig index f1f2a3f..29f43cd 100644 --- a/configs/uniphier_sld3_defconfig +++ b/configs/uniphier_sld3_defconfig @@ -32,7 +32,6 @@ CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_MMC_UNIPHIER=y -CONFIG_MTD_NOR_FLASH=y CONFIG_NAND_DENALI=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index a8f2816..b6010cc 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -27,7 +27,6 @@ CONFIG_I2C_EEPROM=y CONFIG_MMC_UNIPHIER=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y -- 2.7.4

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[U-Boot] [PATCH] ARM: dts: uniphier: drop u-boot, dm-pre-reloc from system-bus pinctrl node
by Masahiro Yamada 17 Feb '17

17 Feb '17

Since commit 26b09c022ab6 ("ARM: uniphier: move SBC and Support Card init code to U-Boot proper"), SPL does not need pin-mux settings for the System Bus. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/dts/uniphier-ld11-ref.dts | 4 ---- arch/arm/dts/uniphier-ld20-ref.dts | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm/dts/uniphier-ld11-ref.dts b/arch/arm/dts/uniphier-ld11-ref.dts index ea11198..7693bf2 100644 --- a/arch/arm/dts/uniphier-ld11-ref.dts +++ b/arch/arm/dts/uniphier-ld11-ref.dts @@ -71,7 +71,3 @@ &pinctrl_uart0 { u-boot,dm-pre-reloc; }; - -&pinctrl_system_bus { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts index 044e000..41ee07e 100644 --- a/arch/arm/dts/uniphier-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ld20-ref.dts @@ -59,7 +59,3 @@ &pinctrl_uart0 { u-boot,dm-pre-reloc; }; - -&pinctrl_system_bus { - u-boot,dm-pre-reloc; -}; -- 2.7.4

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[U-Boot] [PATCH 1/2] pinctrl: uniphier: support pin configuration
by Masahiro Yamada 17 Feb '17

17 Feb '17

Support the following DT properties: "bias-disable" "bias-pull-up" "bias-pull-down" "bias-pull-pin-default" "input-enable" "input-disable" My main motivation is to support pull up/down biasing. For Pro5 and later SoCs, the pupdctrl register number is the same as the pinmux number, so this feature can be supported without having big pin tables. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 134 +++++++++++++++++++++-- drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 3 +- drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 3 +- drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 3 +- drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 1 + drivers/pinctrl/uniphier/pinctrl-uniphier.h | 1 + 7 files changed, 134 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index 51144b8..d8e9948 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> #include <linux/io.h> #include <linux/err.h> #include <linux/sizes.h> @@ -15,6 +16,7 @@ #define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000 #define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700 +#define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00 #define UNIPHIER_PINCTRL_IECTRL 0x1d00 static const char *uniphier_pinctrl_dummy_name = "_dummy"; @@ -55,8 +57,8 @@ static const char *uniphier_pinmux_get_function_name(struct udevice *dev, return priv->socdata->functions[selector]; } -static void uniphier_pinconf_input_enable_perpin(struct udevice *dev, - unsigned pin) +static int uniphier_pinconf_input_enable_perpin(struct udevice *dev, + unsigned int pin, int enable) { struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); unsigned reg; @@ -66,18 +68,30 @@ static void uniphier_pinconf_input_enable_perpin(struct udevice *dev, mask = BIT(pin % 32); tmp = readl(priv->base + reg); - tmp |= mask; + if (enable) + tmp |= mask; + else + tmp &= ~mask; writel(tmp, priv->base + reg); + + return 0; } -static void uniphier_pinconf_input_enable_legacy(struct udevice *dev, - unsigned pin) +static int uniphier_pinconf_input_enable_legacy(struct udevice *dev, + unsigned int pin, int enable) { struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); int pins_count = priv->socdata->pins_count; const struct uniphier_pinctrl_pin *pins = priv->socdata->pins; int i; + /* + * Multiple pins share one input enable, per-pin disabling is + * impossible. + */ + if (!enable) + return -EINVAL; + for (i = 0; i < pins_count; i++) { if (pins[i].number == pin) { unsigned int iectrl; @@ -89,18 +103,115 @@ static void uniphier_pinconf_input_enable_legacy(struct udevice *dev, writel(tmp, priv->base + UNIPHIER_PINCTRL_IECTRL); } } + + return 0; } -static void uniphier_pinconf_input_enable(struct udevice *dev, unsigned pin) +static int uniphier_pinconf_input_enable(struct udevice *dev, + unsigned int pin, int enable) { struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) - uniphier_pinconf_input_enable_perpin(dev, pin); + return uniphier_pinconf_input_enable_perpin(dev, pin, enable); + else + return uniphier_pinconf_input_enable_legacy(dev, pin, enable); +} + +#if CONFIG_IS_ENABLED(PINCONF) + +static const struct pinconf_param uniphier_pinconf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, +}; + +static int uniphier_pinconf_bias_set(struct udevice *dev, unsigned int pin, + unsigned int param, unsigned int arg) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + unsigned int enable = 1; + unsigned int reg; + u32 mask, tmp; + + if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE)) + return -ENOTSUPP; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + enable = 0; + break; + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg == 0) /* total bias is not supported */ + return -EINVAL; + break; + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + if (arg == 0) /* configuration ignored */ + return 0; + default: + BUG(); + } + + reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pin / 32 * 4; + mask = BIT(pin % 32); + + tmp = readl(priv->base + reg); + if (enable) + tmp |= mask; else - uniphier_pinconf_input_enable_legacy(dev, pin); + tmp &= ~mask; + writel(tmp, priv->base + reg); + + return 0; +} + +static int uniphier_pinconf_set_one(struct udevice *dev, unsigned int pin, + unsigned int param, unsigned int arg) +{ + int ret; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + ret = uniphier_pinconf_bias_set(dev, pin, param, arg); + break; + case PIN_CONFIG_INPUT_ENABLE: + ret = uniphier_pinconf_input_enable(dev, pin, arg); + break; + default: + printf("unsupported configuration parameter %u\n", param); + return -EINVAL; + } + + return ret; } +static int uniphier_pinconf_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int param, unsigned int arg) +{ + struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); + const struct uniphier_pinctrl_group *grp = + &priv->socdata->groups[group_selector]; + int i, ret; + + for (i = 0; i < grp->num_pins; i++) { + ret = uniphier_pinconf_set_one(dev, grp->pins[i], param, arg); + if (ret) + return ret; + } + + return 0; +} + +#endif /* CONFIG_IS_ENABLED(PINCONF) */ + static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, int muxval) { @@ -112,7 +223,7 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, u32 tmp; /* some pins need input-enabling */ - uniphier_pinconf_input_enable(dev, pin); + uniphier_pinconf_input_enable(dev, pin, 1); if (muxval < 0) return; /* dedicated pin; nothing to do for pin-mux */ @@ -174,6 +285,11 @@ const struct pinctrl_ops uniphier_pinctrl_ops = { .get_functions_count = uniphier_pinmux_get_functions_count, .get_function_name = uniphier_pinmux_get_function_name, .pinmux_group_set = uniphier_pinmux_group_set, +#if CONFIG_IS_ENABLED(PINCONF) + .pinconf_num_params = ARRAY_SIZE(uniphier_pinconf_params), + .pinconf_params = uniphier_pinconf_params, + .pinconf_group_set = uniphier_pinconf_group_set, +#endif .set_state = pinctrl_generic_set_state, }; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index 1d318d8..53c37cd 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -92,7 +92,8 @@ static struct uniphier_pinctrl_socdata uniphier_ld11_pinctrl_socdata = { .groups_count = ARRAY_SIZE(uniphier_ld11_groups), .functions = uniphier_ld11_functions, .functions_count = ARRAY_SIZE(uniphier_ld11_functions), - .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL, + .caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE | + UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL, }; static int uniphier_ld11_pinctrl_probe(struct udevice *dev) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 0c46450..5a7d142 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -106,7 +106,8 @@ static struct uniphier_pinctrl_socdata uniphier_ld20_pinctrl_socdata = { .groups_count = ARRAY_SIZE(uniphier_ld20_groups), .functions = uniphier_ld20_functions, .functions_count = ARRAY_SIZE(uniphier_ld20_functions), - .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL, + .caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE | + UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL, }; static int uniphier_ld20_pinctrl_probe(struct udevice *dev) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c index 80d782c..b25c7ea 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c @@ -140,6 +140,7 @@ static struct uniphier_pinctrl_socdata uniphier_ld6b_pinctrl_socdata = { .groups_count = ARRAY_SIZE(uniphier_ld6b_groups), .functions = uniphier_ld6b_functions, .functions_count = ARRAY_SIZE(uniphier_ld6b_functions), + .caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE, }; static int uniphier_ld6b_pinctrl_probe(struct udevice *dev) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 9670f25..70c90ba 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -147,7 +147,8 @@ static struct uniphier_pinctrl_socdata uniphier_pro5_pinctrl_socdata = { .groups_count = ARRAY_SIZE(uniphier_pro5_groups), .functions = uniphier_pro5_functions, .functions_count = ARRAY_SIZE(uniphier_pro5_functions), - .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE, + .caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE | + UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE, }; static int uniphier_pro5_pinctrl_probe(struct udevice *dev) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index 1d29170..60777c3 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -140,6 +140,7 @@ static struct uniphier_pinctrl_socdata uniphier_pxs2_pinctrl_socdata = { .groups_count = ARRAY_SIZE(uniphier_pxs2_groups), .functions = uniphier_pxs2_functions, .functions_count = ARRAY_SIZE(uniphier_pxs2_functions), + .caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE, }; static int uniphier_pxs2_pinctrl_probe(struct udevice *dev) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 21e2d37..a0eccf8 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -67,6 +67,7 @@ struct uniphier_pinctrl_socdata { const char * const *functions; int functions_count; unsigned caps; +#define UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE BIT(3) #define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(2) #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(1) #define UNIPHIER_PINCTRL_CAPS_MUX_4BIT BIT(0) -- 2.7.4

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[U-Boot] [PATCH] ARM: uniphier: enable generic EHCI driver for uniphier_v8_defconfig
by Masahiro Yamada 17 Feb '17

17 Feb '17

The LD11 SoC is equipped with USB EHCI controllers. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- configs/uniphier_v8_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index b6010cc..5dadc4c 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -30,4 +30,6 @@ CONFIG_MMC_SDHCI_CADENCE=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y -- 2.7.4

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[U-Boot] [PATCH] ARM: uniphier: remove DRAM base address from board parameters
by Masahiro Yamada 17 Feb '17

17 Feb '17

The base address of each DRAM channel can be calculated from other parameters, so does not need hard-coding. What we need is the size of each DRAM channel and DRAM_SPARSE flag to decide the start address of DRAM channel 1. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/mach-uniphier/bcu/bcu-ld4.c | 2 +- arch/arm/mach-uniphier/bcu/bcu-sld3.c | 2 +- arch/arm/mach-uniphier/boards.c | 30 +------------------- arch/arm/mach-uniphier/dram_init.c | 53 ++++++++++++++++++++--------------- arch/arm/mach-uniphier/init.h | 4 +-- arch/arm/mach-uniphier/memconf.c | 2 +- 6 files changed, 36 insertions(+), 57 deletions(-) diff --git a/arch/arm/mach-uniphier/bcu/bcu-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ld4.c index 7557880..a16b24e 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-ld4.c +++ b/arch/arm/mach-uniphier/bcu/bcu-ld4.c @@ -24,7 +24,7 @@ void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd) writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ /* Specify DDR channel */ - shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4; + shift = bd->dram_ch[0].size / 0x04000000 * 4; writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ shift -= 32; diff --git a/arch/arm/mach-uniphier/bcu/bcu-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-sld3.c index 64efd37..99b318f 100644 --- a/arch/arm/mach-uniphier/bcu/bcu-sld3.c +++ b/arch/arm/mach-uniphier/bcu/bcu-sld3.c @@ -28,7 +28,7 @@ void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd) writel(0x24440000, BCSCR5); /* Specify DDR channel */ - shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4; + shift = bd->dram_ch[0].size / 0x04000000 * 4; writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ shift -= 32; diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index 0596451..26dae9e 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -18,20 +18,18 @@ static const struct uniphier_board_data uniphier_sld3_data = { .dram_freq = 1600, .dram_nr_ch = 3, .dram_ch[0] = { - .base = 0x80000000, .size = 0x20000000, .width = 32, }, .dram_ch[1] = { - .base = 0xc0000000, .size = 0x20000000, .width = 16, }, .dram_ch[2] = { - .base = 0xc0000000, .size = 0x10000000, .width = 16, }, + .flags = UNIPHIER_BD_DRAM_SPARSE, }; #endif @@ -40,12 +38,10 @@ static const struct uniphier_board_data uniphier_ld4_data = { .dram_freq = 1600, .dram_nr_ch = 2, .dram_ch[0] = { - .base = 0x80000000, .size = 0x10000000, .width = 16, }, .dram_ch[1] = { - .base = 0x90000000, .size = 0x10000000, .width = 16, }, @@ -59,12 +55,10 @@ static const struct uniphier_board_data uniphier_pro4_data = { .dram_freq = 1600, .dram_nr_ch = 2, .dram_ch[0] = { - .base = 0x80000000, .size = 0x20000000, .width = 32, }, .dram_ch[1] = { - .base = 0xa0000000, .size = 0x20000000, .width = 32, }, @@ -75,12 +69,10 @@ static const struct uniphier_board_data uniphier_pro4_2g_data = { .dram_freq = 1600, .dram_nr_ch = 2, .dram_ch[0] = { - .base = 0x80000000, .size = 0x40000000, .width = 32, }, .dram_ch[1] = { - .base = 0xc0000000, .size = 0x40000000, .width = 32, }, @@ -92,12 +84,10 @@ static const struct uniphier_board_data uniphier_sld8_data = { .dram_freq = 1333, .dram_nr_ch = 2, .dram_ch[0] = { - .base = 0x80000000, .size = 0x10000000, .width = 16, }, .dram_ch[1] = { - .base = 0x90000000, .size = 0x10000000, .width = 16, }, @@ -110,12 +100,10 @@ static const struct uniphier_board_data uniphier_pro5_data = { .dram_freq = 1866, .dram_nr_ch = 2, .dram_ch[0] = { - .base = 0x80000000, .size = 0x20000000, .width = 32, }, .dram_ch[1] = { - .base = 0xa0000000, .size = 0x20000000, .width = 32, }, @@ -127,17 +115,14 @@ static const struct uniphier_board_data uniphier_pxs2_data = { .dram_freq = 2133, .dram_nr_ch = 3, .dram_ch[0] = { - .base = 0x80000000, .size = 0x40000000, .width = 32, }, .dram_ch[1] = { - .base = 0xc0000000, .size = 0x20000000, .width = 32, }, .dram_ch[2] = { - .base = 0xe0000000, .size = 0x20000000, .width = 16, }, @@ -149,17 +134,14 @@ static const struct uniphier_board_data uniphier_ld6b_data = { .dram_freq = 1866, .dram_nr_ch = 3, .dram_ch[0] = { - .base = 0x80000000, .size = 0x40000000, .width = 32, }, .dram_ch[1] = { - .base = 0xc0000000, .size = 0x20000000, .width = 32, }, .dram_ch[2] = { - .base = 0xe0000000, .size = 0x20000000, .width = 16, }, @@ -171,12 +153,10 @@ static const struct uniphier_board_data uniphier_ld11_data = { .dram_freq = 1600, .dram_nr_ch = 2, .dram_ch[0] = { - .base = 0x80000000, .size = 0x20000000, .width = 16, }, .dram_ch[1] = { - .base = 0xa0000000, .size = 0x20000000, .width = 16, }, @@ -188,17 +168,14 @@ static const struct uniphier_board_data uniphier_ld20_ref_data = { .dram_freq = 1866, .dram_nr_ch = 3, .dram_ch[0] = { - .base = 0x80000000, .size = 0x40000000, .width = 32, }, .dram_ch[1] = { - .base = 0xc0000000, .size = 0x40000000, .width = 32, }, .dram_ch[2] = { - .base = 0x100000000UL, .size = 0x40000000, .width = 32, }, @@ -209,17 +186,14 @@ static const struct uniphier_board_data uniphier_ld20_data = { .dram_freq = 1866, .dram_nr_ch = 3, .dram_ch[0] = { - .base = 0x80000000, .size = 0x40000000, .width = 32, }, .dram_ch[1] = { - .base = 0xc0000000, .size = 0x40000000, .width = 32, }, .dram_ch[2] = { - .base = 0x100000000UL, .size = 0x40000000, .width = 32, }, @@ -230,12 +204,10 @@ static const struct uniphier_board_data uniphier_ld21_data = { .dram_freq = 1866, .dram_nr_ch = 2, .dram_ch[0] = { - .base = 0x80000000, .size = 0x20000000, .width = 32, }, .dram_ch[1] = { - .base = 0xc0000000, .size = 0x40000000, .width = 32, }, diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 881062d..d121a3b 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -11,10 +11,12 @@ #include <linux/errno.h> #include <linux/sizes.h> -#include "init.h" #include "sg-regs.h" #include "soc-info.h" +#define pr_warn(fmt, args...) printf(fmt, ##args) +#define pr_err(fmt, args...) printf(fmt, ##args) + DECLARE_GLOBAL_DATA_PTR; struct uniphier_memif_data { @@ -76,7 +78,12 @@ static const struct uniphier_memif_data uniphier_memif_data[] = { }; UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data) -static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch) +struct uniphier_dram_map { + unsigned long base; + unsigned long size; +}; + +static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map) { const struct uniphier_memif_data *data; unsigned long size; @@ -91,7 +98,7 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch) val = readl(SG_MEMCONF); /* set up ch0 */ - dram_ch[0].base = CONFIG_SYS_SDRAM_BASE; + dram_map[0].base = CONFIG_SYS_SDRAM_BASE; switch (val & SG_MEMCONF_CH0_SZ_MASK) { case SG_MEMCONF_CH0_SZ_64M: @@ -117,20 +124,20 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch) if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2) size *= 2; - dram_ch[0].size = size; + dram_map[0].size = size; /* set up ch1 */ - dram_ch[1].base = dram_ch[0].base + size; + dram_map[1].base = dram_map[0].base + size; if (val & SG_MEMCONF_SPARSEMEM) { - if (dram_ch[1].base > data->sparse_ch1_base) { + if (dram_map[1].base > data->sparse_ch1_base) { pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n"); pr_warn("Only ch0 is available\n"); - dram_ch[1].base = 0; + dram_map[1].base = 0; return 0; } - dram_ch[1].base = data->sparse_ch1_base; + dram_map[1].base = data->sparse_ch1_base; } switch (val & SG_MEMCONF_CH1_SZ_MASK) { @@ -157,13 +164,13 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch) if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2) size *= 2; - dram_ch[1].size = size; + dram_map[1].size = size; if (!data->have_ch2) return 0; /* set up ch2 */ - dram_ch[2].base = dram_ch[1].base + size; + dram_map[2].base = dram_map[1].base + size; switch (val & SG_MEMCONF_CH2_SZ_MASK) { case SG_MEMCONF_CH2_SZ_64M: @@ -189,25 +196,25 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch) if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2) size *= 2; - dram_ch[2].size = size; + dram_map[2].size = size; return 0; } int dram_init(void) { - struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {}; + struct uniphier_dram_map dram_map[3] = {}; int ret, i; gd->ram_size = 0; - ret = uniphier_memconf_decode(dram_ch); + ret = uniphier_memconf_decode(dram_map); if (ret) return ret; - for (i = 0; i < ARRAY_SIZE(dram_ch); i++) { + for (i = 0; i < ARRAY_SIZE(dram_map); i++) { - if (!dram_ch[i].size) + if (!dram_map[i].size) break; /* @@ -215,11 +222,11 @@ int dram_init(void) * but it does not expect sparse memory. We use the first * contiguous chunk here. */ - if (i > 0 && - dram_ch[i - 1].base + dram_ch[i - 1].size < dram_ch[i].base) + if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size < + dram_map[i].base) break; - gd->ram_size += dram_ch[i].size; + gd->ram_size += dram_map[i].size; } return 0; @@ -227,17 +234,17 @@ int dram_init(void) void dram_init_banksize(void) { - struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {}; + struct uniphier_dram_map dram_map[3] = {}; int i; - uniphier_memconf_decode(dram_ch); + uniphier_memconf_decode(dram_map); - for (i = 0; i < ARRAY_SIZE(dram_ch); i++) { + for (i = 0; i < ARRAY_SIZE(dram_map); i++) { if (i >= ARRAY_SIZE(gd->bd->bi_dram)) break; - gd->bd->bi_dram[i].start = dram_ch[i].base; - gd->bd->bi_dram[i].size = dram_ch[i].size; + gd->bd->bi_dram[i].start = dram_map[i].base; + gd->bd->bi_dram[i].size = dram_map[i].size; } } diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 453e68a..c41a5df 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -13,7 +13,6 @@ #define UNIPHIER_MAX_NR_DRAM_CH 3 struct uniphier_dram_ch { - unsigned long base; unsigned long size; unsigned int width; }; @@ -24,7 +23,8 @@ struct uniphier_board_data { struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH]; unsigned int flags; -#define UNIPHIER_BD_DDR3PLUS BIT(2) +#define UNIPHIER_BD_DRAM_SPARSE BIT(9) +#define UNIPHIER_BD_DDR3PLUS BIT(8) #define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x7) #define UNIPHIER_BD_BOARD_LD20_REF 0 /* LD20 reference */ diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c index dcfc645..4ced2cb 100644 --- a/arch/arm/mach-uniphier/memconf.c +++ b/arch/arm/mach-uniphier/memconf.c @@ -93,7 +93,7 @@ static int __uniphier_memconf_init(const struct uniphier_board_data *bd, } /* is sparse mem? */ - if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base) + if (bd->flags & UNIPHIER_BD_DRAM_SPARSE) val |= SG_MEMCONF_SPARSEMEM; if (!have_ch2) -- 2.7.4

1 1

[U-Boot] [PATCH] ARM: uniphier: update README.uniphier for latest build instruction
by Masahiro Yamada 17 Feb '17

17 Feb '17

Since commit c0efc3140e75 ("ARM: uniphier: change CONFIG_SPL_PAD_TO to 128KB"), the u-boot.bin should be burned at the offset 0x20000. I missed to update README.uniphier in that commit. Now updating. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- doc/README.uniphier | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/README.uniphier b/doc/README.uniphier index 539b1f2..f79659c 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -75,7 +75,7 @@ Burn U-Boot images to NAND Write the following to the NAND device: - spl/u-boot-spl.bin at the offset address 0x00000000 - - u-boot.bin at the offset address 0x00010000 + - u-boot.bin at the offset address 0x00020000 or @@ -94,7 +94,7 @@ Burn U-Boot images to eMMC Write the following to the Boot partition 1 of the eMMC device: - spl/u-boot-spl.bin at the offset address 0x00000000 - - u-boot.bin at the offset address 0x00010000 + - u-boot.bin at the offset address 0x00020000 or @@ -179,4 +179,4 @@ newer SoCs. Even if it is, EA[25] is not connected on most of the boards. -- Masahiro Yamada <yamada.masahiro(a)socionext.com> -Oct. 2016 +Jan. 2017 -- 2.7.4

1 1

[U-Boot] [PATCH v2] spl: net: Add FIT image support over network boot
by Andrew F. Davis 16 Feb '17

16 Feb '17

FIT support in the net boot case is much like the RAM boot case in that we load our image to "load_addr" and pass a dummy read function into "spl_load_simple_fit()". As the load address is no longer hard-coded to the final execution address, RAW image loading will rely on "load_addr" pointing to the execution address as they should have before. Signed-off-by: Andrew F. Davis <afd(a)ti.com> --- changes from v1: - move "spl_net_load_read" into #ifdef block as suggested by Vignesh common/spl/spl_net.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c index 0fba0172ea..3d1d05d833 100644 --- a/common/spl/spl_net.c +++ b/common/spl/spl_net.c @@ -11,19 +11,29 @@ #include <errno.h> #include <spl.h> #include <net.h> +#include <libfdt.h> DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT) +static ulong spl_net_load_read(struct spl_load_info *load, ulong sector, + ulong count, void *buf) +{ + debug("%s: sector %lx, count %lx, buf %lx\n", + __func__, sector, count, (ulong)buf); + memcpy(buf, (void *)(load_addr + sector), count); + return count; +} + static int spl_net_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { + struct image_header *header = (struct image_header *)load_addr; int rv; env_init(); env_relocate(); setenv("autoload", "yes"); - load_addr = CONFIG_SYS_TEXT_BASE - sizeof(struct image_header); rv = eth_initialize(); if (rv == 0) { printf("No Ethernet devices found\n"); @@ -36,8 +46,22 @@ static int spl_net_load_image(struct spl_image_info *spl_image, printf("Problem booting with BOOTP\n"); return rv; } - return spl_parse_image_header(spl_image, - (struct image_header *)load_addr); + + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && + image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + debug("Found FIT\n"); + load.bl_len = 1; + load.read = spl_net_load_read; + rv = spl_load_simple_fit(spl_image, &load, 0, header); + } else { + debug("Legacy image\n"); + + rv = spl_parse_image_header(spl_image, header); + } + + return rv; } #endif -- 2.11.0

2 2

[U-Boot] [PATCH v3 0/8] Add workaround for USB PHY errata
by Suresh Gupta 16 Feb '17

16 Feb '17

The patch set implement USB PHY errata workaround which are required for LS series of freescale platforms which have Synopsis UTMI PHY Suresh Gupta (8): armv8: Add workaround for USB erratum A-009008 armv8: Add workaround for USB erratum A-009798 armv8: Add workaround for USB erratum A-008997 armv8: Add workaround for USB erratum A-009007 armv7: Add workaround for USB erratum A-009008 armv7: Add workaround for USB erratum A-009798 armv7: Add workaround for USB erratum A-008997 armv7: Add workaround for USB erratum A-009007 arch/arm/cpu/armv7/ls102xa/Kconfig | 16 +++ arch/arm/cpu/armv7/ls102xa/soc.c | 51 +++++++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 +++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 117 +++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 20 ++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 13 +++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 19 ++++ 7 files changed, 260 insertions(+) -- 1.9.3

2 9

[U-Boot] [RFC PATCH] armv8: Extend modification of MMU tables
by York Sun 16 Feb '17

16 Feb '17

Device memory needs to be set along with PXN and UNX bits. Normal memory must clear these bits. To support modification of PXN, UXN bits, extend existing function mmu_set_region_dcache_behaviour() to accept attributes directly. Also fix parsing d-cache option by removing extra shifting. Signed-off-by: York Sun <york.sun(a)nxp.com> CC: Alexander Graf <agraf(a)suse.de> --- Looks like original function mmu_set_region_dcache_behaviour() was written to support changing d-cache option. However the PMD_ATTRINDX(option) shifts it further higher. Maybe this function wasn't really used for ARMv8. I have a need to update existing MMU table with a little bit more than d-cache options. With a recent debug on memory barrier, it came to my attention that code should run on "normal" memory, while "device" memory should have PXN and UXN bits set. A new function mmu_set_region_attr() is hence introduced and mmu_set_region_dcache_behaviour() becomes a wrapper. BTW, if we don't plan to use "read_start" and "real_size" variables, they should be removed. arch/arm/cpu/armv8/cache_v8.c | 28 +++++++++++++++++++--------- arch/arm/include/asm/armv8/mmu.h | 1 + arch/arm/include/asm/system.h | 1 + 3 files changed, 21 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index afa76c1..3b2f3f8 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -509,8 +509,8 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, int level) /* Can we can just modify the current level block PTE? */ if (is_aligned(start, size, levelsize)) { - *pte &= ~PMD_ATTRINDX_MASK; - *pte |= attrs; + *pte &= ~PMD_ATTRMASK; + *pte |= attrs & PMD_ATTRMASK; debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level); return levelsize; @@ -532,13 +532,8 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, int level) return 0; } -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option) +void mmu_set_region_attr(phys_addr_t start, size_t size, u64 attrs) { - u64 attrs = PMD_ATTRINDX(option); - u64 real_start = start; - u64 real_size = size; - debug("start=%lx size=%lx\n", (ulong)start, (ulong)size); if (!gd->arch.tlb_emerg) @@ -572,7 +567,19 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, } /* We're done modifying page tables, switch back to our primary ones */ + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); __asm_switch_ttbr(gd->arch.tlb_addr); +} + +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ + u64 attrs = option; + u64 real_start = start; + u64 real_size = size; + + mmu_set_region_attr(start, size, attrs); /* * Make sure there's nothing stale in dcache for a region that might @@ -580,7 +587,6 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, */ flush_dcache_range(real_start, real_start + real_size); } - #else /* CONFIG_SYS_DCACHE_OFF */ /* @@ -613,6 +619,10 @@ int dcache_status(void) return 0; } +void mmu_set_region_attr(phys_addr_t start, size_t size, u64 attrs) +{ +} + void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option) { diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 58aecb9..c1cff23 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -86,6 +86,7 @@ */ #define PMD_ATTRINDX(t) ((t) << 2) #define PMD_ATTRINDX_MASK (7 << 2) +#define PMD_ATTRMASK (PTE_BLOCK_PXN | PTE_BLOCK_UXN | PMD_ATTRINDX_MASK) /* * TCR flags. diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index dc4c991..81709ec 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -224,6 +224,7 @@ void protect_secure_region(void); void smp_kick_all_cpus(void); void flush_l3_cache(void); +void mmu_set_region_attr(phys_addr_t start, size_t size, u64 attrs); /* *Issue a secure monitor call in accordance with ARM "SMC Calling convention", -- 2.7.4

3 4

[U-Boot] [PATCH v5 0/6] Allow disabling non-FIT image loading from SPL
by Andrew F. Davis 16 Feb '17

16 Feb '17

Hello all, To address a needed feature brought up by Andreas[0], we need a way to disable SPL from loading non-FIT images. The function spl_parse_image_header is common to all SPL loading paths (common/spl/spl_(nand|net|nor|etc..)) so we add the check here. This version of the series is a bit different than the last 2 due to suggestions by Simon, instead of a negative option disabling non-FIT images, we allow the other image format's support to be toggled off, and do that on HS boards. Thanks, Andrew [0] https://www.mail-archive.com/u-boot@lists.denx.de/msg219253.html Changes from v4: - Finish conversion of SPL_RAW_IMAGE_SUPPORT Changes from v3: - Add debug print as suggested by Simon Andrew F. Davis (6): spl: Convert CONFIG_SPL_ABORT_ON_RAW_IMAGE into a positive option spl: Add option to enable SPL Legacy image support ARM: AM335x: Disable non-FIT based image loading for HS devices ARM: AM43xx: Disable non-FIT based image loading for HS devices ARM: AM57xx: Disable non-FIT based image loading for HS devices ARM: DRA7xx: Disable non-FIT based image loading for HS devices Kconfig | 15 +++++++++++++++ README | 4 ---- common/spl/spl.c | 20 ++++++++++++++------ configs/am335x_hs_evm_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am57xx_hs_evm_defconfig | 2 ++ configs/apalis_imx6_defconfig | 1 + configs/cgtqmx6eval_defconfig | 1 + configs/cm_fx6_defconfig | 1 + configs/colibri_imx6_defconfig | 1 + configs/dra7xx_hs_evm_defconfig | 2 ++ configs/gwventana_defconfig | 1 + configs/imx6dl_icore_mmc_defconfig | 1 + configs/imx6dl_icore_rqs_mmc_defconfig | 1 + configs/imx6q_icore_mmc_defconfig | 1 + configs/imx6q_icore_rqs_mmc_defconfig | 1 + configs/imx6ul_geam_mmc_defconfig | 1 + configs/liteboard_defconfig | 1 + configs/mccmon6_sd_defconfig | 1 + configs/mx6cuboxi_defconfig | 1 + configs/mx6sabresd_spl_defconfig | 1 + configs/mx6slevk_spl_defconfig | 1 + configs/mx6sxsabresd_spl_defconfig | 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/novena_defconfig | 1 + configs/pcm058_defconfig | 1 + configs/platinum_picon_defconfig | 1 + configs/platinum_titanium_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/udoo_defconfig | 1 + configs/udoo_neo_defconfig | 1 + configs/wandboard_defconfig | 1 + configs/xpress_spl_defconfig | 1 + configs/zc5202_defconfig | 1 + configs/zc5601_defconfig | 1 + include/configs/imx6_spl.h | 2 -- include/configs/socfpga_de1_soc.h | 2 -- include/spl.h | 2 +- 39 files changed, 67 insertions(+), 15 deletions(-) -- 2.11.0

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