February 2017 - U-Boot

[U-Boot] [PATCH v2] armv7m: Add SysTick timer driver
by Phil Edworthy 16 Feb '17

16 Feb '17

The SysTick is a 24-bit down counter that is found on all ARM Cortex M3, M4, M7 devices and is always located at a fixed address. Signed-off-by: Phil Edworthy <phil.edworthy(a)renesas.com> --- v2: - Variables & constant renamed. - Use the calibration reg to determine if we use the cpu or ref clk - Use the calibration reg to get the clk rate, unless specified --- arch/arm/cpu/armv7m/Makefile | 2 + arch/arm/cpu/armv7m/systick-timer.c | 107 ++++++++++++++++++++++++++++++++++++ 2 files changed, 109 insertions(+) create mode 100644 arch/arm/cpu/armv7m/systick-timer.c diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile index aff60e8..e1a6c40 100644 --- a/arch/arm/cpu/armv7m/Makefile +++ b/arch/arm/cpu/armv7m/Makefile @@ -7,3 +7,5 @@ extra-y := start.o obj-y += cpu.o + +obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o diff --git a/arch/arm/cpu/armv7m/systick-timer.c b/arch/arm/cpu/armv7m/systick-timer.c new file mode 100644 index 0000000..62308f9 --- /dev/null +++ b/arch/arm/cpu/armv7m/systick-timer.c @@ -0,0 +1,107 @@ +/* + * ARM Cortex M3/M4/M7 SysTick timer driver + * (C) Copyright 2017 Renesas Electronics Europe Ltd + * + * Based on arch/arm/mach-stm32/stm32f1/timer.c + * (C) Copyright 2015 + * Kamil Lulko, <kamil.lulko(a)gmail.com> + * + * Copyright 2015 ATS Advanced Telematics Systems GmbH + * Copyright 2015 Konsulko Group, Matt Porter <mporter(a)konsulko.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * The SysTick timer is a 24-bit count down timer. The clock can be either the + * CPU clock or a reference clock. Since the timer will wrap around very quickly + * when using the CPU clock, and we do not handle the timer interrupts, it is + * expected that this driver is only ever used with a slow reference clock. + */ + +#include <common.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */ +#define SYSTICK_BASE 0xE000E010 + +struct cm3_systick { + uint32_t ctrl; + uint32_t reload_val; + uint32_t current_val; + uint32_t calibration; +}; + +#define TIMER_MAX_VAL 0x00FFFFFF +#define SYSTICK_CTRL_EN BIT(0) +/* Clock source: 0 = Ref clock, 1 = CPU clock */ +#define SYSTICK_CTRL_CPU_CLK BIT(2) +#define SYSTICK_CAL_NOREF BIT(31) +#define SYSTICK_CAL_SKEW BIT(30) +#define SYSTICK_CAL_TENMS_MASK 0x00FFFFFF + +/* read the 24-bit timer */ +static ulong read_timer(void) +{ + struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE; + + /* The timer counts down, therefore convert to an incrementing timer */ + return TIMER_MAX_VAL - readl(&systick->current_val); +} + +int timer_init(void) +{ + struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE; + u32 cal; + + writel(TIMER_MAX_VAL, &systick->reload_val); + /* Any write to current_val reg clears it to 0 */ + writel(0, &systick->current_val); + + cal = readl(&systick->calibration); + if (cal & SYSTICK_CAL_NOREF) + /* Use CPU clock, no interrupts */ + writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, &systick->ctrl); + else + /* Use external clock, no interrupts */ + writel(SYSTICK_CTRL_EN, &systick->ctrl); + +#if defined(CONFIG_SYS_HZ_CLOCK) + gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; +#else + gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100; +#endif + + gd->arch.tbl = 0; + gd->arch.tbu = 0; + gd->arch.lastinc = read_timer(); + + return 0; +} + +/* return milli-seconds timer value */ +ulong get_timer(ulong base) +{ + unsigned long long t = get_ticks() * 1000; + + return (ulong)((t / gd->arch.timer_rate_hz)) - base; +} + +unsigned long long get_ticks(void) +{ + u32 now = read_timer(); + + if (now >= gd->arch.lastinc) + gd->arch.tbl += (now - gd->arch.lastinc); + else + gd->arch.tbl += (TIMER_MAX_VAL - gd->arch.lastinc) + now; + + gd->arch.lastinc = now; + + return gd->arch.tbl; +} + +ulong get_tbclk(void) +{ + return gd->arch.timer_rate_hz; +} -- 2.7.4

2 3

[U-Boot] [PATCH 0/9] arm64: Unify MMU code
by Alexander Graf 16 Feb '17

16 Feb '17

Howdy, Currently on arm64 there is a big pile of mess when it comes to MMU support and page tables. Each board does its own little thing and the generic code is pretty dumb and nobody actually uses it. This patch set tries to clean that up. After this series is applied, all boards except for the FSL Layerscape ones are converted to the new generic page table logic and have icache+dcache enabled. The new code always uses 4k page size. It dynamically allocates 1G or 2M pages for ranges that fit. When a dcache attribute request comes in that requires a smaller granularity than our previous allocation could fulfill, pages get automatically split. I have tested and verified the code works on HiKey (bare metal), vexpress64 (Foundation Model) and zynqmp (QEMU). The TX1 target is untested, but given the simplicity of the maps I doubt it'll break. ThunderX in theory should also work, but I haven't tested it. I would be very happy if people with access to those system could give the patch set a try. With this we're a big step closer to a good base line for EFI payload support, since we can now just require that all boards always have dcache enabled. I would also be incredibly happy if some Freescale people could look at their MMU code and try to unify it into the now cleaned up generic code. I don't think we're far off here. Alex Alexander Graf (9): thunderx: Calculate TCR dynamically arm64: Make full va map code more dynamic zymqmp: Replace home grown mmu code with generic table approach tegra: Replace home grown mmu code with generic table approach vexpress64: Add MMU tables dwmmc: Increase retry timeout hikey: Add MMU tables arm64: Remove non-full-va map code arm64: Only allow dcache disabled in SPL builds arch/arm/cpu/armv8/cache_v8.c | 444 ++++++++++++++++++------- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 29 +- arch/arm/cpu/armv8/zynqmp/cpu.c | 169 ---------- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 94 +++--- arch/arm/include/asm/armv8/mmu.h | 120 ++----- arch/arm/include/asm/global_data.h | 6 +- arch/arm/include/asm/system.h | 7 +- arch/arm/mach-tegra/Makefile | 1 - arch/arm/mach-tegra/arm64-mmu.c | 131 -------- doc/README.arm64 | 20 -- drivers/mmc/dw_mmc.c | 2 +- include/configs/hikey.h | 18 +- include/configs/tegra210-common.h | 15 + include/configs/thunderx_88xx.h | 31 +- include/configs/vexpress_aemv8a.h | 19 +- include/configs/xilinx_zynqmp.h | 43 +++ 16 files changed, 526 insertions(+), 623 deletions(-) delete mode 100644 arch/arm/mach-tegra/arm64-mmu.c -- 1.8.5.6

6 49

[U-Boot] Uart boot broken on AM335x-evm
by Lokesh Vutla 16 Feb '17

16 Feb '17

Hi All, I am facing an issue with UART boot on AM335x-evm using latest U-Boot. SPL is not able to download u-boot.img completely. After a bit of debug with the help of Andrew, it is watchdog causing the timeout. If HW_WATCHDOG is disabled, SPL is able to download the image completely and u-boot successfully boots up. After this I could not progress anything. Wondering if anyone else is facing the same issue and any pointers to debug further will be very helpful. Thanks and regards, Lokesh

3 2

[U-Boot] [PATCH v2 0/3] ARM: AM43xx: Enable SPL_DM
by Lokesh Vutla 16 Feb '17

16 Feb '17

Enable SPL_DM on all AM4xx based boards. This series depends on: - DRA7 SPL_DM series[1] - http://patchwork.ozlabs.org/patch/727106/ [1] https://www.mail-archive.com/u-boot@lists.denx.de/msg238751.html Changes since v1: - Fixed build error with non-SPL_DM defconfigs - Increased SYS_MALLOC_F_LEN Lokesh Vutla (3): ARM: dts: am43xx: Add u-boot specific dtsi config: am43xx_usbhost_boot: sync with am43xx_evm configs: am43xx_evm: Enable SPL_DM arch/arm/dts/am437x-gp-evm-u-boot.dtsi | 38 +++++++++++++++++++++++++++++++ configs/am43xx_evm_defconfig | 8 ++++++- configs/am43xx_evm_usbhost_boot_defconfig | 13 ++++++++++- configs/am43xx_hs_evm_defconfig | 8 ++++++- include/configs/am43xx_evm.h | 7 ++---- 5 files changed, 66 insertions(+), 8 deletions(-) create mode 100644 arch/arm/dts/am437x-gp-evm-u-boot.dtsi -- 2.11.0

2 4

Re: [U-Boot] [PATCH v3 3/3] sunxi: add support for Lichee Pi Zero
by Icenowy Zheng 16 Feb '17

16 Feb '17

2017年2月13日 15:17于 Maxime Ripard <maxime.ripard(a)free-electrons.com>写道： > > Hi, > > On Sat, Feb 11, 2017 at 07:11:02PM +0800, Icenowy Zheng wrote: > > @@ -0,0 +1,13 @@ > > +CONFIG_ARM=y > > +CONFIG_ARCH_SUNXI=y > > +# CONFIG_ARMV7_NONSEC is not set > > Why? It doesn't have Trustzone? The CPU has Secure mode, but no TrustZone Peripheral Controller, neither SMP. > > Thanks, > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com

4 4

Re: [U-Boot] [PATCH 4/9] armv8: layerscape: Rewrite memory reservation
by york sun 15 Feb '17

15 Feb '17

On 02/14/2017 09:00 AM, york.sun(a)nxp.com wrote: > On 02/14/2017 07:31 AM, Alexander Graf wrote: >> >> >> On 14/02/2017 04:45, York Sun wrote: >>> For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved >>> at the end of DDR. DDR is spit into two or three banks. This patch >>> reverts commit aabd7ddb and simplifies the calculation of reserved >>> memory, and moves the code into common SoC file. Secure memory is >>> carved out first. DDR bank size is reduced. Reserved memory is then >>> allocated on the top of available memory. U-Boot still has access >>> to reserved memory as data transferring is needed. Device tree is >>> fixed with reduced memory size to hide the reserved memory from OS. >> >> I haven't looked in detail, but could you please ensure that you also >> reserve those regions in the efi_loader memory map? > > I missed efi reserved memory map. Will add in v2 patch. > Alex, Is the misc_init_r() the best place to add such reservation under your code dealing with DP_DDR? It is per board code. As of now, we only have ls2080ardb with efi boot. York

2 4

[U-Boot] [PATCH v4 0/6] Allow disabling non-FIT image loading from SPL
by Andrew F. Davis 15 Feb '17

15 Feb '17

Hello all, To address a needed feature brought up by Andreas[0], we need a way to disable SPL from loading non-FIT images. The function spl_parse_image_header is common to all SPL loading paths (common/spl/spl_(nand|net|nor|etc..)) so we add the check here. This version of the series is a bit different than the last 2 due to suggestions by Simon, instead of a negative option disabling non-FIT images, we allow the other image format's support to be toggled off, and do that on HS boards. Thanks, Andrew [0] https://www.mail-archive.com/u-boot@lists.denx.de/msg219253.html Changes from v3: - Add debug print as suggested by Simon Andrew F. Davis (6): spl: Convert CONFIG_SPL_ABORT_ON_RAW_IMAGE into a positive option spl: Add option to enable SPL Legacy image support ARM: AM335x: Disable non-FIT based image loading for HS devices ARM: AM43xx: Disable non-FIT based image loading for HS devices ARM: AM57xx: Disable non-FIT based image loading for HS devices ARM: DRA7xx: Disable non-FIT based image loading for HS devices Kconfig | 15 +++++++++++++++ README | 4 ---- common/spl/spl.c | 20 ++++++++++++++------ configs/am335x_hs_evm_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am57xx_hs_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ include/configs/imx6_spl.h | 4 ++-- include/configs/socfpga_de1_soc.h | 2 +- include/spl.h | 2 +- 10 files changed, 41 insertions(+), 14 deletions(-) -- 2.11.0

2 15

[U-Boot] [PATCH 00/10] Add Marvell ESPRESSOBin community board support
by kostap＠marvell.com 15 Feb '17

15 Feb '17

From: Konstantin Porotchkin <kostap(a)marvell.com> This patch set adds support for Marvell ESPRESSOBin community board. The Marvell ESPRESSOBin is a tiny board made by Globalscale and available on KickStarter site. It has (current board version 3.1.1): - Dual core Cortex-A53 @1.2GHz CPU (Marvell Armada-3720) - 512MB/1GB/2GB DDR3 RAM (depends on selected configuration) - Mini-PCIe 2.0 slot - Single SATA-3 port with Molex SATA power connector - USB 2.0 port - USB 3.0 port - Gigabit Ethernet switch with 3 ports - Micro-SD socket - Two 46-pin GPIO connectors. - SPI boot flash - Boot source selection jumpers (SPI/SATA/UART/Auto) - Micro JTAG connector (10 pin) - Micro USB serial port Konstantin Porotchkin (10): arm64: a37xx: Enable Marvell ETH PHY support arm64: a37xx: Enable bubt command support on A3720-DB arm64: a37xx: dts: Add pin control nodes to DT arm64: a37xx: Handle pin controls in early board init mvebu: neta: Add support for board init function mvebu: neta: a37xx: Add fixed link support to neta driver mvebu: a37xx: Add init for ESPRESSBin Topaz switch arm64: dts: Add device tree for ESPRESSOBin board arm64: mvebu: Add default config for ESPRESSOBin board arm64: a3720: Disable DB configurations on ESPRESSOBin board arch/arm/dts/Makefile | 1 + arch/arm/dts/armada-3720-espressobin.dts | 135 ++++++++++++++++++++++++++++ arch/arm/dts/armada-37xx.dtsi | 14 +++ board/Marvell/mvebu_db-88f3720/board.c | 83 ++++++++++++++++- configs/mvebu_db-88f3720_defconfig | 3 + configs/mvebu_espressobin-88f3720_defconfig | 67 ++++++++++++++ drivers/net/mvneta.c | 125 ++++++++++++++++++++------ include/configs/mvebu_db-88f3720.h | 1 + 8 files changed, 400 insertions(+), 29 deletions(-) create mode 100644 arch/arm/dts/armada-3720-espressobin.dts create mode 100644 configs/mvebu_espressobin-88f3720_defconfig -- 2.7.4

4 22

[U-Boot] [PATCH 1/1] Secure Boot: Set NPSWA_EN bit for SNVS state transition to happen in EL2.
by Udit Agarwal 15 Feb '17

15 Feb '17

For Layerscape chasis Gen 3 based platforms, during PPA execution exception level transition happens from EL3 to EL2. While in EL2 state SNVS state doesnot changes from secure to non secure state in case of ESBC failure. So to enable the SNVS transition in EL2 state, NPSWA_EN bit has to be set when in EL3 state. Signed-off-by: Udit Agarwal <udit.agarwal(a)nxp.com> --- drivers/crypto/fsl/jr.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 1b88229..ccd2168 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -8,6 +8,7 @@ #include <common.h> #include <malloc.h> +#include <fsl_sec_mon.h> #include "fsl_sec.h" #include "jr.h" #include "jobdesc.h" @@ -574,6 +575,12 @@ int sec_init_idx(uint8_t sec_idx) uint32_t liodn_s; #endif +#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_LS_PPA_ESBC_ADDR) +#define SEC_MON_HPCOMR (CONFIG_SYS_SEC_MON_ADDR + 0x04) +#define SEC_MON_HPCOMR_NPSWA_EN 0x80000000 + sec_mon_setbits32(SEC_MON_HPCOMR, SEC_MON_HPCOMR_NPSWA_EN); +#endif + if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) { printf("SEC initialization failed\n"); return -1; -- 1.9.1

2 1

[U-Boot] [PATCH] sunxi: Add defconfig for Allwinner A23 EVB
by Florent Jacquet 15 Feb '17

15 Feb '17

This enables the support for the Allwinner A23 Evaluation Board (EVB), that already had a device tree (from Linux) but no defconfig. This board has an AXP223 PMIC, some NAND, Audio out and in plugs, an accelerometer and light sensor, as well as a USB HSIC hub and a USB OTG mini-USB connector. It also has a Wifi/BT chip. Access to the other buses (LCD, MIPI DSI, LVDS, etc) can be done through dedicated pin headers. Signed-off-by: Florent Jacquet <florent.jacquet(a)free-electrons.com> --- configs/sun8i_a23_evb_defconfig | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 configs/sun8i_a23_evb_defconfig diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig new file mode 100644 index 0000000..296df00 --- /dev/null +++ b/configs/sun8i_a23_evb_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A23=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=63351 +CONFIG_USB0_VBUS_PIN="axp_drivebus" +CONFIG_USB0_VBUS_DET="axp_vbus_detect" +CONFIG_USB1_VBUS_PIN="PH7" +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-evb" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_EHCI_HCD=y -- 2.7.4

1 0