January 2017 - U-Boot

[U-Boot] Pull request: u-boot-sunxi/master
by Jagan Teki 11 Jan '17

11 Jan '17

Hi Tom, Please take this PR. thanks! Jagan. The following changes since commit 87f5f5417fc897df0b05826b408f0f4b7d2ee388: Prepare v2017.01-rc3 (2017-01-02 20:00:55 -0500) are available in the git repository at: git://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to eb77f5c9f69ef6c8cb39643b7b7107ef7bff5305: sunxi: A64: enable SPL (2017-01-04 16:37:43 +0100) ---------------------------------------------------------------- Andre Przywara (16): sun6i: Restrict some register initialization to Allwinner A31 SoC armv8: prevent using THUMB armv8: add lowlevel_init.S SPL: tiny-printf: add "l" modifier SPL: tiny-printf: ignore "-" modifier move UL() macro from armv8/mmu.h into common.h SPL: make struct spl_image 64-bit safe armv8: add simple sdelay implementation armv8: move reset branch into boot hook ARM: boot0 hook: remove macro, include whole header file sunxi: introduce extra config option for boot0 header sunxi: A64: do an RMR switch if started in AArch32 mode sunxi: provide default DRAM config for sun50i in Kconfig sunxi: H3/A64: fix non-ODT setting sunxi: DRAM: fix H3 DRAM size display on aarch64 sunxi: A64: enable SPL Jens Kuske (3): sunxi: H3: add and rename some DRAM contoller registers sunxi: H3: add DRAM controller single bit delay support sunxi: A64: use H3 DRAM initialization code for A64 as well Philipp Tomsich (2): sunxi: H3: Rework MBUS priority setup sunxi: clocks: Use the correct pattern register for PLL11 Priit Laes (1): spl: sunxi: Fix build error with CONFIG_SPL_SPI_SUNXI arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/cpu.c | 14 + arch/arm/cpu/armv8/lowlevel_init.S | 44 +++ arch/arm/cpu/armv8/start.S | 5 +- arch/arm/include/asm/arch-bcm235xx/boot0.h | 8 +- arch/arm/include/asm/arch-bcm281xx/boot0.h | 8 +- arch/arm/include/asm/arch-sunxi/boot0.h | 37 ++- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + arch/arm/include/asm/arch-sunxi/cpu.h | 3 + arch/arm/include/asm/arch-sunxi/dram.h | 2 +- arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h | 53 ++-- arch/arm/include/asm/armv8/mmu.h | 8 - arch/arm/lib/Makefile | 2 + arch/arm/lib/vectors.S | 1 - arch/arm/mach-omap2/boot-common.c | 2 +- arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/board.c | 2 +- arch/arm/mach-sunxi/clock_sun6i.c | 10 +- arch/arm/mach-sunxi/dram_sun8i_h3.c | 400 +++++++++++++++++------- arch/arm/mach-sunxi/rmr_switch.S | 41 +++ arch/arm/mach-tegra/spl.c | 2 +- board/sunxi/Kconfig | 27 ++ common/spl/spl.c | 8 +- common/spl/spl_mmc.c | 2 +- configs/pine64_plus_defconfig | 5 +- drivers/mtd/spi/sunxi_spi_spl.c | 2 +- include/common.h | 13 +- include/configs/sunxi-common.h | 4 +- include/spl.h | 4 +- lib/tiny-printf.c | 50 ++- 30 files changed, 564 insertions(+), 196 deletions(-) create mode 100644 arch/arm/cpu/armv8/lowlevel_init.S create mode 100644 arch/arm/mach-sunxi/rmr_switch.S

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[U-Boot] Please pull u-boot-dm
by Simon Glass 11 Jan '17

11 Jan '17

Hi Tom, The following changes since commit a705ebc81b7f91bbd0ef7c634284208342901149: Prepare v2017.01 (2017-01-09 11:57:05 -0500) are available in the git repository at: git://git.denx.de/u-boot-dm.git for you to fetch changes up to f8f41ae668040d58271e03bc85b58e13becb14af: scsi: dm: Unbind all scsi based block devices before new scan (2017-01-09 11:25:20 -0700) ---------------------------------------------------------------- Michal Simek (1): scsi: dm: Unbind all scsi based block devices before new scan Mugunthan V N (4): drivers: usb: gadget: ether/rndis: convert driver to adopt device driver model am33xx: board: init usb ether gadget for rndis support am335x_evm: enable usb ether gadget as it supports DM_ETH defconfig: am335x_evm: enable usb driver model arch/arm/mach-omap2/am33xx/board.c | 8 +++++ common/scsi.c | 2 ++ configs/am335x_evm_defconfig | 3 ++ drivers/usb/gadget/Kconfig | 4 +++ drivers/usb/gadget/ether.c | 153 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------ drivers/usb/gadget/rndis.c | 13 ++++++-- drivers/usb/gadget/rndis.h | 19 +++++++++--- include/configs/am335x_evm.h | 3 -- include/net.h | 7 +++++ 9 files changed, 194 insertions(+), 18 deletions(-) Regards, Simon

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[U-Boot] [PATCH 0/4] imx6: Engicam i.CoreM6 eMMC boot support
by Jagan Teki 11 Jan '17

11 Jan '17

From: Jagan Teki <jagan(a)amarulasolutions.com> This series support boot from eMMC on Engicam i.CoreM6 QDL boards. i.CoreM6 QDL boards, support both eSD and eMMC this patch-set add eMMC support from SPL. but the issue is - SD card (eSD) is not detecting when booting from eMMC but - SD card along with eMMC is able to detect while booting from eSD If any one tried this please help. Log: --- U-Boot SPL 2017.01-00005-g5986ea7-dirty (Jan 10 2017 - 23:56:16) Trying to boot from MMC2 U-Boot 2017.01-00005-g5986ea7-dirty (Jan 10 2017 - 23:56:16 +0100) CPU: Freescale i.MX6D rev1.2 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 mmc_init: -70, time 38 *** Warning - MMC init failed, using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs> icorem6qdl-rqs> mmc dev 0 mmc_init: -70, time 38 icorem6qdl-rqs> mmc dev 1 switch to partitions #0, OK mmc1(part 0) is current device icorem6qdl-rqs> mmcinfo Device: FSL_SDHC Manufacturer ID: fe OEM: 14e Name: MMC04 Tran Speed: 52000000 Rd Block Len: 512 MMC version 4.4.1 High Capacity: Yes Capacity: 3.5 GiB Bus Width: 4-bit Erase Group Size: 512 KiB HC WP Group Size: 4 MiB User Capacity: 3.5 GiB Boot Capacity: 16 MiB ENH RPMB Capacity: 128 KiB ENH icorem6qdl-rqs> Jagan Teki (4): arm: dts: imx6qdl-icore-rqs: Add eMMC node imx6: Add imx6_src_get_boot_mode imx6: icorem6_rqs: Update SPL board boot order for mmc imx6: icorem6_rqs: Add eMMC boot support arch/arm/dts/imx6qdl-icore-rqs.dtsi | 22 ++++++++++++++ arch/arm/imx-common/init.c | 22 ++++++++++++++ arch/arm/imx-common/spl.c | 6 ++-- arch/arm/include/asm/arch-mx6/sys_proto.h | 5 ++++ board/engicam/icorem6_rqs/MAINTAINERS | 1 + board/engicam/icorem6_rqs/icorem6_rqs.c | 50 +++++++++++++++++++++++++++++-- configs/imx6q_icore_rqs_emmc_defconfig | 38 +++++++++++++++++++++++ include/configs/imx6qdl_icore_rqs.h | 2 +- 8 files changed, 140 insertions(+), 6 deletions(-) create mode 100644 configs/imx6q_icore_rqs_emmc_defconfig -- 1.9.1

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[U-Boot] [PATCH] xilinx_phy: Pass correct pointer to fdtdec_get_int()
by Michal Simek 10 Jan '17

10 Jan '17

From: Kamensky Ivan <kamensky.ivan(a)mail.ru> This patch fixes incorrect pointer on offset device in device tree blob. When using with the component "Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII" it does not understand what type is XAE_PHY_TYPE_1000BASE_X and trying to change frequency. Signed-off-by: Kamensky Ivan <kamensky.ivan(a)mail.ru> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/phy/xilinx_phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c index f3eaf2e97ced..920bfcb380b3 100644 --- a/drivers/net/phy/xilinx_phy.c +++ b/drivers/net/phy/xilinx_phy.c @@ -101,11 +101,11 @@ static int xilinxphy_startup(struct phy_device *phydev) static int xilinxphy_of_init(struct phy_device *phydev) { - struct udevice *dev = (struct udevice *)&phydev->dev; u32 phytype; debug("%s\n", __func__); - phytype = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "phy-type", -1); + phytype = fdtdec_get_int(gd->fdt_blob, phydev->dev->of_offset, + "phy-type", -1); if (phytype == XAE_PHY_TYPE_1000BASE_X) phydev->flags |= XAE_PHY_TYPE_1000BASE_X; -- 1.9.1

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Re: [U-Boot] [PATCH] sunxi: makes an invisible option for H3-like DRAM controllers
by Icenowy Zheng 10 Jan '17

10 Jan '17

2017年1月9日下午7:06于 Maxime Ripard <maxime.ripard(a)free-electrons.com>写道： > > On Fri, Jan 06, 2017 at 07:13:17AM +0800, Icenowy Zheng wrote: > > > > > > 06.01.2017, 06:16, "Maxime Ripard" <maxime.ripard(a)free-electrons.com>: > > > On Thu, Dec 29, 2016 at 02:50:48AM +0800, Icenowy Zheng wrote: > > >> Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like > > >> DesignWare DRAM controller, which do not have official free DRAM > > >> initialization code, but can use modified dram_sun8i_h3.c. > > >> > > >> Add a invisible option for easier DRAM initialization code reuse. > > > > > > Since it's used on all the newer SoCs, do we need to keep the H3 name > > > in the config option name? > > > > Good question... > > > > Name it "SUNXI_DW_DRAM"? > > Looks good. > > > (Although I think at least A33 uses the same series of DRAM controller) > > Does it? Why do we need a separate DRAM init code then? I think it does. See dram_sun8i_a33.c . We used to use per-device dram code, but failed after allwinner uses libdram, then we worked on modifying H3 code. I think it's also possible to make H3 code capable of A33, but since our A33 code works well, should we do it? > > Thanks, > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com

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[U-Boot] [PATCH] ARM64: zynqmp: Move CONFIG_AHCI from board file
by Michal Simek 10 Jan '17

10 Jan '17

Move configuration option from board file to defconfig. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 + include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index f4307a494f39..41fcc8dc99c9 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -6,6 +6,7 @@ CONFIG_ZYNQMP_USB=y CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm015 dc1" CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1" +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h index b19a55219aa0..e3797a8efdc3 100644 --- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h +++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h @@ -12,7 +12,6 @@ #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_SDHCI1 -#define CONFIG_AHCI #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} #include <configs/xilinx_zynqmp.h> -- 1.9.1

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[U-Boot] [PATCH] mx6sx: Add initial support for UDOO Neo Board
by Breno Lima 10 Jan '17

10 Jan '17

UDOO Neo Board is a development board from Seco that has three models: - UDOO Neo Basic - UDOO Neo Basic Kick Starter - UDOO Neo Extended - UDOO Neo Full All versions are based on the i.MX6 SoloX processor. For more details about the UDOO Neo board, please refer to: http://www.udoo.org/udoo-neo/ This work is based on a previous commit of Francesco Montefoschi <francesco.monte(a)gmail.com>: https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed57496… Only tested on the UDOO Neo Full board. Signed-off-by: Breno Lima <breno.lima(a)nxp.com> --- arch/arm/cpu/armv7/mx6/Kconfig | 5 + board/udoo/neo/Kconfig | 12 ++ board/udoo/neo/MAINTAINERS | 7 + board/udoo/neo/Makefile | 6 + board/udoo/neo/neo.c | 441 +++++++++++++++++++++++++++++++++++++++++ configs/udoo_neo_defconfig | 30 +++ include/configs/udoo_neo.h | 94 +++++++++ 7 files changed, 595 insertions(+) create mode 100644 board/udoo/neo/Kconfig create mode 100644 board/udoo/neo/MAINTAINERS create mode 100644 board/udoo/neo/Makefile create mode 100644 board/udoo/neo/neo.c create mode 100644 configs/udoo_neo_defconfig create mode 100644 include/configs/udoo_neo.h diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 762a581..ea8b693 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -192,6 +192,10 @@ config TARGET_UDOO bool "udoo" select SUPPORT_SPL +config TARGET_UDOO_NEO + bool "UDOO Neo" + select SUPPORT_SPL + config TARGET_WANDBOARD bool "wandboard" select SUPPORT_SPL @@ -253,6 +257,7 @@ source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/udoo/Kconfig" +source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" diff --git a/board/udoo/neo/Kconfig b/board/udoo/neo/Kconfig new file mode 100644 index 0000000..8f474df --- /dev/null +++ b/board/udoo/neo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_UDOO_NEO + +config SYS_VENDOR + default "udoo" + +config SYS_BOARD + default "neo" + +config SYS_CONFIG_NAME + default "udoo_neo" + +endif diff --git a/board/udoo/neo/MAINTAINERS b/board/udoo/neo/MAINTAINERS new file mode 100644 index 0000000..743fe33 --- /dev/null +++ b/board/udoo/neo/MAINTAINERS @@ -0,0 +1,7 @@ +UDOO NEO BOARD +M: Breno Lima <breno.lima(a)nxp.com> +M: Francesco Montefoschi <francesco.montefoschi(a)udoo.org> +S: Maintained +F: board/udoo/neo/ +F: include/configs/udoo_neo.h +F: configs/udoo_neo_defconfig diff --git a/board/udoo/neo/Makefile b/board/udoo/neo/Makefile new file mode 100644 index 0000000..150cbc1 --- /dev/null +++ b/board/udoo/neo/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 UDOO Team +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := neo.o diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c new file mode 100644 index 0000000..7f17469 --- /dev/null +++ b/board/udoo/neo/neo.c @@ -0,0 +1,441 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright (C) Jasbir Matharu + * Copyright (C) UDOO Team + * + * Author: Breno Lima <breno.lima(a)nxp.com> + * Author: Francesco Montefoschi <francesco.monte(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <spl.h> +#include <linux/sizes.h> +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum { + UDOO_NEO_TYPE_BASIC, + UDOO_NEO_TYPE_BASIC_KS, + UDOO_NEO_TYPE_FULL, + UDOO_NEO_TYPE_EXTENDED, +}; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) +#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \ + MUX_MODE_SION) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD pin */ + MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Power */ + MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const board_recognition_pads[] = { + /*Connected to R184*/ + MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG, + /*Connected to R185*/ + MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG, +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + /* Configured for WLAN */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_b_pad = { + MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const peri_3v3_pads[] = { + MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* + * Because kernel set WDOG_B mux before pad with the commone pinctrl + * framwork now and wdog reset will be triggered once set WDOG_B mux + * with default pad setting, we set pad setting here to workaround this. + * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set + * as GPIO mux firstly here to workaround it. + */ + imx_iomux_v3_setup_pad(wdog_b_pad); + + /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ + imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, + ARRAY_SIZE(peri_3v3_pads)); + + /* Active high for ncp692 */ + gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); + + return 0; +} + +static int get_board_value(void) +{ + int r184, r185; + + imx_iomux_v3_setup_multiple_pads(board_recognition_pads, + ARRAY_SIZE(board_recognition_pads)); + + gpio_direction_input(IMX_GPIO_NR(4, 13)); + gpio_direction_input(IMX_GPIO_NR(4, 0)); + + r184 = gpio_get_value(IMX_GPIO_NR(4, 13)); + r185 = gpio_get_value(IMX_GPIO_NR(4, 0)); + + /* + * Machine selection - + * Machine r184, r185 + * --------------------------------- + * Basic 0 0 + * Basic Ks 0 1 + * Full 1 0 + * Extended 1 1 + */ + + return (r184 << 1) + r185; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1) +#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_SPL_BUILD + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers\ + (%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning:\ + failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +#else + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + if ((val & 0xc0) != 0x40) { + printf("Not boot from USDHC!\n"); + return -EINVAL; + } + + port = (val >> 11) & 0x3; + printf("port %d\n", port); + switch (port) { + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + break; + } + + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif +} + +char *board_string(void) +{ + switch (get_board_value()) { + case UDOO_NEO_TYPE_BASIC: + return "BASIC"; + case UDOO_NEO_TYPE_BASIC_KS: + return "BASICKS"; + case UDOO_NEO_TYPE_FULL: + return "FULL"; + case UDOO_NEO_TYPE_EXTENDED: + return "EXTENDED"; + } + return "UNDEFINED"; +} + +int checkboard(void) +{ + printf("Board: UDOO Neo %s\n", board_string()); + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + setenv("board_name", board_string()); +#endif + + return 0; +} + +#ifdef CONFIG_SPL_BUILD + +#include <libfdt.h> +#include <asm/arch/mx6-ddr.h> + +static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_ras = 0x00000020, + .dram_cas = 0x00000020, + .dram_odt0 = 0x00000020, + .dram_odt1 = 0x00000020, + .dram_sdba2 = 0x00000000, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_reset = 0x00000020, +}; + +static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000020, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_ctlds = 0x00000020, + .grp_ddr_type = 0x000c0000, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, +}; + +static const struct mx6_mmdc_calibration neo_mmcd_calib = { + .p0_mpwldectrl0 = 0x000E000B, + .p0_mpwldectrl1 = 0x000E0010, + .p0_mpdgctrl0 = 0x41600158, + .p0_mpdgctrl1 = 0x01500140, + .p0_mprddlctl = 0x3A383E3E, + .p0_mpwrdlctl = 0x3A383C38, +}; + +static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = { + .p0_mpwldectrl0 = 0x001E0022, + .p0_mpwldectrl1 = 0x001C0019, + .p0_mpdgctrl0 = 0x41540150, + .p0_mpdgctrl1 = 0x01440138, + .p0_mprddlctl = 0x403E4644, + .p0_mpwrdlctl = 0x3C3A4038, +}; + +/* MT41K256M16 */ +static struct mx6_ddr3_cfg neo_mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* MT41K128M16 */ +static struct mx6_ddr3_cfg neo_basic_mem_ddr = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + int board = get_board_value(); + + struct mx6_ddr_sysinfo sysinfo = { + .dsize = 1, /* width of data bus: 1 = 32 bits */ + .cs_density = 24, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); + if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS) + mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib, + &neo_basic_mem_ddr); + else + mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +#endif diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig new file mode 100644 index 0000000..3304afb --- /dev/null +++ b/configs/udoo_neo_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_UDOO_NEO=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_DHCP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h new file mode 100644 index 0000000..81e0481 --- /dev/null +++ b/include/configs/udoo_neo.h @@ -0,0 +1,94 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * Copyright Jasbir Matharu + * Copyright 2015 UDOO Team + * + * Configuration settings for the UDOO NEO board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <config_distro_defaults.h> +#include "mx6_common.h" + +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_UART + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* Command definition */ +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/ + +/* Linux only */ +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcrootfstype=ext4\0" \ + "mmcautodetect=no\0" \ + "findfdt="\ + "if test $board_name = BASIC; then " \ + "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \ + "if test $board_name = BASICKS; then " \ + "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \ + "if test $board_name = FULL; then " \ + "setenv fdt_file imx6sx-udoo-neo-full.dtb; fi; " \ + "if test $board_name = EXTENDED; then " \ + "setenv fdt_file imx6sx-udoo-neo-extended.dtb; fi; " \ + "if test $fdt_file = UNDEFINED; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x83000000\0" \ + "ramdiskaddr=0x83000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run distro_bootcmd" + +#include <config_distro_bootcmd.h> + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC + +#endif /* __CONFIG_H */ -- 2.7.4

5 4

[U-Boot] Some discussion about Allwinner DesignWare DRAM controller SPL code cleanup
by Icenowy Zheng 10 Jan '17

10 Jan '17

Hi Jens, Andre, Chen-Yu and everyone, As we know, allwinner start to refuse to provide code about DRAM initialization after H3. For A64, H5, V3s we have already did some work on reusing H3 code and it gives good result. For R40 the result is also usable (although half of the memory is lost) I think we will need some refactor, which will makes the H3 driver finally a SUNXI_DW_DRAM driver ;-) The first thing I want to say is that the DDR timing parameters part needs a lot refactor, for V3s' integrated DDR2, for SoPine's LPDDR3, etc... What I think is to create some header files included by the DRAM driver which defines the timing parameters, and make dram_sun8i_h3.c include them by the choice in .config . The second thing is that, for some alike controller from AW, we have at least source files: dram_sun8i_{a33,h3}.c (A33 uses a similar DW DRAM). Should we merge A33 into the H3 source code? Opinions wanted ;-) Thanks, Icenowy

2 1

Re: [U-Boot] [linux-sunxi] Re: [RFC PATCH 1/4] sunxi: add DDR2 support to H3-like DRAM controller
by Icenowy Zheng 10 Jan '17

10 Jan '17

2017年1月6日 06:37于 Maxime Ripard <maxime.ripard(a)free-electrons.com>写道： > > On Thu, Dec 29, 2016 at 03:00:58AM +0800, Icenowy Zheng wrote: > > H3-like DRAM controller needs some special code to operate a DDR2 DRAM > > chip. Add the logic to probe such a chip. > > > > As there's no commercial boards available now with H3 and DDR2 DRAM, the > > patch is developed and tested on a V3s chip, which has in-package DDR2 > > DRAM. > > > > Signed-off-by: Icenowy Zheng <icenowy(a)aosc.xyz> > > It would have been great if your previous patch renaming the H3 symbol > was part of that serie. > > > --- > > arch/arm/mach-sunxi/dram_sun8i_h3.c | 114 ++++++++++++++++++++++++++++++++++-- > > board/sunxi/Kconfig | 11 ++++ > > 2 files changed, 120 insertions(+), 5 deletions(-) > > > > diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c > > index 8e2527dee1..a48320e01c 100644 > > --- a/arch/arm/mach-sunxi/dram_sun8i_h3.c > > +++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c > > @@ -22,6 +22,9 @@ struct dram_para { > > u8 bus_width; > > u8 dual_rank; > > u8 row_bits; > > +#ifdef CONFIG_SUNXI_H3_DRAM_DDR2 > > + u8 bank_bits; > > +#endif > > }; > > > > static inline int ns_to_t(int nanoseconds) > > @@ -136,36 +139,77 @@ static void mctl_set_timing_params(struct dram_para *para) > > struct sunxi_mctl_ctl_reg * const mctl_ctl = > > (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; > > > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > u8 tccd = 2; > > +#else > > + u8 tccd = 1; > > +#endif > > u8 tfaw = ns_to_t(50); > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > u8 trrd = max(ns_to_t(10), 4); > > u8 trcd = ns_to_t(15); > > u8 trc = ns_to_t(53); > > u8 txp = max(ns_to_t(8), 3); > > u8 twtr = max(ns_to_t(8), 4); > > u8 trtp = max(ns_to_t(8), 4); > > +#else > > + u8 trrd = max(ns_to_t(10), 2); > > + u8 trcd = ns_to_t(20); > > + u8 trc = ns_to_t(65); > > + u8 txp = 2; > > + u8 twtr = max(ns_to_t(8), 2); > > + u8 trtp = max(ns_to_t(8), 2); > > +#endif > > u8 twr = max(ns_to_t(15), 3); > > u8 trp = ns_to_t(15); > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > u8 tras = ns_to_t(38); > > +#else > > + u8 tras = ns_to_t(45); > > +#endif > > u16 trefi = ns_to_t(7800) / 32; > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > u16 trfc = ns_to_t(350); > > +#else > > + u16 trfc = ns_to_t(328); > > +#endif > > > > u8 tmrw = 0; > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > u8 tmrd = 4; > > +#else > > + u8 tmrd = 2; > > +#endif > > u8 tmod = 12; > > u8 tcke = 3; > > u8 tcksrx = 5; > > u8 tcksre = 5; > > u8 tckesr = 4; > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > u8 trasmax = 24; > > +#else > > + u8 trasmax = 27; > > +#endif > > Can't that be moved into a structure that would have different > declaration, this is barely readable. > > > > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > u8 tcl = 6; /* CL 12 */ > > u8 tcwl = 4; /* CWL 8 */ > > u8 t_rdata_en = 4; > > u8 wr_latency = 2; > > - > > +#else > > + u8 tcl = 3; /* CL 12 */ > > + u8 tcwl = 3; /* CWL 8 */ > > Aren't the comments supposed to change? > > > + u8 t_rdata_en = 1; > > + u8 wr_latency = 1; > > +#endif > > + > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ > > u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ > > +#else > > + u32 tdinit0 = (400 * CONFIG_DRAM_CLK) + 1; /* 400us */ > > + u32 tdinit1 = (500 * CONFIG_DRAM_CLK) / 1000 + 1; /* 500ns */ > > +#endif > > u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ > > u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ > > > > @@ -174,9 +218,15 @@ static void mctl_set_timing_params(struct dram_para *para) > > u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ > > > > /* set mode register */ > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ > > writel(0x40, &mctl_ctl->mr[1]); > > writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ > > +#else > > + writel(0x263, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ > > + writel(0x4, &mctl_ctl->mr[1]); > > + writel(0x0, &mctl_ctl->mr[2]); /* CWL=8 */ > > Ditto > > > +#endif > > writel(0x0, &mctl_ctl->mr[3]); > > > > /* set DRAM timing */ > > @@ -244,7 +294,12 @@ static void mctl_zq_calibration(struct dram_para *para) > > > > writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); > > > > - for (i = 0; i < 6; i++) { > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > + for (i = 0; i < 6; i++) > > +#else > > + for (i = 0; i < 4; i++) > > +#endif > > + { > > This should also be put into that structure or a define. > > > u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; > > > > writel((zq << 20) | (zq << 16) | (zq << 12) | > > @@ -266,7 +321,9 @@ static void mctl_zq_calibration(struct dram_para *para) > > > > writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); > > writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); > > +#endif > > } > > } > > > > @@ -275,8 +332,16 @@ static void mctl_set_cr(struct dram_para *para) > > struct sunxi_mctl_com_reg * const mctl_com = > > (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; > > > > - writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | > > - MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) | > > + writel(MCTL_CR_BL8 | MCTL_CR_2T | > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > + MCTL_CR_DDR3 | MCTL_CR_EIGHT_BANKS | > > + MCTL_CR_BUS_WIDTH(para->bus_width) | > > +#else > > + (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | > > + MCTL_CR_DDR2 | > > You can use a variable and then or is based on whether that option is > enabled or not, this will be easier to read. > > > + MCTL_CR_32BIT /* fixme, thats wrong but what boot0 does */ | > > What's wrong about it? V3s DRAM seems to be 16-bit. However, boot0 has this bit set, and without this bit, it cannot work. According to Jens' guess (only guess), this may be something more like full-width and half-width. > > > +#endif > > + MCTL_CR_INTERLEAVED | > > > (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | > > MCTL_CR_PAGE_SIZE(para->page_size) | > > MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr); > > @@ -380,7 +445,10 @@ static int mctl_channel_init(struct dram_para *para) > > > > mctl_zq_calibration(para); > > > > - mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST | > > + mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > + PIR_DRAMRST | > > +#endif > > PIR_DRAMINIT | PIR_QSGATE); > > > > /* detect ranks and bus width */ > > @@ -435,12 +503,29 @@ static void mctl_auto_detect_dram_size(struct dram_para *para) > > /* detect row address bits */ > > para->page_size = 512; > > para->row_bits = 16; > > +#ifdef CONFIG_SUNXI_H3_DRAM_DDR2 > > + para->bank_bits = 2; > > +#endif > > mctl_set_cr(para); > > > > for (para->row_bits = 11; para->row_bits < 16; para->row_bits++) > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size)) > > +#else > > + if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size)) > > +#endif > > Can't you use bank_bits all the time? > > > break; > > > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > + /* detect bank address bits */ > > + para->bank_bits = 3; > > + mctl_set_cr(para); > > + > > + for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++) > > + if (mctl_mem_matches((1 << para->bank_bits) * para->page_size)) > > + break; > > +#endif > > + > > /* detect page size */ > > para->page_size = 8192; > > mctl_set_cr(para); > > @@ -458,11 +543,19 @@ unsigned long sunxi_dram_init(void) > > (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; > > > > struct dram_para para = { > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > .read_delays = 0x00007979, /* dram_tpr12 */ > > .write_delays = 0x6aaa0000, /* dram_tpr11 */ > > +#else > > + .read_delays = 0x00007878, /* dram_tpr12 */ > > + .write_delays = 0x6a440000, /* dram_tpr11 */ > > +#endif > > .dual_rank = 0, > > .bus_width = 32, > > .row_bits = 15, > > +#ifdef CONFIG_SUNXI_H3_DRAM_DDR2 > > + .bank_bits = 3, > > +#endif > > .page_size = 4096, > > }; > > > > @@ -477,7 +570,13 @@ unsigned long sunxi_dram_init(void) > > udelay(1); > > > > /* odt delay */ > > +#ifndef CONFIG_SUNXI_H3_DRAM_DDR2 > > writel(0x0c000400, &mctl_ctl->odtcfg); > > +#else > > + writel(0x04000400, &mctl_ctl->odtcfg); > > + > > + clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13)); > > +#endif > > Some defines would be great. > > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe(a)googlegroups.com. > For more options, visit https://groups.google.com/d/optout.

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[U-Boot] Vexpress-ca9x4: huge size
by Mark L. 10 Jan '17

10 Jan '17

Hi, Once compiled, the u-boot.bin for vexpress-ca9x4 is 267,424 bytes on disk. In memory, it occupies 332,957 bytes (mallocs and so on). To me, it is HUGE. Is there a problem with my build, or is it normal? My compilation commands: make ARCH=arm CROSS_COMPILE=~/Downloads/gcc-arm-none-eabi-5_4-2016q3/bin/arm-none-eabi- vexpress_ca9x4_config make ARCH=arm CROSS_COMPILE=~/Downloads/gcc-arm-none-eabi-5_4-2016q3/bin/arm-none-eabi- Thanks -- Mark

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