January 2017 - U-Boot

[U-Boot] [ANN] U-Boot v2017.01 is released
by Tom Rini 12 Jan '17

12 Jan '17

Hey all, I've released v2017.01 and it's now live on git and FTP and ACD (along with PGP sig file). This release I think is a good way to start out a new year. There's the usual level of forward progress on the things that've been in progress for a while. I'll leave pointing out big changes to the custodians and instead I want to talk about what I see as the priorities for 2017. In 2016 we fully moved away from MAKEALL and to using buildman. In 2017 I want to see us finish the move to Kconfig. In September we added logic to break builds that introduce new symbols and since then we've been making progress on removing CONFIG symbols. I'm confident that this year we can finish the transition. Thanks again everyone! -- Tom

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[U-Boot] [PATCH v8 0/3] armv8: Support loading 32-bit OS in AArch32 execution state
by Alison Wang 12 Jan '17

12 Jan '17

This series is to support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. PSCI method can also be used for secondary cores to load 32-bit OS. As PSCI and secure monitor firmware framework are enabled, loading 32-bit OS is supported in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. --------------------------------------- Changes in v8: - Fix the issue when U-Boot is running in EL2 or EL1. - Support loading 32-bit OS with PSCI enabled. Changes in v7: - Move the call for armv8_switch_to_el2_m into the first patch. Changes in v6: - Modified armv8_switch_to_el1(). It will always jump to ep when switching to AArch64 or AArch32 modes. - Make other platforms compatible with the new armv8_switch_to_el2() and armv8_switch_to_el1(). - Make secondary_switch_to_el1() always jump to ep when switching to AArch64 or AArch32 modes. Changes in v5: - Modified armv8_switch_to_el2(). It will always jump to ep when switching to AArch64 or AArch32 modes. - Make secondary_switch_to_el2() always jump to ep when switching to AArch64 or AArch32 modes. Changes in v4: - Correct config ARM64_SUPPORT_AARCH32. - Omit arch and ftaddr arguments. - Rename "xreg5" to "tmp". - Use xxx_RES1 to combine all RES1 fields in xxx register. - Use an immediate cmp directly. - Use #ifdef for CONFIG_ARM64_SUPPORT_AARCH32. Changes in v3: - Comments the functions and the arguments. - Rename the real parameters. - Use the macros instead of the magic values. - Remove the redundant codes. - Clean up all of the mess in boot_jump_linux(). - Add CONFIG_ARM64_SUPPORT_AARCH32 to detect for some ARM64 system doesn't support AArch32 state. - Adjust the arguments for armv8_switch_to_el2_m and armv8_switch_to_el1_m. Changes in v2: - armv8_switch_to_el2_aarch32() is removed. armv8_switch_to_el2_m is used to switch to AArch64 EL2 or AArch32 Hyp. - armv8_switch_to_el1_aarch32() is removed. armv8_switch_to_el1_m is used to switch to AArch64 EL1 or AArch32 SVC. - Support to call armv8_switch_to_el2_m and armv8_switch_to_el1_m. ---------------------------------------------------------------- Alison Wang (3): armv8: Support loading 32-bit OS in AArch32 execution state armv8: fsl-layerscape: SMP support for loading 32-bit OS armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled arch/arm/Kconfig | 6 ++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 61 +++++++++++++++++++++++++------ arch/arm/cpu/armv8/fsl-layerscape/mp.c | 10 ++++++ arch/arm/cpu/armv8/sec_firmware_asm.S | 23 ++++++++++++ arch/arm/cpu/armv8/start.S | 8 +++++ arch/arm/cpu/armv8/transition.S | 35 ++++++++++++++---- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 6 ++++ arch/arm/include/asm/macro.h | 176 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------------- arch/arm/include/asm/system.h | 121 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- arch/arm/lib/bootm.c | 45 ++++++++++++++++++++--- arch/arm/mach-rmobile/lowlevel_init_gen3.S | 9 ++++- common/image-fit.c | 19 +++++++++- 12 files changed, 451 insertions(+), 68 deletions(-)

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[U-Boot] [PATCH] arm: samsung: goni: use the driver model for max8998
by Jaehoon Chung 12 Jan '17

12 Jan '17

Remove the "ifndef CONFIG_DM_I2C". Instead, use the driver model for max8998. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- board/samsung/goni/goni.c | 61 ++++++++++++++++++++++++----------------------- 1 file changed, 31 insertions(+), 30 deletions(-) diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index b066832..c1d7438 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/gpio.h> #include <asm/arch/mmc.h> +#include <dm.h> #include <power/pmic.h> #include <usb/dwc2_udc.h> #include <asm/arch/cpu.h> @@ -43,19 +44,6 @@ void i2c_init_board(void) } #endif -int power_init_board(void) -{ -#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ - /* - * For PMIC the I2C bus is named as I2C5, but it is connected - * to logical I2C adapter 0 - */ - return pmic_init(I2C_0); -#else - return 0; -#endif -} - int dram_init(void) { gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE + @@ -146,34 +134,47 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_USB_GADGET static int s5pc1xx_phy_control(int on) { -#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ - int ret; +#ifdef CONFIG_DM_PMIC_MAX8998 + struct udevice *dev; static int status; - struct pmic *p = pmic_get("MAX8998_PMIC"); - if (!p) - return -ENODEV; + int reg, ret; - if (pmic_probe(p)) - return -1; + ret = pmic_get("max8998_pmix", &dev); + if (ret) + return ret; if (on && !status) { - ret = pmic_set_output(p, MAX8998_REG_ONOFF1, - MAX8998_LDO3, LDO_ON); - ret = pmic_set_output(p, MAX8998_REG_ONOFF2, - MAX8998_LDO8, LDO_ON); + reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1); + reg |= MAX8998_LDO3; + ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg); if (ret) { puts("MAX8998 LDO setting error!\n"); - return -1; + return -EINVAL; + } + + reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2); + reg |= MAX8998_LDO8; + ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg); + if (ret) { + puts("MAX8998 LDO setting error!\n"); + return -EINVAL; } status = 1; } else if (!on && status) { - ret = pmic_set_output(p, MAX8998_REG_ONOFF1, - MAX8998_LDO3, LDO_OFF); - ret = pmic_set_output(p, MAX8998_REG_ONOFF2, - MAX8998_LDO8, LDO_OFF); + reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1); + reg &= ~MAX8998_LDO3; + ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg); + if (ret) { + puts("MAX8998 LDO setting error!\n"); + return -EINVAL; + } + + reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2); + reg &= ~MAX8998_LDO8; + ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg); if (ret) { puts("MAX8998 LDO setting error!\n"); - return -1; + return -EINVAL; } status = 0; } -- 2.10.2

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[U-Boot] [PATCH v4] rockchip: rk3288: set isp/vop qos priority level
by Nickey Yang 12 Jan '17

12 Jan '17

Isp-camera preview image will be broken when dual screen display mode. This patch set isp/vop qos level higher to solve this problem. We have verified this patch on rk3288-miniarm board. Signed-off-by: Nickey Yang <nickey.yang(a)rock-chips.com> --- arch/arm/include/asm/arch-rockchip/qos_rk3288.h | 20 ++++++++++++++++++++ arch/arm/mach-rockchip/rk3288-board.c | 20 ++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/qos_rk3288.h diff --git a/arch/arm/include/asm/arch-rockchip/qos_rk3288.h b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h new file mode 100644 index 0000000..b3094fc --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h @@ -0,0 +1,20 @@ +/* + * Copyright 2016 Rockchip Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_QOS_RK3288_H +#define _ASM_ARCH_QOS_RK3288_H + +#define PRIORITY_HIGH_SHIFT 2 +#define PRIORITY_LOW_SHIFT 0 + +#define CPU_AXI_QOS_PRIORITY 0x08 + +#define VIO0_VOP_QOS 0xffad0400 +#define VIO1_VOP_QOS 0xffad0000 +#define VIO1_ISP_R_QOS 0xffad0900 +#define VIO1_ISP_W0_QOS 0xffad0100 +#define VIO1_ISP_W1_QOS 0xffad0180 + +#endif diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 411bb29..018ac88 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -13,6 +13,7 @@ #include <asm/arch/clock.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3288.h> +#include <asm/arch/qos_rk3288.h> #include <asm/arch/boot_mode.h> #include <asm/arch/timer.h> #include <asm/gpio.h> @@ -50,9 +51,28 @@ __weak int rk_board_late_init(void) return 0; } +int rk3288_qos_init(void) +{ + int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; + /* set vop qos to higher priority */ + writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); + + if (!fdt_node_check_compatible(gd->fdt_blob, 0, + "rockchip,rk3288-miniarm")) + { + /* set isp qos to higher priority */ + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); + } + return 0; +} + int board_late_init(void) { setup_boot_mode(); + rk3288_qos_init(); return rk_board_late_init(); } -- 1.9.1

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[U-Boot] [RESEND PATCH v3 1/2] mmc: rockchip_sdhci: add clock init for mmc
by Kever Yang 12 Jan '17

12 Jan '17

Init the clock rate to max-frequency from dts with clock driver api. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v3: - using dt for max-frequency Series-changes: 2 - using the return value drivers/mmc/rockchip_sdhci.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index c56e1a3..e33e35e 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -12,7 +12,9 @@ #include <libfdt.h> #include <malloc.h> #include <sdhci.h> +#include <clk.h> +DECLARE_GLOBAL_DATA_PTR; /* 400KHz is max freq for card ID etc. Use that as min */ #define EMMC_MIN_FREQ 400000 @@ -32,11 +34,24 @@ static int arasan_sdhci_probe(struct udevice *dev) struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); struct rockchip_sdhc *prv = dev_get_priv(dev); struct sdhci_host *host = &prv->host; - int ret; + int max_frequency, ret; + struct clk clk; + + + max_frequency = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "max-frequency", 0); + ret = clk_get_by_index(dev, 0, &clk); + if (!ret) { + ret = clk_set_rate(&clk, max_frequency); + if (IS_ERR_VALUE(ret)) + printf("%s clk set rate fail!\n", __func__); + } else { + printf("%s fail to get clk\n", __func__); + } host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; - ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ, + ret = sdhci_setup_cfg(&plat->cfg, host, max_frequency, EMMC_MIN_FREQ); host->mmc = &plat->mmc; -- 1.9.1

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[U-Boot] [PATCH] rockchip: Fix veyron-minnie's Kconfig description
by Martin Michlmayr 12 Jan '17

12 Jan '17

The veyron-minnie Kconfig referred to jerry by mistake. Signed-off-by: Martin Michlmayr <tbm(a)cyrius.com> --- arch/arm/mach-rockchip/rk3288/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 223ae41..54545f3 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -61,7 +61,7 @@ config TARGET_CHROMEBIT_MICKEY config TARGET_CHROMEBOOK_MINNIE bool "Google/Rockchip Veyron-Minnie Chromebook" help - Jerry is a RK3288-based convertible clamshell device with 2 USB 3.0 + Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0 ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card, HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery -- 2.1.4 -- Martin Michlmayr http://www.cyrius.com/

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[U-Boot] [PATCH 00/18] imx: add i.MX7ULP support
by Peng Fan 12 Jan '17

12 Jan '17

This patchset is to add i.MX7 ULP support default enabling OF_CONTROL. i.MX7ULP has different architecture with i.MX7D/S, so not reuse the code in imx-common. Also there are some new IPs, such lpi2c/lpuart/ rapid gpio2p and etc. Peng Fan (15): imx: mx7ulp: Add mx7ulp to Kconfig imx: mx7ulp: add registers header file imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1 imx: mx7ulp: Add clock framework and functions imx: mx7ulp: Add soc level initialization codes and functions imx: mx7ulp: handle all the lpuarts in get_lpuart_clk gpio: Add Rapid GPIO2P driver for i.MX7ULP wdog: Add the watchdog driver for MX7ULP. pinctrl: Add i.MX7ULP pinctrl driver i2c: lpi2c: add lpi2c driver for i.MX7ULP serial: Add support for i.MX7ULP arm: dts: add i.MX7ULP dtsi file mmc: fsl_esdhc: support i.MX7ULP imx: imx7ulp: add EVK board support imx: mx7ulp_evk: enable mmc/regulator support Ye Li (3): imx: mx7ulp: Implement the clock functions for i2c driver mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULP mx7ulp: Add iomux pins header file arch/arm/Kconfig | 7 + arch/arm/cpu/armv7/Makefile | 3 +- arch/arm/cpu/armv7/mx7ulp/Kconfig | 17 + arch/arm/cpu/armv7/mx7ulp/Makefile | 8 + arch/arm/cpu/armv7/mx7ulp/clock.c | 354 +++++++ arch/arm/cpu/armv7/mx7ulp/iomux.c | 70 ++ arch/arm/cpu/armv7/mx7ulp/pcc.c | 286 ++++++ arch/arm/cpu/armv7/mx7ulp/scg.c | 1086 ++++++++++++++++++++++ arch/arm/cpu/armv7/mx7ulp/soc.c | 290 ++++++ arch/arm/dts/Makefile | 2 + arch/arm/dts/imx7ulp-evk.dts | 426 +++++++++ arch/arm/dts/imx7ulp-pinfunc.h | 882 ++++++++++++++++++ arch/arm/dts/imx7ulp-uboot.dtsi | 43 + arch/arm/dts/imx7ulp.dtsi | 598 ++++++++++++ arch/arm/include/asm/arch-mx7ulp/clock.h | 42 + arch/arm/include/asm/arch-mx7ulp/gpio.h | 22 + arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 1166 ++++++++++++++++++++++++ arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h | 520 +++++++++++ arch/arm/include/asm/arch-mx7ulp/iomux.h | 95 ++ arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h | 910 ++++++++++++++++++ arch/arm/include/asm/arch-mx7ulp/pcc.h | 377 ++++++++ arch/arm/include/asm/arch-mx7ulp/scg.h | 342 +++++++ arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 24 + board/freescale/mx7ulp_evk/Kconfig | 12 + board/freescale/mx7ulp_evk/Makefile | 10 + board/freescale/mx7ulp_evk/imximage.cfg | 131 +++ board/freescale/mx7ulp_evk/mx7ulp_evk.c | 77 ++ configs/mx7ulp_evk_defconfig | 25 + drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/imx_rgpio2p.c | 224 +++++ drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/imx_lpi2c.c | 462 ++++++++++ drivers/misc/mxc_ocotp.c | 50 + drivers/mmc/fsl_esdhc.c | 8 + drivers/pinctrl/nxp/Kconfig | 14 + drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imx.c | 10 +- drivers/pinctrl/nxp/pinctrl-imx.h | 3 + drivers/pinctrl/nxp/pinctrl-imx7ulp.c | 41 + drivers/serial/Kconfig | 5 + drivers/serial/Makefile | 1 + drivers/serial/serial_imxlpuart.c | 261 ++++++ drivers/watchdog/Kconfig | 8 + drivers/watchdog/Makefile | 1 + drivers/watchdog/ulp_wdog.c | 92 ++ include/configs/mx7ulp_evk.h | 128 +++ include/dt-bindings/clock/imx7ulp-clock.h | 161 ++++ 49 files changed, 9305 insertions(+), 5 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx7ulp/Kconfig create mode 100644 arch/arm/cpu/armv7/mx7ulp/Makefile create mode 100644 arch/arm/cpu/armv7/mx7ulp/clock.c create mode 100644 arch/arm/cpu/armv7/mx7ulp/iomux.c create mode 100644 arch/arm/cpu/armv7/mx7ulp/pcc.c create mode 100644 arch/arm/cpu/armv7/mx7ulp/scg.c create mode 100644 arch/arm/cpu/armv7/mx7ulp/soc.c create mode 100644 arch/arm/dts/imx7ulp-evk.dts create mode 100644 arch/arm/dts/imx7ulp-pinfunc.h create mode 100644 arch/arm/dts/imx7ulp-uboot.dtsi create mode 100644 arch/arm/dts/imx7ulp.dtsi create mode 100644 arch/arm/include/asm/arch-mx7ulp/clock.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/gpio.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/imx_lpi2c.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/iomux.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/pcc.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/scg.h create mode 100644 arch/arm/include/asm/arch-mx7ulp/sys_proto.h create mode 100644 board/freescale/mx7ulp_evk/Kconfig create mode 100644 board/freescale/mx7ulp_evk/Makefile create mode 100644 board/freescale/mx7ulp_evk/imximage.cfg create mode 100644 board/freescale/mx7ulp_evk/mx7ulp_evk.c create mode 100644 configs/mx7ulp_evk_defconfig create mode 100644 drivers/gpio/imx_rgpio2p.c create mode 100644 drivers/i2c/imx_lpi2c.c create mode 100644 drivers/pinctrl/nxp/pinctrl-imx7ulp.c create mode 100644 drivers/serial/serial_imxlpuart.c create mode 100644 drivers/watchdog/ulp_wdog.c create mode 100644 include/configs/mx7ulp_evk.h create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h -- 2.6.2

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[U-Boot] [PATCH] arm64: rk3399: update rockchip_get_cru API
by Kever Yang 12 Jan '17

12 Jan '17

rk3399 has two clock-controller: cru and pmucru, update the rockchip_get_crui() API, and rockchip_get_clk() do not used for other module. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index 7663591..ce706a6 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -11,10 +11,10 @@ #include <asm/arch/clock.h> #include <asm/arch/cru_rk3399.h> -int rockchip_get_clk(struct udevice **devp) +static int rockchip_get_cruclk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp); + DM_GET_DRIVER(clk_rk3399), devp); } void *rockchip_get_cru(void) @@ -23,7 +23,7 @@ void *rockchip_get_cru(void) struct udevice *dev; int ret; - ret = rockchip_get_clk(&dev); + ret = rockchip_get_cruclk(&dev); if (ret) return ERR_PTR(ret); -- 1.9.1

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[U-Boot] Accessing nested device tree nodes via phandle
by Vlad Zakharov 12 Jan '17

12 Jan '17

Hi everybody, I am working on reorganization of device trees for ARC boards in U-Boot in order to create a common device tree blob for both Linux and U-Boot. And I've struggled with a kind of problem and need some help. On AXS10x motherboard clocks for various peripherals are managed by one hardware block, so clock nodes in Linux device tree are grouped into one "clocks" node like this: ---------------------------------->8------------------------------------ clocks { i2cclk: i2cclk { compatible = "fixed-clock"; clock-frequency = <50000000>; #clock-cells = <0>; }; ... ... ... uartclk: uartclk { compatible = "fixed-clock"; clock-frequency = <33333333>; #clock-cells = <0>; }; }; ---------------------------------->8------------------------------------ And then some of them a referenced via phandle from other nodes, e.g. &uartclk is referenced from uart node. When I try to create such hierarchy in U-Boot I find that uart driver is not able to get clock via phandle and corresponding uart doesn't work. As I understand that is because children clocks nodes, i.e. "uartclk" in my case, never got bound as it's parent node "clocks" never got bound too. So when I add "compatible" and "u-boot,dm-pre-reloc" properties to "clocks" parent node everything works fine, e.g.: ---------------------------------->8------------------------------------ clocks { compatible = "simple-bus"; u-boot,dm-pre-reloc; uartclk: uartclk { compatible = "fixed-clock"; clock-frequency = <33333333>; #clock-cells = <0>; }; ... ... ... }; ---------------------------------->8------------------------------------ Please correct me if I wrongly interpret such behavior. I wonder if it the only approach to implement Linux-like hierarchy for ARC? Or I am mistaken and in fact can use pure Linux device tree without adding properties, described above? Thank you! -- Best regards, Vlad Zakharov <vzakhar(a)synopsys.com>

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[U-Boot] [PATCH] serial, ns16550: bugfix: ns16550 fifo not enabled
by Heiko Schocher 12 Jan '17

12 Jan '17

commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/isee/igep00x0/igep00x0.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c This patch fixes only: ./arch/arm/mach-omap2/am33xx/board.c Signed-off-by: Heiko Schocher <hs(a)denx.de> --- arch/arm/mach-omap2/am33xx/board.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 581c0ab..a0ce62c 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -39,15 +39,26 @@ DECLARE_GLOBAL_DATA_PTR; #if !CONFIG_IS_ENABLED(OF_CONTROL) +/* Clear & enable FIFOs */ +#define UART_FCRVAL (UART_FCR_FIFO_EN | \ + UART_FCR_RXSR | \ + UART_FCR_TXSR) + static const struct ns16550_platdata am33xx_serial[] = { - { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCRVAL }, # ifdef CONFIG_SYS_NS16550_COM2 - { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCRVAL }, # ifdef CONFIG_SYS_NS16550_COM3 - { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, - { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, - { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, - { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, .clock = CONFIG_SYS_NS16550_CLK }, + { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCRVAL }, + { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCRVAL }, + { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCRVAL }, + { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCRVAL }, # endif # endif }; -- 2.7.4

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