January 2017 - U-Boot

[U-Boot] [PATCH v2 0/7] mmc: more Kconfig conversion, MMC related clean-up
by Masahiro Yamada 12 Jan '17

12 Jan '17

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[U-Boot] [PATCH] SPL: Adjust more debug prints for ulong entry_point
by Tom Rini 11 Jan '17

11 Jan '17

With entry_point now being an unsigned long we need to adapt the last two debug prints to use %lX not %X. Fixes: 11e1479b9e67 ("SPL: make struct spl_image 64-bit safe") Signed-off-by: Tom Rini <trini(a)konsulko.com> --- arch/arm/imx-common/spl.c | 2 +- board/freescale/common/fsl_chain_of_trust.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c index c86b6f83b85c..60c4adf23751 100644 --- a/arch/arm/imx-common/spl.c +++ b/arch/arm/imx-common/spl.c @@ -101,7 +101,7 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) image_entry_noargs_t image_entry = (image_entry_noargs_t)(unsigned long)spl_image->entry_point; - debug("image entry point: 0x%X\n", spl_image->entry_point); + debug("image entry point: 0x%lX\n", spl_image->entry_point); /* HAB looks for the CSF at the end of the authenticated data therefore, * we need to subtract the size of the CSF from the actual filesize */ diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index dea231b866fe..438e7819576f 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -151,7 +151,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) * may return back in case of non-fatal failures. */ - debug("image entry point: 0x%X\n", spl_image->entry_point); + debug("image entry point: 0x%lX\n", spl_image->entry_point); image_entry(); } #endif /* ifdef CONFIG_SPL_FRAMEWORK */ -- 1.9.1

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[U-Boot] [GIT PULL] Please pull u-boot-mmc master
by Jaehoon Chung 11 Jan '17

11 Jan '17

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[U-Boot] [RFC Patch] drivers: mmc: omap_hsmmc: Fix IO Buffer on OMAP36XX
by aford173＠gmail.com 11 Jan '17

11 Jan '17

From: Adam Ford <aford173(a)gmail.com> On the OMAP36xx (and 37xx) the CONTROL_WKUP_CTRL register has a field (bit 6) named GPIO_IO_PWRDNZ. If 0, the IO buffers which are related to the MMC are disabled. After the PBIAS is configured, this bit should be set high to enable the MMC port. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 0a1ee40..069fd5a 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -38,6 +38,7 @@ #include <asm/arch/sys_proto.h> #endif #include <dm.h> +#include <asm/arch-omap3/mux.h> DECLARE_GLOBAL_DATA_PTR; @@ -115,6 +116,11 @@ static unsigned char mmc_board_init(struct mmc *mmc) PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, &t2_base->pbias_lite); + if (get_cpu_family() == CPU_OMAP36XX) + writel(readl(OMAP34XX_CTRL_WKUP_CTRL) | + OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, + OMAP34XX_CTRL_WKUP_CTRL); + writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, &t2_base->devconf0); -- 2.7.4

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[U-Boot] Allwinner A33 MIPI DSI Support.
by far5893 11 Jan '17

11 Jan '17

I have a new fresh Q8 A33 tablet but different from previous two it have native MIPI DSI interface, there is working in progress to support MIPI DSI interface in u-boot ? lcd_fex [lcd0_para] lcd_used = 1 lcd_driver_name = "tm1280X800" lcd_if = 4 lcd_x = 800 lcd_y = 1280 lcd_width = 120 lcd_height = 160 lcd_dclk_freq = 78 lcd_pwm_used = 1 lcd_pwm_ch = 0 lcd_pwm_freq = 50000 lcd_pwm_pol = 1 lcd_hbp = 96 lcd_ht = 961 lcd_hspw = 48 lcd_vbp = 12 lcd_vt = 1322 lcd_vspw = 4 lcd_dsi_if = 0 lcd_dsi_lane = 4 lcd_dsi_format = 0 lcd_dsi_te = 0 lcd_lvds_if = 0 lcd_lvds_colordepth = 0 lcd_lvds_mode = 0 lcd_frm = 1 lcd_hv_clk_phase = 0 lcd_hv_sync_polarity = 0 lcd_gamma_en = 0 lcd_bright_curve_en = 0 lcd_cmap_en = 0 deu_mode = 0 lcdgamma4iep = 22 smart_color = 90 lcd_bl_en = port:PH06<1><0><default><1> lcd_power = port:power2<1><0><default><1> lcd_power_1 = "axp22_eldo1" lcd_gpio_0 = port:PH07<1><0><default><1> Thank silviop

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[U-Boot] [PATCH] board/t1024rdb: enable board-level reset when issuing reset command
by Shengzhou Liu 11 Jan '17

11 Jan '17

As board-specific reset logic, it needs to issue reset signal via CPLD when issuing 'reset' command in u-boot, this patch solves the issue of reset command not working on T1024RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- board/freescale/t102xrdb/t102xrdb.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index 01dbf38..6de877a 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -167,6 +167,11 @@ unsigned long get_board_ddr_clk(void) return CONFIG_DDR_CLK_FREQ; } +void board_reset(void) +{ + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + int misc_init_r(void) { return 0; -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 0/8] zynq: clk: Move zynq platform to clock framework
by stefan.herbrechtsmeier＠weidmueller.com 11 Jan '17

11 Jan '17

From: Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> The old platform clock driver use a dynamic array which is filled at every boot with static clock tree information and unused clock rates. This needs much memory and complicates the strip down for the SPL. The new clock framework driver contains the tree information in functions and reads clock rates on demand. Stefan Herbrechtsmeier (8): net: zynq: Don't overwrite gem_rclk_ctrl with default value net: zynq: Add clk framework support to zynq ethernet driver zynq: Add clk framework support to zynq timer zynq: Move static clock names into separate array zynq: Remove zynq_clk_get_name function clk: zynq: Add zynq clock framework driver zynq: Move zynq to clock framework clk: zynq: Add optional ethernet emio clock source support arch/arm/Kconfig | 2 + arch/arm/dts/zynq-7000.dtsi | 2 + arch/arm/include/asm/arch-zynqmp/sys_proto.h | 5 - arch/arm/mach-zynq/clk.c | 687 +++------------------------ arch/arm/mach-zynq/cpu.c | 1 - arch/arm/mach-zynq/include/mach/clk.h | 6 - arch/arm/mach-zynq/include/mach/sys_proto.h | 1 - arch/arm/mach-zynq/slcr.c | 29 -- arch/arm/mach-zynq/timer.c | 23 + drivers/clk/Kconfig | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk_zynq.c | 499 +++++++++++++++++++ drivers/net/zynq_gem.c | 27 +- drivers/serial/serial_zynq.c | 6 +- include/configs/topic_miami.h | 2 - include/configs/zynq_zybo.h | 3 - scripts/config_whitelist.txt | 1 - 17 files changed, 618 insertions(+), 684 deletions(-) create mode 100644 drivers/clk/clk_zynq.c -- 2.7.4 Kommanditgesellschaft - Sitz: Detmold - Amtsgericht Lemgo HRA 2790 - Komplementärin: Weidmüller Interface Führungsgesellschaft mbH - Sitz: Detmold - Amtsgericht Lemgo HRB 3924; Geschäftsführer: José Carlos Álvarez Tobar, Elke Eckstein, Dr. Peter Köhler, Jörg Timmermann; USt-ID-Nr. DE124599660

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[U-Boot] [PATCH v3 0/4] mmc: sdhci: Add support for frequency constrained peripheral interfaces
by stefan.herbrechtsmeier＠weidmueller.de 11 Jan '17

11 Jan '17

From: Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.de> The sdhci controller assumes that the base clock frequency is fully supported by the peripheral and doesn't support hardware limitations. Distinguish between base clock of the host controller and maximal supported peripheral clock frequency of the peripheral interface. This is needed for the zynq platform to support two sdhci ports with different IO routings. Changes in v3: - Rename arguments of sdhci_setup_cfg function from max_clk/min_clk to f_max/f_min Changes in v2: - Remove unused index from get uart clock function - Remove unused index from get sdio clock function - Introduce common get clock function Stefan Herbrechtsmeier (4): mmc: sdhci: Distinguish between base clock and maximum peripheral frequency serial: zynq: Remove unused index from get uart clock function mmc: zynq: Determine base clock frequency via clock framework mmc: zynq: Add fdt max-frequency support arch/arm/mach-zynq/clk.c | 51 +++++++++++++++++++++++++++-------- arch/arm/mach-zynq/include/mach/clk.h | 3 ++- drivers/mmc/atmel_sdhci.c | 7 +++-- drivers/mmc/bcm2835_sdhci.c | 3 ++- drivers/mmc/ftsdc021_sdhci.c | 3 ++- drivers/mmc/kona_sdhci.c | 3 ++- drivers/mmc/msm_sdhci.c | 2 ++ drivers/mmc/mv_sdhci.c | 3 ++- drivers/mmc/pci_mmc.c | 1 + drivers/mmc/pic32_sdhci.c | 4 ++- drivers/mmc/rockchip_sdhci.c | 4 +-- drivers/mmc/s5p_sdhci.c | 5 ++-- drivers/mmc/sdhci.c | 34 ++++++++++++----------- drivers/mmc/spear_sdhci.c | 3 ++- drivers/mmc/zynq_sdhci.c | 40 ++++++++++++++++++++++++++- drivers/serial/serial_zynq.c | 2 +- include/sdhci.h | 13 ++++----- 17 files changed, 133 insertions(+), 48 deletions(-) -- 2.7.4 Kommanditgesellschaft - Sitz: Detmold - Amtsgericht Lemgo HRA 2790 - Komplementärin: Weidmüller Interface Führungsgesellschaft mbH - Sitz: Detmold - Amtsgericht Lemgo HRB 3924; Geschäftsführer: José Carlos Álvarez Tobar, Elke Eckstein, Dr. Peter Köhler, Jörg Timmermann; USt-ID-Nr. DE124599660

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[U-Boot] x86: binman build error (fdtget)
by Stefan Roese 11 Jan '17

11 Jan '17

Hi Simon, I just tried to build a new U-Boot image for an x86 platform and get this compilation error: ... CC lib/display_options.o LD lib/built-in.o LD u-boot OBJCOPY u-boot-x86-16bit.bin OBJCOPY u-boot-nodtb.bin CAT u-boot-dtb.bin COPY u-boot.bin BINMAN u-boot.rom binman: Error running 'fdtget u-boot.dtb / -p': <type 'str'> Makefile:1081: recipe for target 'u-boot.rom' failed make: *** [u-boot.rom] Error 1 Do you have a quick idea, why I see this error? Thanks, Stefan

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[U-Boot] [PATCH v6 0/9] rockchip: Add gmac Ethernet support
by Romain Perier 11 Jan '17

11 Jan '17

>From Romain: This is a resent of Simon's v4 series. I have changed what was suggested by David Wu about the driver name (rename gmac_rk3288 to gmac_rockchip). I have also tested the whole series on a rock2 square board, updated the configuration files for rock2 and firefly boards and added some Signed-off-by tags. >From Simon: This v3 patch is an update on Sjoerd's original v2 series from Feburary. I have dealt with the changes requested at the time, and adjusted the way that the speed change is handled. Tested on firefly-rk3288, rock2. Original cover letter: To add support I've taken a slightly different approach then some of the other boards with a designware IP block, by creating a new driver to take care of the platfrom glue which subclasses the main designware driver instead of adding the compatibility string the designware driver directly and doing the SoC specific setup in the board files. This seems quite a bit more elegant in a device model based world. I've only tested this series on a Radxa Rock 2 board, it would be great if someone could test this on other boards with the designware IP especially for those with the reset GPIO in devicetree (e.g. some of the Allwinner boards). Compared to the first one round the pinctrl related bits were dropped as RK3288 now has a full pinctrl driver. Furthermore the started hook in the designware driver was renamed to fix_mac_speed in line with what linux uses and moved to the dw_link_adjust function. Changes in v6: - Changed Acked-by to Signed-off-by for Romain in commits from [PATCH 01/09] to [PATCH 06/09] Changes in v5: - Changed the name of the driver gmac_rk3288 to gmac_rockchip, as suggested by David Wu. Also I rewrote the commit message - Added my Acked-by to commits from [PATCH 01/09] to [PATCH 06/09] - Updated configuration files for rock2 and firefly with the new Kconfig symbol Changes in v4: - Fix commit message to say 'rk3399' Changes in v3: - Add a few new patches - Add comments for struct gmac_rk3288_platdata - Add new patch to adjust dw_adjust_link() to return an error - Add new patch to enable networking on evb-rk3399 - Add new patch to export the operation functions - Add new patch to split the link init into a separate function - Adjust binding to use r/tx-delay instead of r/tx_delay - Drop the 'net: designware: Add a fix_mac_speed hook' patch - Sort includes - Use debug() instead of printf() for error - Use function calls instead of fix_mac_speed() hook - Use new clk interface Changes in v2: - Adjust to new hook name - Fix various coding style nits Simon Glass (4): net: designware: Adjust dw_adjust_link() to return an error net: designware: Split the link init into a separate function net: designware: Export the operation functions rockchip: evb-rk3339: Enable DHCP Sjoerd Simons (5): net: designware: Export various functions/struct to allow subclassing net: gmac_rockchip: Add Rockchip GMAC driver rockchip: Enable networking support on rock2 and firefly rockchip: Add PXE and DHCP to the default boot targets rockchip: Drop Ethernet from the TODO configs/evb-rk3399_defconfig | 3 + configs/firefly-rk3288_defconfig | 4 + configs/rock2_defconfig | 4 + doc/README.rockchip | 1 - drivers/net/Kconfig | 7 ++ drivers/net/Makefile | 1 + drivers/net/designware.c | 57 ++++++++++---- drivers/net/designware.h | 13 ++++ drivers/net/gmac_rockchip.c | 154 ++++++++++++++++++++++++++++++++++++++ include/configs/rockchip-common.h | 4 +- 10 files changed, 230 insertions(+), 18 deletions(-) create mode 100644 drivers/net/gmac_rockchip.c -- 2.11.0

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