February 2016 - U-Boot

[U-Boot] [PATCH] Revert "arm: Remove wireless_space board"
by Albert ARIBAUD 02 Apr '16

02 Apr '16

Revert commit b352182a and complete generic board support. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- arch/arm/mach-kirkwood/Kconfig | 4 + board/LaCie/wireless_space/Kconfig | 12 ++ board/LaCie/wireless_space/MAINTAINERS | 6 + board/LaCie/wireless_space/Makefile | 12 ++ board/LaCie/wireless_space/kwbimage.cfg | 71 +++++++++++ board/LaCie/wireless_space/wireless_space.c | 165 +++++++++++++++++++++++++ configs/wireless_space_defconfig | 7 ++ include/configs/wireless_space.h | 179 ++++++++++++++++++++++++++++ 8 files changed, 456 insertions(+) create mode 100644 board/LaCie/wireless_space/Kconfig create mode 100644 board/LaCie/wireless_space/MAINTAINERS create mode 100644 board/LaCie/wireless_space/Makefile create mode 100644 board/LaCie/wireless_space/kwbimage.cfg create mode 100644 board/LaCie/wireless_space/wireless_space.c create mode 100644 configs/wireless_space_defconfig create mode 100644 include/configs/wireless_space.h diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 9205b1e..9249564 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -37,6 +37,9 @@ config TARGET_NET2BIG_V2 config TARGET_NETSPACE_V2 bool "LaCie netspace_v2 Board" +config TARGET_WIRELESS_SPACE + bool "LaCie Wireless_space Board" + config TARGET_IB62X0 bool "ib62x0 Board" @@ -68,6 +71,7 @@ source "board/iomega/iconnect/Kconfig" source "board/keymile/km_arm/Kconfig" source "board/LaCie/net2big_v2/Kconfig" source "board/LaCie/netspace_v2/Kconfig" +source "board/LaCie/wireless_space/Kconfig" source "board/raidsonic/ib62x0/Kconfig" source "board/Seagate/dockstar/Kconfig" source "board/Seagate/goflexhome/Kconfig" diff --git a/board/LaCie/wireless_space/Kconfig b/board/LaCie/wireless_space/Kconfig new file mode 100644 index 0000000..75a2fc5 --- /dev/null +++ b/board/LaCie/wireless_space/Kconfig @@ -0,0 +1,12 @@ +if TARGET_WIRELESS_SPACE + +config SYS_BOARD + default "wireless_space" + +config SYS_VENDOR + default "LaCie" + +config SYS_CONFIG_NAME + default "wireless_space" + +endif diff --git a/board/LaCie/wireless_space/MAINTAINERS b/board/LaCie/wireless_space/MAINTAINERS new file mode 100644 index 0000000..c32ecb8 --- /dev/null +++ b/board/LaCie/wireless_space/MAINTAINERS @@ -0,0 +1,6 @@ +WIRELESS_SPACE BOARD +M: Albert ARIBAUD <albert.u.boot(a)aribaud.net> +S: Maintained +F: board/LaCie/wireless_space/ +F: include/configs/wireless_space.h +F: configs/wireless_space_defconfig diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile new file mode 100644 index 0000000..90a84f4 --- /dev/null +++ b/board/LaCie/wireless_space/Makefile @@ -0,0 +1,12 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot(a)lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := wireless_space.o ../common/common.o diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg new file mode 100644 index 0000000..037248b --- /dev/null +++ b/board/LaCie/wireless_space/kwbimage.cfg @@ -0,0 +1,71 @@ +# +# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot(a)aribaud.net> +# +# Based on netspace_v2 kwbimage.cfg: +# Copyright (C) 2011 Simon Guinot <sguinot(a)lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand # Boot from NAND flash +NAND_PAGE_SIZE 800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Values taken from image original LaCie U-Boot header dump! + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register + +DATA 0xFFD01404 0x37743000 # DDR Controller Control Low + +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) + +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) + +DATA 0xFFD01410 0x0000CCCC # DDR Address Control + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control + +DATA 0xFFD01418 0x00000000 # DDR Operation + +DATA 0xFFD0141C 0x00000662 # DDR Mode + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High + +DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) + +DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +DATA 0xFFD20134 0x66666666 +DATA 0xFFD20138 0x66666666 +DATA 0xFFD10000 0x01112222 +DATA 0xFFD1000C 0x00000000 +DATA 0xFFD10104 0x00000000 +DATA 0xFFD10100 0x40000000 +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c new file mode 100644 index 0000000..8620e4b --- /dev/null +++ b/board/LaCie/wireless_space/wireless_space.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot(a)lacie.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> + +#include "../common/common.h" +#include "netdev.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO configuration: start FAN at low speed, USB and HDD */ + +#define WIRELESS_SPACE_OE_LOW 0xFF006808 +#define WIRELESS_SPACE_OE_HIGH 0x0000F989 +#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080 +#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240 + +#define WIRELESS_SPACE_REAR_BUTTON 13 +#define WIRELESS_SPACE_FRONT_BUTTON 43 + +const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Fan speed (bit 1) */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP13_GPIO, /* Red led */ + MPP14_GPIO, /* USB fuse */ + MPP15_SATA0_ACTn, + MPP16_GPIO, /* SATA 0 power */ + MPP17_GPIO, /* SATA 1 power */ + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, /* Gigabit Ethernet 1 */ + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GE1_8, + MPP29_GE1_9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GE1_14, + MPP35_GE1_15, + MPP36_GPIO, /* Fan speed (bit 2) */ + MPP37_GPIO, /* Fan speed (bit 0) */ + MPP38_GPIO, /* Fan power */ + MPP39_GPIO, /* Fan rotation fail */ + MPP40_GPIO, /* Ethernet switch link */ + MPP41_GPIO, /* USB enable host vbus */ + MPP42_GPIO, /* LED clock control */ + MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */ + MPP44_GPIO, /* Red LED on/off */ + MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */ + MPP46_GPIO, /* Green LED on/off */ + MPP47_GPIO, /* LED (blue, green) SATA activity blink */ + MPP48_GPIO, /* Blue LED on/off */ + 0 +}; + +struct mv88e61xx_config swcfg = { + .name = "egiga0", + .vlancfg = MV88E61XX_VLANCFG_ROUTER, + .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, + .led_init = MV88E61XX_LED_INIT_EN, + .mdip = MV88E61XX_MDIP_NOCHANGE, + .portstate = MV88E61XX_PORTSTT_FORWARDING, + .cpuport = 0x20, + .ports_enabled = 0x3F, +}; + +int board_early_init_f(void) +{ + /* Gpio configuration */ + mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, + WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + /* Machine number */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* Boot parameters address */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) + if (!getenv("ethaddr")) { + uchar mac[6]; + if (lacie_read_mac_address(mac) == 0) + eth_setenv_enetaddr("ethaddr", mac); + } +#endif + return 0; +} +#endif + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and initialize PHY */ +void reset_phy(void) +{ + /* configure switch on egiga0 */ + mv88e61xx_switch_initialize(&swcfg); +} +#endif + +#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD) +/* Return GPIO button status */ +static int +do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (strcmp(argv[1], "button") == 0) { + if (strcmp(argv[2], "rear") == 0) + /* invert GPIO result for intuitive while/until use */ + return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON); + else if (strcmp(argv[2], "front") == 0) + return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON); + else + return -1; + } else { + return -1; + } +} + +U_BOOT_CMD(ws, 3, 0, do_ws, + "Return GPIO button status 0=off 1=on", + "- ws button rear|front: test buttons' states\n" +); +#endif diff --git a/configs/wireless_space_defconfig b/configs/wireless_space_defconfig new file mode 100644 index 0000000..daf8870 --- /dev/null +++ b/configs/wireless_space_defconfig @@ -0,0 +1,7 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_WIRELESS_SPACE=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h new file mode 100644 index 0000000..191ac1b --- /dev/null +++ b/include/configs/wireless_space.h @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2011 Albert ARIBAUD <albert.u.boot(a)aribaud.net> + * + * Based on the netspace_v2 code which is + * Copyright (C) 2011 Simon Guinot <sguinot(a)lacie.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_WIRELESS_SPACE_H +#define _CONFIG_WIRELESS_SPACE_H + +/* + * Machine number definition + */ +#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */ +#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE +#define CONFIG_IDENT_STRING " Wireless Space" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +/* SoC name */ +#define CONFIG_KW88F6281 +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_NAND +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_USB + +/* + * Core clock definition + */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +/* + * SDRAM configuration + */ +#define CONFIG_NR_DRAM_BANKS 1 + +/* + * Different SDRAM configuration and size for some of the boards derived + * from the Network Space v2 + */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_RBTREE +#undef CONFIG_SYS_IDE_MAXBUS +#undef CONFIG_SYS_IDE_MAXDEVICE +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */ +#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */ +#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */ +#define CONFIG_MII +#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_NETCONSOLE +#define CONFIG_MV88E61XX_SWITCH +#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define CONFIG_MV88E61XX_CMD +#define CONFIG_CMD_TFTPPUT +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /* CONFIG_MVSATA_IDE */ + +/* + * Enable GPI0 support + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * Enable I2C support + */ +#ifdef CONFIG_CMD_I2C +/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ +#endif /* CONFIG_CMD_I2C */ + +/* + * Partition support + */ +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + +/* + * File systems support + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Console configuration + */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Environment variables configurations + */ + +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */ +#define CONFIG_ENV_SIZE 0x20000 /* 128KB */ +#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ + +/* + * Board-specific command to make using buttons etc easier + */ + +#define CONFIG_WIRELESS_SPACE_CMD + +/* + * Default environment variables + */ +#define CONFIG_PREBOOT + +#define CONFIG_BOOTARGS "console=ttyS0,115200" + +#define CONFIG_BOOTCOMMAND \ + "if run usbload || run diskload; then bootm; fi" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "bootfile=uImage\0" \ + "loadaddr=0x800000\0" \ + "autoload=no\0" \ + "netconsole=" \ + "set stdin $stdin,nc; " \ + "set stdout $stdout,nc; " \ + "set stderr $stderr,nc;\0" \ + "diskload=ide reset && " \ + "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ + "usbload=usb start && " \ + "fatload usb 0:1 $loadaddr /boot/$bootfile\0" \ + "preboot=" \ + "dhcp && run netconsole\0" + +#endif /* _CONFIG_WIRELESS_SPACE_H */ -- 2.5.0

2 2

[U-Boot] [PATCH V4 1/3] arm: discard relocation entries for secure text
by Peng Fan 31 Mar '16

31 Mar '16

The code such as PSCI in section named secure is bundled with u-boot image, and when bootm, the code will be copied to their runtime address same to compliation/linking address - CONFIG_ARMV7_SECURE_BASE. When compile the PSCI code and link it into the u-boot image, there will be relocation entries in .rel.dyn section for PSCI. Actually, we do not needs these relocation entries. If still keep the relocation entries in .rel.dyn section, r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid address which may not support read/write for one SoC. 102 /* relative fix: increase location by offset */ 103 add r0, r0, r4 104 ldr r1, [r0] 105 add r1, r1, r4 106 str r1, [r0] So discard them to avoid touching the relocation entry in arch/arm/lib/relocate.S. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Tom Warren <twarren(a)nvidia.com> Cc: York Sun <yorksun(a)freescale.com> Cc: Hans De Goede <hdegoede(a)redhat.com> Cc: Ian Campbell <ijc(a)hellion.org.uk> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Tom Rini <trini(a)konsulko.com> Cc: Jan Kiszka <jan.kiszka(a)siemens.com> Cc: Stefano Babic <sbabic(a)denx.de> --- Changes v4: none V2 thread: http://lists.denx.de/pipermail/u-boot/2015-October/230755.html Changes v3: Move the relocation entries to the very begining and discard them. V1 thread: http://lists.denx.de/pipermail/u-boot/2015-October/229426.html Changes V2: Refine commit msg. Discard the relocation entry section for secure text. arch/arm/cpu/u-boot.lds | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 03cd9f6..d48a905 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -14,6 +14,23 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { + /* + * Discard the relocation entries for secure text. + * The secure code is bundled with u-boot image, so there will + * be relocations entries for the secure code, since we use + * "-mword-relocations" to compile and "-pie" to link into the + * final image. We do not need the relocation entries for secure + * code, because secure code will not be relocated, it only needs + * to be copied from loading address to CONFIG_ARMV7_SECURE_BASE, + * which is the linking and running address for secure code. + * If keep the relocation entries in .rel.dyn section, + * "relocation offset + linking address" may locates into an + * address that is reserved by SoC, then will trigger data abort. + * + * The reason that move .rel._secure at the beginning, is to + * avoid hole in the final image. + */ + /DISCARD/ : { *(.rel._secure*) } . = 0x00000000; . = ALIGN(4); -- 1.8.4

6 11

[U-Boot] [PATCH] tools/kwboot.c: Support UART fallback mode
by Kevin Smith 29 Mar '16

29 Mar '16

On some processors such as Armada 38x, if the hardware- configured boot mode fails, the CPU falls back to booting over UART. When this happens the chip prints a failure message, waits for the magic sequence and, when it is received, prints a "(boot)" message, then sends a NAK to start the transfer. This breaks the current kwboot behavior because the xmodem transfer only tries to read one character after the magic sequence, looking for the NAK. Instead it gets the "(boot)" text, and retries the magic sequence. The CPU thinks the repeated sequence is part of the packet, stops NAKing, and one side or another eventually times out. This patch adds support for a fallback mode which continues to scan for a NAK in the characters received after the sequence, printing out any non-NAK characters. This allows kwboot to skip the "(boot)" message, find the NAK, and start the transfer successfully. Signed-off-by: Kevin Smith <kevin.smith(a)elecsyscorp.com> --- tools/kwboot.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/tools/kwboot.c b/tools/kwboot.c index af7a6ee..6b58fc9 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -71,6 +71,7 @@ struct kwboot_block { #define KWBOOT_BLK_RSP_TIMEO 1000 /* ms */ static int kwboot_verbose; +static int support_fallback; static int msg_req_delay = KWBOOT_MSG_REQ_DELAY; static int msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO; @@ -300,7 +301,15 @@ kwboot_bootmsg(int tty, void *msg) continue; } - rc = kwboot_tty_recv(tty, &c, 1, msg_rsp_timeo); + while (1) { + rc = kwboot_tty_recv(tty, &c, 1, msg_rsp_timeo); + if (support_fallback && rc == 0 && c != NAK) { + printf("%c", c); + fflush(stdout); + continue; + } + break; + } kwboot_spinner(); @@ -657,7 +666,7 @@ static void kwboot_usage(FILE *stream, char *progname) { fprintf(stream, - "Usage: %s [-d | -a | -q <req-delay> | -s <resp-timeo> | -b <image> | -D <image> ] [ -t ] [-B <baud> ] <TTY>\n", + "Usage: %s [-f] [-d | -a | -q <req-delay> | -s <resp-timeo> | -b <image> | -D <image> ] [ -t ] [-B <baud> ] <TTY>\n", progname); fprintf(stream, "\n"); fprintf(stream, @@ -667,6 +676,7 @@ kwboot_usage(FILE *stream, char *progname) " -D <image>: boot <image> without preamble (Dove)\n"); fprintf(stream, " -d: enter debug mode\n"); fprintf(stream, " -a: use timings for Armada XP\n"); + fprintf(stream, " -f: support UART fallback after failed boot\n"); fprintf(stream, " -q <req-delay>: use specific request-delay\n"); fprintf(stream, " -s <resp-timeo>: use specific response-timeout\n"); fprintf(stream, "\n"); @@ -701,7 +711,7 @@ main(int argc, char **argv) kwboot_verbose = isatty(STDOUT_FILENO); do { - int c = getopt(argc, argv, "hb:ptaB:dD:q:s:"); + int c = getopt(argc, argv, "hb:ptfaB:dD:q:s:"); if (c < 0) break; @@ -728,6 +738,10 @@ main(int argc, char **argv) term = 1; break; + case 'f': + support_fallback = 1; + break; + case 'a': msg_req_delay = KWBOOT_MSG_REQ_DELAY_AXP; msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO_AXP; -- 2.4.6

2 3

[U-Boot] [PATCH v2 1/2] mx7_common: Put early/late init configs into board file
by Fabio Estevam 25 Mar '16

25 Mar '16

From: Fabio Estevam <fabio.estevam(a)nxp.com> CONFIG_BOARD_EARLY_INIT_F and CONFIG_BOARD_LATE_INIT should not be placed into mx7_common because not all boards need these options. Move them to the board file instead. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> Reviewed-by: Peng Fan <peng.fan(a)nxp.com> --- Changes since v1: - None include/configs/mx7_common.h | 3 --- include/configs/mx7dsabresd.h | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index fac7c3f..a78fc7c 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -32,9 +32,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 2c981e0..d233572 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -14,6 +14,9 @@ #define CONFIG_DBG_MONITOR #define PHYS_SDRAM_SIZE SZ_1G +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + /* Uncomment to enable secure boot support */ /* #define CONFIG_SECURE_BOOT */ #define CONFIG_CSF_SIZE 0x4000 -- 1.9.1

2 7

[U-Boot] [PATCH] mvebu: usb: Add missing controller reset after initialization
by Phil Sutter 24 Mar '16

24 Mar '16

In order to allow for Linux properly register the integrated EHCI host, we have to reset it after initialization. Without this, enumeration fails if 'usb start' wasn't issued prior to booting Linux. Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- arch/arm/mach-mvebu/cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 5c62fd5..cb885f8 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -281,6 +281,8 @@ static void set_cbar(u32 addr) (((addr) & 0xF) << 6)) #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \ (((reg) & 0xF) << 2)) +#define MV_USB_CMD_REG(dev) (MVEBU_AXP_USB_BASE + (dev * 0x1000) + 0x140) +#define MV_USB_MODE_REG(dev) (MVEBU_AXP_USB_BASE + (dev * 0x1000) + 0x1A8) static void setup_usb_phys(void) { @@ -313,6 +315,16 @@ static void setup_usb_phys(void) setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); udelay(40); clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); + + /* disable (bit 0) and reset (bit 1) controller */ + /* XXX: do this in two steps? */ + clrsetbits_le32(MV_USB_CMD_REG(dev), BIT(0), BIT(1)); + + while(readl(MV_USB_CMD_REG(dev)) & BIT(1)) + ; + + /* set host mode (device mode is (0x2 | 1 << 3)) */ + writel(0x3, MV_USB_MODE_REG(dev)); } } -- 2.5.3

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[U-Boot] [PATCH 1/2] tools: kwboot: Clean up usage text
by Kevin Smith 24 Mar '16

24 Mar '16

Usage text was getting unwieldy and somewhat incorrect. The usage summary implied that some options were mutually exclusive (e.g. -q or -s). Clean up the summary to just include the important ones, and include a generic "[OPTIONS]" instead. Signed-off-by: Kevin Smith <kevin.smith(a)elecsyscorp.com> Cc: Stefan Roese <sr(a)denx.de> --- tools/kwboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/kwboot.c b/tools/kwboot.c index c5f4492..6d1f66e 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -674,7 +674,7 @@ static void kwboot_usage(FILE *stream, char *progname) { fprintf(stream, - "Usage: %s [-d | -a | -q <req-delay> | -s <resp-timeo> | -b <image> | -D <image> ] [ -t ] [-B <baud> ] <TTY>\n", + "Usage: %s [OPTIONS] [-b <image> | -D <image> ] [-B <baud> ] <TTY>\n", progname); fprintf(stream, "\n"); fprintf(stream, -- 2.4.6

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[U-Boot] [PATCH] arm: mvebu: db-88f6820: Drop obsolete binary.0 placeholder
by Andreas Färber 24 Mar '16

24 Mar '16

It has been superseded in kwbimage.cfg in favor of an SPL in commit 9e30b31d20f0b793465d07f056b3d9885f578c0d (arm: mvebu: db-88f6820: Add SPL support with DDR init code). Found via code review. Cc: Stefan Roese <sr(a)denx.de> Signed-off-by: Andreas Färber <afaerber(a)suse.de> --- board/Marvell/db-88f6820-gp/binary.0 | 16 ---------------- 1 file changed, 16 deletions(-) delete mode 100644 board/Marvell/db-88f6820-gp/binary.0 diff --git a/board/Marvell/db-88f6820-gp/binary.0 b/board/Marvell/db-88f6820-gp/binary.0 deleted file mode 100644 index 57a4cbf..0000000 --- a/board/Marvell/db-88f6820-gp/binary.0 +++ /dev/null @@ -1,16 +0,0 @@ --------- -WARNING: --------- -This file should contain the bin_hdr generated by the original Marvell -U-Boot implementation. As this is currently not included in this -U-Boot version, we have added this placeholder, so that the U-Boot -image can be generated without errors. - -If you have a known to be working bin_hdr for your board, then you -just need to replace this text file here with the binary header -and recompile U-Boot. - -In a few weeks, mainline U-Boot will get support to generate the -bin_hdr with the DDR training code itself. By implementing this code -as SPL U-Boot. Then this file will not be needed any more and will -get removed. -- 2.6.2

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[U-Boot] [PATCH 1/3] arm: mvebu: Add some SPI CS attributes
by Stefan Roese 24 Mar '16

24 Mar '16

These attribute defines may be used to map an area of memory for direct access to the specific SPI devices. See SPI Direct Access Mode for further information. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 017d55f..dd58b4a 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -47,6 +47,9 @@ enum cpu_attrib { CPU_ATTR_DRAM_CS3 = 0x07, CPU_ATTR_NANDFLASH = 0x2f, CPU_ATTR_SPIFLASH = 0x1e, + CPU_ATTR_SPI0_CS0 = 0x1e, + CPU_ATTR_SPI0_CS1 = 0x5e, + CPU_ATTR_SPI1_CS2 = 0x9a, CPU_ATTR_BOOTROM = 0x1d, CPU_ATTR_PCIE_IO = 0xe0, CPU_ATTR_PCIE_MEM = 0xe8, -- 2.7.1

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[U-Boot] [PATCH] fpga: altera: Add StratixV support
by Stefan Roese 24 Mar '16

24 Mar '16

This patch adds support for programming of the StratixV FPGAs. Programming is done in this case (board theadorable) via SPI. The board may provide board specific code for bitstream programming. This StratixV support will be used by the theadorable board. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> --- drivers/fpga/Makefile | 1 + drivers/fpga/altera.c | 3 ++ drivers/fpga/stratixv.c | 103 ++++++++++++++++++++++++++++++++++++++++++++++++ include/altera.h | 20 ++++++++++ 4 files changed, 127 insertions(+) create mode 100644 drivers/fpga/stratixv.c diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 6aa24d4..fec3fec 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -17,5 +17,6 @@ obj-y += altera.o obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o +obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o endif diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index a5bfe5d..135a357 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -37,6 +37,9 @@ static const struct altera_fpga { { Altera_StratixII, "StratixII", StratixII_load, StratixII_dump, StratixII_info }, #endif +#if defined(CONFIG_FPGA_STRATIX_V) + { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL }, +#endif #if defined(CONFIG_FPGA_SOCFPGA) { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, #endif diff --git a/drivers/fpga/stratixv.c b/drivers/fpga/stratixv.c new file mode 100644 index 0000000..cc035eb --- /dev/null +++ b/drivers/fpga/stratixv.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <altera.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/errno.h> + +/* Write the RBF data to FPGA via SPI */ +static int program_write(int spi_bus, int spi_dev, const void *rbf_data, + unsigned long rbf_size) +{ + struct spi_slave *slave; + int ret; + + debug("%s (%d): data=%p size=%ld\n", + __func__, __LINE__, rbf_data, rbf_size); + + /* FIXME: How to get the max. SPI clock and SPI mode? */ + slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3); + if (!slave) + return -1; + + if (spi_claim_bus(slave)) + return -1; + + ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data, + SPI_XFER_BEGIN | SPI_XFER_END); + + spi_release_bus(slave); + + return ret; +} + +/* + * This is the interface used by FPGA driver. + * Return 0 for sucess, non-zero for error. + */ +int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) +{ + altera_board_specific_func *pfns = desc->iface_fns; + int cookie = desc->cookie; + int spi_bus; + int spi_dev; + int ret = 0; + + if ((u32)rbf_data & 0x3) { + puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); + return -EINVAL; + } + + /* Run the pre configuration function if there is one */ + if (pfns->pre) + (pfns->pre)(cookie); + + /* Establish the initial state */ + if (pfns->config) { + /* De-assert nCONFIG */ + (pfns->config)(false, true, cookie); + + /* nConfig minimum low pulse width is 2us */ + udelay(200); + + /* Assert nCONFIG */ + (pfns->config)(true, true, cookie); + + /* nCONFIG high to first rising clock on DCLK min 1506 us */ + udelay(1600); + } + + /* Write the RBF data to FPGA */ + if (pfns->write) { + /* + * Use board specific data function to write bitstream + * into the FPGA + */ + ret = (pfns->write)(rbf_data, rbf_size, true, cookie); + } else { + /* + * Use common SPI functions to write bitstream into the + * FPGA + */ + spi_bus = COOKIE2SPI_BUS(cookie); + spi_dev = COOKIE2SPI_DEV(cookie); + ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size); + } + if (ret) + return ret; + + /* Check done pin */ + if (pfns->done) { + ret = (pfns->done)(cookie); + + if (ret) + printf("Error: DONE not set (ret=%d)!\n", ret); + } + + return ret; +} diff --git a/include/altera.h b/include/altera.h index c2991ad..48d3eb7 100644 --- a/include/altera.h +++ b/include/altera.h @@ -10,6 +10,19 @@ #ifndef _ALTERA_H_ #define _ALTERA_H_ +/* + * For the StratixV FPGA programming via SPI, the following + * information is coded in the 32bit cookie: + * Bit 31 ... Bit 0 + * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin + */ +#define FPGA_COOKIE(bus, dev, config, done) \ + (((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done)) +#define COOKIE2SPI_BUS(c) (((c) >> 24) & 0xff) +#define COOKIE2SPI_DEV(c) (((c) >> 16) & 0xff) +#define COOKIE2CONFIG(c) (((c) >> 8) & 0xff) +#define COOKIE2DONE(c) ((c) & 0xff) + enum altera_iface { /* insert all new types after this */ min_altera_iface_type, @@ -40,6 +53,8 @@ enum altera_family { Altera_CYC2, /* StratixII Family */ Altera_StratixII, + /* StratixV Family */ + Altera_StratixV, /* SoCFPGA Family */ Altera_SoCFPGA, @@ -89,6 +104,7 @@ typedef struct { Altera_done_fn done; Altera_clk_fn clk; Altera_data_fn data; + Altera_write_fn write; Altera_abort_fn abort; Altera_post_fn post; } altera_board_specific_func; @@ -97,4 +113,8 @@ typedef struct { int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); #endif +#ifdef CONFIG_FPGA_STRATIX_V +int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); +#endif + #endif /* _ALTERA_H_ */ -- 2.7.1

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[U-Boot] [PATCH] gpio: Add DM GPIO driver for Marvell MVEBU
by Stefan Roese 24 Mar '16

24 Mar '16

This patch adds a DM GPIO driver for the Marvell MVEBU SoCs. There are other non-DM drivers that might be used on these platforms. But this patch creates a new DM driver. Which will be used by all Armada XP/38x boards. Other MVEBU SoC (Kirkwood / Orion) may follow once they support DM as well. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Dirk Eibach <dirk.eibach(a)gdsys.cc> Cc: Phil Sutter <phil(a)nwl.cc> Cc: Kevin Smith <kevin.smith(a)elecsyscorp.com> Cc: Luka Perkov <luka.perkov(a)sartura.hr> Cc: Tom Rini <trini(a)konsulko.com> --- drivers/gpio/Kconfig | 7 +++ drivers/gpio/Makefile | 1 + drivers/gpio/mvebu_gpio.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+) create mode 100644 drivers/gpio/mvebu_gpio.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 845dc72..6147aa3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -90,4 +90,11 @@ config PIC32_GPIO help Say yes here to support Microchip PIC32 GPIOs. +config MVEBU_GPIO + bool "Marvell MVEBU GPIO driver" + depends on DM_GPIO && ARCH_MVEBU + default y + help + Say yes here to support Marvell MVEBU (Armada XP/38x) GPIOs. + endmenu diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 845a6d4..54d1706 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -47,3 +47,4 @@ obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o +obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o diff --git a/drivers/gpio/mvebu_gpio.c b/drivers/gpio/mvebu_gpio.c new file mode 100644 index 0000000..9564ce2 --- /dev/null +++ b/drivers/gpio/mvebu_gpio.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MVEBU_GPIOS_PER_BANK 32 + +struct mvebu_gpio_regs { + u32 data_out; + u32 io_conf; + u32 blink_en; + u32 in_pol; + u32 data_in; +}; + +struct mvebu_gpio_priv { + struct mvebu_gpio_regs *regs; + char name[2]; +}; + +static int mvebu_gpio_direction_input(struct udevice *dev, unsigned int gpio) +{ + struct mvebu_gpio_priv *priv = dev_get_priv(dev); + struct mvebu_gpio_regs *regs = priv->regs; + + setbits_le32(&regs->io_conf, BIT(gpio)); + + return 0; +} + +static int mvebu_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) +{ + struct mvebu_gpio_priv *priv = dev_get_priv(dev); + struct mvebu_gpio_regs *regs = priv->regs; + + clrbits_le32(&regs->io_conf, BIT(gpio)); + + return 0; +} + +static int mvebu_gpio_get_function(struct udevice *dev, unsigned gpio) +{ + struct mvebu_gpio_priv *priv = dev_get_priv(dev); + struct mvebu_gpio_regs *regs = priv->regs; + u32 val; + + val = readl(&regs->io_conf) & BIT(gpio); + if (val) + return GPIOF_INPUT; + else + return GPIOF_OUTPUT; +} + +static int mvebu_gpio_set_value(struct udevice *dev, unsigned gpio, + int value) +{ + struct mvebu_gpio_priv *priv = dev_get_priv(dev); + struct mvebu_gpio_regs *regs = priv->regs; + + if (value) + setbits_le32(&regs->data_out, BIT(gpio)); + else + clrbits_le32(&regs->data_out, BIT(gpio)); + + return 0; +} + +static int mvebu_gpio_get_value(struct udevice *dev, unsigned gpio) +{ + struct mvebu_gpio_priv *priv = dev_get_priv(dev); + struct mvebu_gpio_regs *regs = priv->regs; + + return !!(readl(&regs->data_in) & BIT(gpio)); +} + +static int mvebu_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct mvebu_gpio_priv *priv = dev_get_priv(dev); + + priv->regs = (struct mvebu_gpio_regs *)dev_get_addr(dev); + uc_priv->gpio_count = MVEBU_GPIOS_PER_BANK; + priv->name[0] = 'A' + dev->req_seq; + uc_priv->bank_name = priv->name; + + return 0; +} + +static const struct dm_gpio_ops mvebu_gpio_ops = { + .direction_input = mvebu_gpio_direction_input, + .direction_output = mvebu_gpio_direction_output, + .get_function = mvebu_gpio_get_function, + .get_value = mvebu_gpio_get_value, + .set_value = mvebu_gpio_set_value, +}; + +static const struct udevice_id mvebu_gpio_ids[] = { + { .compatible = "marvell,orion-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_mvebu) = { + .name = "gpio_mvebu", + .id = UCLASS_GPIO, + .of_match = mvebu_gpio_ids, + .ops = &mvebu_gpio_ops, + .probe = mvebu_gpio_probe, + .priv_auto_alloc_size = sizeof(struct mvebu_gpio_priv), +}; -- 2.7.1

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