February 2016 - U-Boot

[U-Boot] FPGA detection failure on Cyclone V soc development kit
by Måns Rullgård 12 Apr '16

12 Apr '16

I'm having a problem with u-boot 2016.01 failing to detect the FPGA on my Altera Cyclone V SoC Development Kit. On startup, it simply prints "FPGA: Not Altera chip ID" (the ID having been read as all-zero). No amount of messing with jumpers or switches makes a difference. The software on the SD card included in the box appears to work, so on a whim I took the SPL pre-loader from this card and combined it with the main 2016.01 u-boot. This makes the detection succeed, despite Marek baulking at this idea. The "good" SPL identifies as "U-Boot SPL 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different build date than the main u-boot on the same SD card, so which source code version it was built from is anyone's guess. What's interesting is that Marek's board works with u-boot 2016.01 while mine fails even with the very same binary. The boards are different revisions (his 100-0321003-C1, mine -E1), and the main Cyclone V chips are also different (his 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N). Any suggestions for what to try next? -- Måns Rullgård

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[U-Boot] [RFC 0/2] Add cdns-i2c driver as drop in for zynq-i2c
by Moritz Fischer 12 Apr '16

12 Apr '16

Hi all, I spent some time moving over the zynq-i2c.c to support dm. While doing that I realized that renaming it to cdns-i2c might make sense since it now could be used with other SoCs that also use the the Cadence IP. This is a first shot, but I'd like to get some early feedback ;-) Cheers, Moritz PS: I skipped touching the Zynq board files for now, since I wanted to make sure I get the driver right first ;-) Moritz Fischer (2): i2c: Describe Cadence I2C devicetree bindings dm: i2c: Add driver for Cadence I2C IP doc/device-tree-bindings/i2c/i2c-cdns.txt | 20 ++ drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/i2c-cdns.c | 339 ++++++++++++++++++++++++++++++ 4 files changed, 367 insertions(+) create mode 100644 doc/device-tree-bindings/i2c/i2c-cdns.txt create mode 100644 drivers/i2c/i2c-cdns.c -- 2.4.3

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[U-Boot] [PATCH] fastboot: sparse: fix sparse blocks calculation
by Jeffy Chen 12 Apr '16

12 Apr '16

It may overflow in sparse_block_size_to_storage, use uint64_t instead in the calculation. Signed-off-by: Jeffy Chen <jeffy.chen(a)rock-chips.com> --- common/image-sparse.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/image-sparse.c b/common/image-sparse.c index 542a8c4..0c07976 100644 --- a/common/image-sparse.c +++ b/common/image-sparse.c @@ -62,7 +62,8 @@ static unsigned int sparse_block_size_to_storage(unsigned int size, sparse_storage_t *storage, sparse_header_t *sparse) { - return size * sparse->blk_sz / storage->block_sz; + return (unsigned int)lldiv((uint64_t)size * sparse->blk_sz, + storage->block_sz); } static bool sparse_chunk_has_buffer(chunk_header_t *chunk) -- 2.1.4

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[U-Boot] [PATCH v2 1/2] fastboot: sparse: fix block addressing for don't care chunk type
by Steve Rae 12 Apr '16

12 Apr '16

When 7bfc3b1 (sparse: Refactor chunk parsing function) was implemented, it dropped 9981945 (aboot: fix block addressing for don't care chunk type). This re-implements the required fix for the "don't care chunk type"... Signed-off-by: Steve Rae <srae(a)broadcom.com> --- Changes in v2: Handle MMC device differently than the NAND device. common/image-sparse.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/common/image-sparse.c b/common/image-sparse.c index dffe844..ef0d232 100644 --- a/common/image-sparse.c +++ b/common/image-sparse.c @@ -330,9 +330,13 @@ int store_sparse_image(sparse_storage_t *storage, void *storage_priv, * and go on parsing the rest of the chunks */ if (chunk_header->chunk_type == CHUNK_TYPE_DONT_CARE) { - skipped += sparse_block_size_to_storage(chunk_header->chunk_sz, - storage, - sparse_header); + blkcnt = sparse_block_size_to_storage(chunk_header->chunk_sz, + storage, + sparse_header); +#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV + total_blocks += blkcnt; +#endif + skipped += blkcnt; continue; } @@ -380,7 +384,7 @@ int store_sparse_image(sparse_storage_t *storage, void *storage_priv, printf("........ wrote %d blocks to '%s'\n", total_blocks, storage->name); - if ((total_blocks + skipped) != + if (total_blocks != sparse_block_size_to_storage(sparse_header->total_blks, storage, sparse_header)) { printf("sparse image write failure\n"); -- 1.8.5

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[U-Boot] [PATCH] arc: get rid of running_on_hw
by Alexey Brodkin 11 Apr '16

11 Apr '16

ISS is obsolete now and nSIM is used for simulation instead. In its turn nSIM properly handles baud-rate settings so get rid of now useless check. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- arch/arc/include/asm/global_data.h | 1 - arch/arc/lib/cpu.c | 6 ------ drivers/serial/serial_arc.c | 16 ---------------- 3 files changed, 23 deletions(-) diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h index d644e80..e25b966 100644 --- a/arch/arc/include/asm/global_data.h +++ b/arch/arc/include/asm/global_data.h @@ -9,7 +9,6 @@ /* Architecture-specific global data */ struct arch_global_data { - int running_on_hw; }; #include <asm-generic/global_data.h> diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index 4e4dd74..d1f10ab 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -14,12 +14,6 @@ int arch_cpu_init(void) { timer_init(); -/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */ - if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00) - gd->arch.running_on_hw = 0; - else - gd->arch.running_on_hw = 1; - gd->cpu_clk = CONFIG_SYS_CLK_FREQ; gd->ram_size = CONFIG_SYS_SDRAM_SIZE; diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c index 7dbb49f..36d6404 100644 --- a/drivers/serial/serial_arc.c +++ b/drivers/serial/serial_arc.c @@ -42,23 +42,7 @@ static int arc_serial_setbrg(struct udevice *dev, int baudrate) int arc_console_baud = gd->cpu_clk / (baudrate * 4) - 1; writeb(arc_console_baud & 0xff, &regs->baudl); - -#ifdef CONFIG_ARC - /* - * UART ISS(Instruction Set simulator) emulation has a subtle bug: - * A existing value of Baudh = 0 is used as a indication to startup - * it's internal state machine. - * Thus if baudh is set to 0, 2 times, it chokes. - * This happens with BAUD=115200 and the formaula above - * Until that is fixed, when running on ISS, we will set baudh to !0 - */ - if (gd->arch.running_on_hw) - writeb((arc_console_baud & 0xff00) >> 8, &regs->baudh); - else - writeb(1, &regs->baudh); -#else writeb((arc_console_baud & 0xff00) >> 8, &regs->baudh); -#endif return 0; } -- 2.5.0

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[U-Boot] [PATCH 0/4] QEMU (qemu-mips) and MIPS 64-bit changes
by Stanislav Galabov 10 Apr '16

10 Apr '16

Stanislav Galabov (4): - Properly calculate ATA_SECTORWORDS, using a fixed-size integer, so it works for both 32-bit and 64-bit targets - Use CONFIG_IDE_SWAP_IO when running on big-endian MIPS (32 or 64-bit) in QEMU so that IDE transfers work properly - Fix FreeBSD loader API so that it works on both 32-bit and 64-bit targets. Specifically tested on MIPS under QEMU (works with all combination of bit-ness and endian-ness) - Add support for 64-bit MIPS to examples/standalone api/api.c | 58 +++++++++++++++++++++---------------------- examples/api/Makefile | 4 +++ examples/api/crt0.S | 13 +++++----- examples/api/glue.c | 18 +++++++------- examples/standalone/stubs.c | 18 ++++++++++++++ include/ata.h | 2 +- include/configs/qemu-mips.h | 4 +++ include/configs/qemu-mips64.h | 4 +++ 8 files changed, 76 insertions(+), 45 deletions(-) -- 1.9.1

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[U-Boot] Fwd: Marvell Armada XP u-boot from uart
by Konstantin Lezhnyev 06 Apr '16

06 Apr '16

---------- Forwarded message ---------- From: Konstantin Lezhnyev <konst.ru(a)gmail.com> Date: 2015-05-26 13:30 GMT+05:00 Subject: Re: [U-Boot] Marvell Armada XP u-boot from uart To: Stefan Roese <sr(a)denx.de> I'm sorry, the wording of my question was too short. I have already fulfilled the steps described in the article. But the article describes loading of the image from manufacturer - it is not my case. 1. I create a configuration for my board from maxbcm config. 2. Set `BOOT_FROM` parameter in board\my\kwbimage.cfg to `uart`. 3. Set DDR timings/settings. 4. Upload and execute image via uart. 5. Memory training ended successfully. But then I get the following messages in the terminal: | >>spl:board_init_r() | boot device - 8 | ... | SPI probe failed. Boot device 8 - constant `BOOT_DEVICE_SPI`. Function code returns this value looks like: | u32 spl_boot_device(void) | { | /* Right now only booting via SPI NOR flash is supported */ | return BOOT_DEVICE_SPI; | } And now I repeat my question: >Is it possible to load and boot Marvell Armada XP u-boot completely from uart without spi or nand flash? Regards, kon5t. 2015-05-23 13:08 GMT+05:00 Stefan Roese <sr(a)denx.de>: > On 22.05.2015 16:12, Peter Robinson wrote: > >> Is it possible to load and boot Marvell Armada XP u-boot completely from >>> uart without spi or nand flash? >>> I have custom board with MV78460 and clean flash memory. >>> >> >> You can use kwboot I believe. >> > > Correct. kwboot can be used to upload and execute a binary (compiled for > UART booting) via UART. Please make sure to use the "-a" parameter for the > Armada XP timings. > > Thanks, > Stefan > >

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[U-Boot] [RFC PATCH v1] kirkwood_nand: claim MPP pins on the fly
by Chris Packham 06 Apr '16

06 Apr '16

Claim the MPP pins for the NAND flash controller only when it's actually being used. This allows the pins to be shared with the SPI interface which already supports an equivalent on-access MPP reconfiguration. Reviewed-by: Mark Tomlinson <mark.tomlinson(a)alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- I haven't wrapped this with a configuration option because I think it should be safe to enable by default. It will either re-apply the same MPP configuration that has already been done in the board init or put the MPP pins into the correct mode to access NAND. I've only got access to one kirkwood based board with NAND flash so I'd appreciate some feedback from someone with access to a few different boards. >From the datasheets I have access to it looks like there is only one possible MPP configuration for NF_IO[0-7] so that is what I've implemented. I'm not aware of anything using this driver that needs a different MPP config. drivers/mtd/nand/kirkwood_nand.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c index 4fc34d6..ff81212 100644 --- a/drivers/mtd/nand/kirkwood_nand.c +++ b/drivers/mtd/nand/kirkwood_nand.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/soc.h> +#include <asm/arch/mpp.h> #include <nand.h> /* NAND Flash Soc registers */ @@ -22,6 +23,8 @@ struct kwnandf_registers { static struct kwnandf_registers *nf_reg = (struct kwnandf_registers *)KW_NANDF_BASE; +static u32 nand_mpp_backup[9] = { 0 }; + /* * hardware specific access to control-lines/bits */ @@ -49,6 +52,22 @@ static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd, void kw_nand_select_chip(struct mtd_info *mtd, int chip) { u32 data; + u32 nand_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP18_NF_IO0, + MPP19_NF_IO1, + 0 + }; + + if (chip >= 0) + kirkwood_mpp_conf(nand_config, nand_mpp_backup); + else + kirkwood_mpp_conf(nand_mpp_backup, NULL); data = readl(&nf_reg->ctrl); data |= NAND_ACTCEBOOT_BIT; -- 2.7.0

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[U-Boot] [PATCH] spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU
by Stefan Roese 06 Apr '16

06 Apr '16

Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU. The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> Cc: Jagan Teki <jteki(a)openedev.com> --- arch/arm/include/asm/arch-mvebu/spi.h | 17 ++++++++++++----- drivers/spi/kirkwood_spi.c | 6 ++++++ 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h index e512dce..4b66499 100644 --- a/arch/arm/include/asm/arch-mvebu/spi.h +++ b/arch/arm/include/asm/arch-mvebu/spi.h @@ -32,13 +32,15 @@ struct kwspi_registers { #define SCK_MPP10 (1 << 1) #define MISO_MPP11 (1 << 2) +/* Control Register */ +#define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */ +#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ +#define KWSPI_CS_SHIFT 2 /* chip select shift */ +#define KWSPI_CS_MASK 0x7 /* chip select mask */ + +/* Configuration Register */ #define KWSPI_CLKPRESCL_MASK 0x1f #define KWSPI_CLKPRESCL_MIN 0x12 -#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ -#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ -#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ -#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ -#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ #define KWSPI_XFERLEN_1BYTE 0 #define KWSPI_XFERLEN_2BYTE (1 << 5) #define KWSPI_XFERLEN_MASK (1 << 5) @@ -47,6 +49,11 @@ struct kwspi_registers { #define KWSPI_ADRLEN_3BYTE (2 << 8) #define KWSPI_ADRLEN_4BYTE (3 << 8) #define KWSPI_ADRLEN_MASK (3 << 8) + +#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ +#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ +#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ + #define KWSPI_TIMEOUT 10000 #endif /* __KW_SPI_H__ */ diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 7890796..fa30be4 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -280,6 +280,12 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, struct udevice *bus = dev->parent; struct mvebu_spi_platdata *plat = dev_get_platdata(bus); +#ifdef CONFIG_ARCH_MVEBU + clrsetbits_le32(&plat->spireg->ctrl, + KWSPI_CS_MASK << KWSPI_CS_SHIFT, + spi_chip_select(dev) << KWSPI_CS_SHIFT); +#endif + return _spi_xfer(plat->spireg, bitlen, dout, din, flags); } -- 2.7.1

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[U-Boot] [PATCH] dm: ns16550: Add support for reg-offset property
by Michal Simek 05 Apr '16

05 Apr '16

reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/serial/ns16550.c | 6 ++++-- include/ns16550.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 93dad338b375..28da9ddfd859 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -105,7 +105,7 @@ static void ns16550_writeb(NS16550_t port, int offset, int value) * As far as we know it doesn't make sense to support selection of * these options at run-time, so use the existing CONFIG options. */ - serial_out_shift(addr, plat->reg_shift, value); + serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); } static int ns16550_readb(NS16550_t port, int offset) @@ -116,7 +116,7 @@ static int ns16550_readb(NS16550_t port, int offset) offset *= 1 << plat->reg_shift; addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset; - return serial_in_shift(addr, plat->reg_shift); + return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); } /* We can clean these up once everything is moved to driver model */ @@ -401,6 +401,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) return -EINVAL; plat->base = addr; + plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "reg-offset", 0); plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg-shift", 0); plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, diff --git a/include/ns16550.h b/include/ns16550.h index 4e620676c453..5eeacd6ff945 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -54,6 +54,7 @@ */ struct ns16550_platdata { unsigned long base; + int reg_offset; int reg_shift; int clock; }; -- 1.9.1

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