February 2016 - U-Boot

[U-Boot] [PATCH] ls102xa: fdt: Update FSL_QSPI_COMPAT and FSL_DSPI_COMPAT
by Alison Wang 22 Mar '16

22 Mar '16

As the compatible property values for QSPI and DSPI dts nodes are changed in kernel, FSL_QSPI_COMPAT and FSL_DSPI_COMPAT need to be updated too. Signed-off-by: Alison Wang <alison.wang(a)nxp.com> --- arch/arm/include/asm/arch-ls102xa/config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 424fe87..ab4b697 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -137,7 +137,7 @@ #endif #define FSL_IFC_COMPAT "fsl,ifc" -#define FSL_QSPI_COMPAT "fsl,ls1-qspi" -#define FSL_DSPI_COMPAT "fsl,vf610-dspi" +#define FSL_QSPI_COMPAT "fsl,ls1021a-qspi" +#define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi" #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2] drivers/crypto/fsl: add constructs for protocol descriptors
by Aneesh Bansal 22 Mar '16

22 Mar '16

Construct API's have been added to create Protocol Descriptors for CAAM block. CC: Ulises Cardenas <raul.casas(a)nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta(a)nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal(a)nxp.com> --- drivers/crypto/fsl/desc.h | 25 +++++++++++++++++++++++++ drivers/crypto/fsl/desc_constr.h | 27 +++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h index 18e2ec8..1c13fbc 100644 --- a/drivers/crypto/fsl/desc.h +++ b/drivers/crypto/fsl/desc.h @@ -436,6 +436,31 @@ #define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT) #define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT) #define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT) +#define OP_PCLID_DSA_SIGN (0x15 << OP_PCLID_SHIFT) +#define OP_PCLID_DSA_VERIFY (0x16 << OP_PCLID_SHIFT) + +/* Assuming OP_TYPE = OP_TYPE_DECAP_PROTOCOL */ +#define OP_PCLID_MP_PUB_KEY (0x14 << OP_PCLID_SHIFT) +#define OP_PCLID_MP_SIGN (0x15 << OP_PCLID_SHIFT) + +/* Assuming OP_TYPE = OP_TYPE_ENCAP_PROTOCOL */ +#define OP_PCLID_MP_PRIV_KEY (0x14 << OP_PCLID_SHIFT) + +/* PROTINFO fields for discrete log public key protocols */ +#define OP_PROTINFO_F2M_FP 0x00000001 +#define OP_PROTINFO_ECC_DL 0x00000002 +#define OP_PROTINFO_ENC_PRI 0x00000004 +#define OP_PROTINFO_TEST 0x00000008 +#define OP_PROTINFO_EXT_PRI 0x00000010 +#define OP_PROTINFO_ENC_Z 0x00000020 +#define OP_PROTINFO_EKT_Z 0x00000040 +#define OP_PROTINFO_MES_REP 0x00000400 +#define OP_PROTINFO_HASH_MD5 0x00000000 +#define OP_PROTINFO_HASH_SHA1 0x00000080 +#define OP_PROTINFO_HASH_SHA224 0x00000100 +#define OP_PROTINFO_HASH_SHA256 0x00000180 +#define OP_PROTINFO_HASH_SHA384 0x00000200 +#define OP_PROTINFO_HASH_SHA512 0x00000280 /* For non-protocol/alg-only op commands */ #define OP_ALG_TYPE_SHIFT 24 diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index 2559ccd..4ea93b0 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -53,6 +53,19 @@ union ptr_addr_t { }; #endif +static inline void pdb_add_ptr(dma_addr_t *offset, dma_addr_t ptr) +{ +#ifdef CONFIG_PHYS_64BIT + /* The Position of low and high part of 64 bit address + * will depend on the endianness of CAAM Block */ + union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset; + ptr_addr->m_halfs.high = (u32)(ptr >> 32); + ptr_addr->m_halfs.low = (u32)ptr; +#else + *offset = ptr; +#endif +} + static inline int desc_len(u32 *desc) { return *desc & HDR_DESCLEN_MASK; @@ -68,6 +81,11 @@ static inline u32 *desc_end(u32 *desc) return desc + desc_len(desc); } +static inline void *desc_pdb(u32 *desc) +{ + return desc + 1; +} + static inline void init_desc(u32 *desc, u32 options) { *desc = (options | HDR_ONE) + 1; @@ -78,6 +96,15 @@ static inline void init_job_desc(u32 *desc, u32 options) init_desc(desc, CMD_DESC_HDR | options); } +static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes) +{ + u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ; + + init_job_desc(desc, + (((pdb_len + 1) << HDR_START_IDX_SHIFT) + pdb_len) | + options); +} + static inline void append_ptr(u32 *desc, dma_addr_t ptr) { dma_addr_t *offset = (dma_addr_t *)desc_end(desc); -- 1.8.1.4

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[U-Boot] [PATCH] drivers/crypto/fsl: correct error checking in run_descriptor
by Aneesh Bansal 22 Mar '16

22 Mar '16

When CAAM runs a descriptor and an error occurs, a non-zero value is set in Output Status Register. The if condition should check the status for a non-zero value. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)nxp.com> --- drivers/crypto/fsl/jr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index b553e3c..f4069b5 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -353,7 +353,7 @@ int run_descriptor_jr(uint32_t *desc) } } - if (!op.status) { + if (op.status) { debug("Error %x\n", op.status); ret = op.status; } -- 1.8.1.4

2 1

[U-Boot] [PATCH][v2] armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY
by shh.xie＠gmail.com 22 Mar '16

22 Mar '16

From: Shaohui Xie <Shaohui.Xie(a)nxp.com> To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins polarity by setting IRQCR register, because AQR405 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)nxp.com> --- changes in v2: 1. move Interrupt register offset define to immap_lsch3.h. arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++ board/freescale/ls2080ardb/ls2080ardb.c | 4 ++++ include/configs/ls2080ardb.h | 1 + 3 files changed, 9 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index cd96604..f182dea 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -94,6 +94,10 @@ #define DCFG_DCSR_BASE 0X700100000ULL #define DCFG_DCSR_PORCR1 0x000 +/* Interrupt Sampling Control */ +#define ISC_BASE 0x01F70000 +#define IRQCR_OFFSET 0x14 + /* Supplemental Configuration */ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 2ae9d6c..da227a7 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -149,6 +149,7 @@ int board_init(void) { char *env_hwconfig; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; u32 val; init_final_memctl_regs(); @@ -170,6 +171,9 @@ int board_init(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); + /* invert AQR405 IRQ pins polarity */ + out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); + return 0; } diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 65d4f64..0d60420 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -336,6 +336,7 @@ unsigned long get_board_sys_clk(void); #define AQ_PHY_ADDR2 0x01 #define AQ_PHY_ADDR3 0x02 #define AQ_PHY_ADDR4 0x03 +#define AQR405_IRQ_MASK 0x36 #define CONFIG_MII #define CONFIG_ETHPRIME "DPNI1" -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: lsch3: Enable WUO config for RNI-20 node
by Prabhakar Kushwaha 22 Mar '16

22 Mar '16

Enable wuo config to accelerate coherent ordered writes for LS2080A and LS2085A. WRIOP IP is connected to RNI-20 Node. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 8 ++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++ arch/arm/lib/ccn504.S | 21 +++++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 41e1704..9c69ed1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -18,6 +18,14 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ #ifdef CONFIG_FSL_LSCH3 + + /* Set Wuo bit for RN-I 20 */ +#if defined(CONFIG_LS2085A) || defined (CONFIG_LS2080A) + ldr x0, =CCI_AUX_CONTROL_BASE(20) + ldr x1, =0x00000010 + bl ccn504_set_aux +#endif + /* Add fully-coherent masters to DVM domain */ ldr x0, =CCI_MN_BASE ldr x1, =CCI_MN_RNF_NODEID_LIST diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 49b113d..f5a8595 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -91,6 +91,8 @@ #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) +#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) + /* TZ Protection Controller Definitions */ #define TZPC_BASE 0x02200000 #define TZPCR0SIZE_BASE (TZPC_BASE) diff --git a/arch/arm/lib/ccn504.S b/arch/arm/lib/ccn504.S index 7570c7b..1e07876 100644 --- a/arch/arm/lib/ccn504.S +++ b/arch/arm/lib/ccn504.S @@ -59,3 +59,24 @@ ENTRY(ccn504_set_qos) ret ENDPROC(ccn504_set_qos) +/************************************************************************* + * + * void ccn504_set_aux(CCI_AUX_CONTROL_BASE, Value); + * + * Initialize AUX control settings + * + *************************************************************************/ +ENTRY(ccn504_set_aux) + /* + * x0: CCI_AUX_CONTROL_BASE + * x1: Value + */ + + ldr x9, [x0] + mov x10, x1 + orr x9, x9, x10 + str x9, [x0] + + ret +ENDPROC(ccn504_set_aux) + -- 1.9.1

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[U-Boot] Problem with attaching UBI partition
by Bakhvalov, Denis (Nokia - PL/Wroclaw) 22 Mar '16

22 Mar '16

Dear U-Boot support, I have problems while running following commands in U-Boot: U-Boot => sf probe 0 0 0 SF: Detected S25FL512S with page size 512, total: 67108864 U-Boot => mtdparts device nor0 <snor0>, # parts = 4 #: name size offset mask_flags 0: boot 0x00100000 0x00000000 0 1: bootenv 0x00080000 0x00100000 0 2: SomeInfo 0x01980000 0x00180000 0 3: ubifspart 0x02500000 0x01b00000 0 U-Boot => ubi part ubifspart mtd: Giving out device 1 to mtd=3 ubi0: attaching mtd1 UBI DBG gen (pid 1): sizeof(struct ubi_ainf_peb) 48 UBI DBG gen (pid 1): sizeof(struct ubi_wl_entry) 20 UBI DBG gen (pid 1): min_io_size 1 UBI DBG gen (pid 1): max_write_size 512 UBI DBG gen (pid 1): hdrs_min_io_size 1 UBI DBG gen (pid 1): ec_hdr_alsize 64 UBI DBG gen (pid 1): vid_hdr_alsize 64 UBI DBG gen (pid 1): vid_hdr_offset 64 UBI DBG gen (pid 1): vid_hdr_aloffset 64 UBI DBG gen (pid 1): vid_hdr_shift 0 UBI DBG gen (pid 1): leb_start 128 UBI DBG gen (pid 1): max_erroneous 16 UBI DBG gen (pid 1): process PEB 0 UBI DBG bld (pid 1): scan PEB 0 UBI DBG io (pid 1): read EC header from PEB 0 UBI DBG io (pid 1): read 64 bytes from PEB 0:0 ubi0 warning: ubi_io_read_ec_hdr: bad magic number at PEB 0: ff554249 instead of 55424923 Erase counter header dump: magic 0xff554249 version 35 ec 0 vid_hdr_offset 16777216 data_offset 1073741824 image_seq -2142856561 hdr_crc 0xe046ed erase counter header hexdump: UBI DBG bld (pid 1): bad magic number at PEB 0: ff554249 instead of 55424923 UBI DBG io (pid 1): read VID header from PEB 0 UBI DBG io (pid 1): read 64 bytes from PEB 0:64 UBI DBG bld (pid 1): no VID header found at PEB 0, only 0xFF bytes UBI DBG bld (pid 1): add to erase: PEB 0, EC -1 ... // this warning goes for all PEBs from 1 to 147 ubi0: scanning is finished UBI DBG gen (pid 1): max. sequence number: 0 ubi0 error: ubi_read_volume_table: the layout volume was not found ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -22 UBI error: cannot attach mtd1 UBI error: cannot initialize UBI, error -22 UBI init error 22 UBI init error 22 For me it looks like this magic number is shifted one byte right, although I can't understand why. Here is how I create UBI partition in Linux env: Linux Env #> mtdinfo -a mtd5 Name: data Type: nor Eraseblock size: 262144 bytes, 256.0 KiB Amount of eraseblocks: 148 (38797312 bytes, 37.0 MiB) Minimum input/output unit size: 1 byte Sub-page size: 1 byte Character device major/minor: 90:10 Bad blocks are allowed: false Device is writable: true Linux Env #> ubiformat /dev/mtd5 ubiformat: mtd5 (nor), size 38797312 bytes (37.0 MiB), 148 eraseblocks of 262144 bytes (256.0 KiB), min. I/O size 1 bytes libscan: scanning eraseblock 147 -- 100 % complete ubiformat: 148 eraseblocks are supposedly empty ubiformat: formatting eraseblock 147 -- 100 % complete 797312 Linux Env #> ubiattach -m 5 /dev/ubi_ctrl UBI: attaching mtd5 to ubi0 UBI: scanning is finished UBI: attached mtd5 (name "part5", size 37 MiB) to ubi0 UBI: PEB size: 262144 bytes (256 KiB), LEB size: 262016 bytes UBI: min./max. I/O unit sizes: 1/256, sub-page size 1 UBI: VID header offset: 64 (aligned 64), data offset: 128 UBI: good PEBs: 148, bad PEBs: 0, corrupted PEBs: 0 UBI: user volume: 0, internal volumes: 1, max. volumes count: 128 UBI: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 1371523162 UBI: available PEBs: 144, total reserved PEBs: 4, PEBs reserved for bad PEB handling: 0 UBI: background thread "ubi_bgt0d" started, PID 1003 Linux Env #> ubimkvol -N data -m /dev/ubi0 Linux Env #> mount -t ubifs ubi0:data /mnt Linux Env #> mount -t ubifs ubi0:data /mnt UBIFS: default file-system created UBIFS: background thread "ubifs_bgt0_0" started, PID 1010 UBIFS: mounted UBI device 0, volume 0, name "data" UBIFS: LEB size: 262016 bytes (255 KiB), min./max. I/O unit sizes: 8 bytes/256 bytes UBIFS: FS size: 35110144 bytes (33 MiB, 134 LEBs), journal size 2096129 bytes (1 MiB, 7 LEBs) UBIFS: reserved for root: 1658338 bytes (1619 KiB) UBIFS: media format: w4/r0 (latest is w4/r0), UUID 696FFD7B-1957-4ABD-9FDC-ED0EEB674D9D, small LPT model It's perfectly working from Linux env, however U-Boot don't want to attach UBI partition. Please help me identify the problem! Best regards, Denis Bakhvalov

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[U-Boot] [PATCH v6 00/76] mtd: Add SPI-NOR core support
by Jagan Teki 21 Mar '16

21 Mar '16

Compared to previous patch series this series adds spi-nor core with spi-nor controller drivers are of "mtd uclass" This is whole series for all spi-nor related changes, and while series tested on spansion spi-nor chip. Know issue: - arch/x86/lib/mrccache.c uses dm_spi_flash_ops, this need to fix. Why this framework: Some of the SPI device drivers at drivers/spi not a real spi controllers, Unlike normal/generic SPI controllers they operates only with SPI-NOR flash devices. these were technically termed as SPI-NOR controllers, Ex: drivers/spi/fsl_qspi.c The problem with these were resides at drivers/spi is entire SPI layer becomes SPI-NOR flash oriented which is absolutely a wrong indication where SPI layer getting effected more with flash operations - So this SPI-NOR core will resolve this issue by separating all SPI-NOR flash operations from spi layer and creats a generic layer called SPI-NOR core which can be used to interact SPI-NOR to SPI driver interface layer and the SPI-NOR controller driver. The idea is taken from Linux spi-nor framework. Before SPI-NOR: ----------------------- cmd/sf.c ----------------------- spi_flash.c ----------------------- sf_probe.c ----------------------- spi-uclass ----------------------- spi drivers ----------------------- SPI NOR chip ----------------------- After SPI-NOR: ------------------------------ cmd/sf.c ------------------------------ spi-nor.c ------------------------------- m25p80.c spi nor drivers ------------------------------- spi-uclass SPI NOR chip ------------------------------- spi drivers ------------------------------- SPI NOR chip ------------------------------- SPI-NOR with MTD: ------------------------------ cmd/sf.c ------------------------------ MTD core ------------------------------ spi-nor.c ------------------------------- m25p80.c spi nor drivers ------------------------------- spi-uclass SPI NOR chip ------------------------------- spi drivers ------------------------------- SPI NOR chip ------------------------------- drivers/mtd/spi-nor/spi-nor.c: spi-nor core drivers/mtd/spi-nor/m25p80.c: mtd uclass driver which is an interface layer b/w spi-nor core drivers/spi drivers/mtd/spi-nor/fsl_qspi.c: spi-nor controller driver(mtd uclass) Changes for v6: - Fixed git bisectable issues, with buildman. - Fixed spi-nor compilation issues - newly designed changes. Changes for v5: - newly designed changes Testing: $ git clone git://git.denx.de/u-boot-spi.git $ cd u-boot-spi $ git checkout -b spi-nor origin/spi-nor Jagan Teki (76): mtd: Add m25p80 driver mtd: Add Kconfig entry for MTD_M25P80 mtd: Add SPI-NOR core support doc: device-tree-bindings: jedec,spi-nor mtd: spi-nor: Add Kconfig entry for MTD_SPI_NOR mtd: spi-nor: Add kconfig for MTD_SPI_NOR_USE_4K_SECTORS mtd: spi-nor: Add MTD support mtd: spi-nor: Add spi_nor support in m25p80 mtd: spi-nor: Add dm spi-nor probing mtd: spi-nor: Add spi_flash_probe for mtd-dm-spi-nor mtd: spi-nor: Add spi_flash_free for mtd-dm-spi-nor mtd: spi-nor: m25p80: Add spi_nor support for non-dm sf: Rename erase_size to erasesize sf: Use erasesize instead of sector_size sf: Use uint64_t for flash->size spi_flash: Use mtd_info operation for SPI-NOR spi_flash: Use spi_flash_t instead of struct spi_flash mtd: spi-nor: Move spi_read_then_write to spi layer spi: Rename spi_read_then_write to spi_write_then_read mtd: spi-nor: Rename SPI_FLASH_BAR to SPI_NOR_BAR mtd: spi-nor: Add Kconfig entry for SPI_NOR_BAR mtd: spi-nor: Copy spl files from drivers/mtd/spi mtd: spi-nor: spl: Follow ascending order of include headers mtd: spi-nor: fsl_espi_spl: Use mtd_info mtd: spi-nor: spi_spl_load: Use mtd_info mtd: spi-nor: Add flash vendor Kconfig entries arm: zynq: Kconfig: Select MTD uclass arm: zynq: Kconfig: Drop DM_SPI_FLASH defconfigs: zynq_microzed: Drop CONFIG_SPI_FLASH defconfig: zynq_microzed: Enable CONFIG_MTD_M25P80 defconfig: zynq_microzed: Enable CONFIG_MTD_SPI_NOR spl: Add CONFIG_SPL_SPI_NOR_SUPPORT configs: zynq: Use CONFIG_SPL_SPI_NOR_SUPPORT configs: zynq: Use CONFIG_SPL_MTD_SUPPORT mtd: spi-nor: Copy sf_dataflash mtd: dataflash: Remove unneeded spi data mtd: dataflash: Move flash id detection into jedec_probe mtd: dataflash: Fix add_dataflash return logic mtd: dataflash: Add UCLASS_MTD support mtd: dataflash: Use spi_write_then_read mtd: dataflash: Drop sf_internal.h mtd: dataflash: Minor cleanups mtd: Rename sf_dataflash.c to mtd_dataflash.c mtd: spi-nor: Add Kconfig entry for mtd_dataflash mtd: dataflash: Add MTD_DATAFLASH_WRITE_VERIFY mtd: spi-nor: Add kconfig MTD_DATAFLASH_WRITE_VERIFY configs: ls1021aqds: Drop DM_SPI_FLASH and DATAFLASH defconfig: ls1021aqds_qspi: Enable SPI-NOR defconfig: ls1021aqds_qspi: Enable CONFIG_MTD_DATAFLASH mtd: spi-nor: Copy sandbox mtd: spi-nor: sandbox: Use spi-nor header mtd: spi-nor: Add SPI_NOR_SANBOX sandbox: kconfig: Drop DM_SPI_FLASH sandbox: kconfig: Select MTD uclass defconfigs: sandbox: Enable SPI-NOR mtd: sandbox: Use CONFIG_MTD_SPI_NOR defconfigs: sandbox: Enable SPI_NOR_SANDBOX spi_flash: Use spi_flash_t mtd: spi-nor: Add CONFIG_SPI_NOR_MISC config: Enable SPI-NOR framework spi-nor: Use CONFIG_MTD_SPI_NOR configs: Use CONFIG_MTD_SPI_NOR configs: Use CONFIG_SPI_NOR_BAR configs: spi-nor: Add new flash vendor configs configs: Use CONFIG_SPI_NOR_MISC spi: Drop mode_rx spi: Drop SPI_RX_FAST configs: Enable MTD uclass in missing configs configs: Drop CONFIG_SPI_FLASH_MTD uclass: Replace UCLASS_SPI_FLASH with UCLASS_MTD uclass: Drop UCLASS_SPI_FLASH configs: Use CONFIG_SPL_SPI_NOR_SUPPORT configs: Enable CONFIG_SPL_MTD_SUPPORT sf: Drop entire spi-flash framework MAINTAINERS: Add myself as SPI NOR maintainer configs: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS MAINTAINERS | 11 +- Makefile | 2 +- arch/Kconfig | 4 +- arch/arm/Kconfig | 10 +- arch/arm/mach-rockchip/Kconfig | 2 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +- arch/arm/mach-tegra/Kconfig | 2 +- arch/x86/lib/mrccache.c | 3 +- board/Arcturus/ucp1020/cmd_arc.c | 2 +- board/Synology/common/cmd_syno.c | 2 +- board/buffalo/lsxl/lsxl.c | 2 +- board/congatec/cgtqmx6eval/cgtqmx6eval.c | 2 +- board/davinci/da8xxevm/da850evm.c | 4 +- board/davinci/ea20/ea20.c | 2 +- board/renesas/sh7752evb/sh7752evb.c | 4 +- board/renesas/sh7753evb/sh7753evb.c | 4 +- board/renesas/sh7757lcr/sh7757lcr.c | 6 +- board/siemens/taurus/taurus.c | 2 +- cmd/sf.c | 38 +- common/env_sf.c | 6 +- common/splash_source.c | 4 +- configs/B4420QDS_NAND_defconfig | 5 +- configs/B4420QDS_SPIFLASH_defconfig | 5 +- configs/B4420QDS_defconfig | 5 +- configs/B4860QDS_NAND_defconfig | 5 +- configs/B4860QDS_SECURE_BOOT_defconfig | 5 +- configs/B4860QDS_SPIFLASH_defconfig | 5 +- configs/B4860QDS_SRIO_PCIE_BOOT_defconfig | 5 +- configs/B4860QDS_defconfig | 5 +- configs/BSC9131RDB_NAND_SYSCLK100_defconfig | 5 +- configs/BSC9131RDB_NAND_defconfig | 5 +- configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig | 5 +- configs/BSC9131RDB_SPIFLASH_defconfig | 5 +- configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig | 5 +- configs/BSC9132QDS_NAND_DDRCLK100_defconfig | 5 +- configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig | 5 +- configs/BSC9132QDS_NAND_DDRCLK133_defconfig | 5 +- configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig | 5 +- configs/BSC9132QDS_NOR_DDRCLK100_defconfig | 5 +- configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig | 5 +- configs/BSC9132QDS_NOR_DDRCLK133_defconfig | 5 +- .../BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig | 5 +- configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig | 5 +- .../BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig | 5 +- configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig | 5 +- .../BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig | 5 +- configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig | 5 +- .../BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig | 5 +- configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig | 5 +- configs/C29XPCIE_NAND_defconfig | 7 +- configs/C29XPCIE_NOR_SECBOOT_defconfig | 7 +- configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 7 +- configs/C29XPCIE_SPIFLASH_defconfig | 7 +- configs/C29XPCIE_defconfig | 7 +- configs/M52277EVB_defconfig | 5 +- configs/M52277EVB_stmicro_defconfig | 5 +- configs/M54418TWR_defconfig | 5 +- configs/M54418TWR_nand_mii_defconfig | 5 +- configs/M54418TWR_nand_rmii_defconfig | 5 +- configs/M54418TWR_nand_rmii_lowfreq_defconfig | 5 +- configs/M54418TWR_serial_mii_defconfig | 5 +- configs/M54418TWR_serial_rmii_defconfig | 5 +- configs/M54451EVB_defconfig | 5 +- configs/M54451EVB_stmicro_defconfig | 5 +- configs/M54455EVB_a66_defconfig | 5 +- configs/M54455EVB_defconfig | 5 +- configs/M54455EVB_i66_defconfig | 5 +- configs/M54455EVB_intel_defconfig | 5 +- configs/M54455EVB_stm33_defconfig | 5 +- configs/MPC8536DS_36BIT_defconfig | 5 +- configs/MPC8536DS_SDCARD_defconfig | 5 +- configs/MPC8536DS_SPIFLASH_defconfig | 5 +- configs/MPC8536DS_defconfig | 5 +- configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 5 +- configs/P1010RDB-PA_36BIT_NAND_defconfig | 5 +- configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 5 +- configs/P1010RDB-PA_36BIT_NOR_defconfig | 5 +- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 5 +- .../P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 5 +- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 5 +- configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 5 +- configs/P1010RDB-PA_NAND_defconfig | 5 +- configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 5 +- configs/P1010RDB-PA_NOR_defconfig | 5 +- configs/P1010RDB-PA_SDCARD_defconfig | 5 +- configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 5 +- configs/P1010RDB-PA_SPIFLASH_defconfig | 5 +- configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 5 +- configs/P1010RDB-PB_36BIT_NAND_defconfig | 5 +- configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 5 +- configs/P1010RDB-PB_36BIT_NOR_defconfig | 5 +- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 5 +- .../P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 5 +- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 5 +- configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 5 +- configs/P1010RDB-PB_NAND_defconfig | 5 +- configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 5 +- configs/P1010RDB-PB_NOR_defconfig | 5 +- configs/P1010RDB-PB_SDCARD_defconfig | 5 +- configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 5 +- configs/P1010RDB-PB_SPIFLASH_defconfig | 5 +- configs/P1020RDB-PC_36BIT_NAND_defconfig | 5 +- configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 5 +- configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 5 +- configs/P1020RDB-PC_36BIT_defconfig | 5 +- configs/P1020RDB-PC_NAND_defconfig | 5 +- configs/P1020RDB-PC_SDCARD_defconfig | 5 +- configs/P1020RDB-PC_SPIFLASH_defconfig | 5 +- configs/P1020RDB-PC_defconfig | 5 +- configs/P1020RDB-PD_NAND_defconfig | 5 +- configs/P1020RDB-PD_SDCARD_defconfig | 5 +- configs/P1020RDB-PD_SPIFLASH_defconfig | 5 +- configs/P1020RDB-PD_defconfig | 5 +- configs/P1021RDB-PC_36BIT_NAND_defconfig | 5 +- configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 5 +- configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 5 +- configs/P1021RDB-PC_36BIT_defconfig | 5 +- configs/P1021RDB-PC_NAND_defconfig | 5 +- configs/P1021RDB-PC_SDCARD_defconfig | 5 +- configs/P1021RDB-PC_SPIFLASH_defconfig | 5 +- configs/P1021RDB-PC_defconfig | 5 +- configs/P1022DS_36BIT_NAND_defconfig | 5 +- configs/P1022DS_36BIT_SDCARD_defconfig | 5 +- configs/P1022DS_36BIT_SPIFLASH_defconfig | 5 +- configs/P1022DS_36BIT_defconfig | 5 +- configs/P1022DS_NAND_defconfig | 5 +- configs/P1022DS_SDCARD_defconfig | 5 +- configs/P1022DS_SPIFLASH_defconfig | 5 +- configs/P1022DS_defconfig | 5 +- configs/P1024RDB_36BIT_defconfig | 5 +- configs/P1024RDB_NAND_defconfig | 5 +- configs/P1024RDB_SDCARD_defconfig | 5 +- configs/P1024RDB_SPIFLASH_defconfig | 5 +- configs/P1024RDB_defconfig | 5 +- configs/P1025RDB_36BIT_defconfig | 5 +- configs/P1025RDB_NAND_defconfig | 5 +- configs/P1025RDB_SDCARD_defconfig | 5 +- configs/P1025RDB_SPIFLASH_defconfig | 5 +- configs/P1025RDB_defconfig | 5 +- configs/P2020RDB-PC_36BIT_NAND_defconfig | 5 +- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 5 +- configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 5 +- configs/P2020RDB-PC_36BIT_defconfig | 5 +- configs/P2020RDB-PC_NAND_defconfig | 5 +- configs/P2020RDB-PC_SDCARD_defconfig | 5 +- configs/P2020RDB-PC_SPIFLASH_defconfig | 5 +- configs/P2020RDB-PC_defconfig | 5 +- configs/P2041RDB_NAND_defconfig | 5 +- configs/P2041RDB_SDCARD_defconfig | 5 +- configs/P2041RDB_SECURE_BOOT_defconfig | 5 +- configs/P2041RDB_SPIFLASH_defconfig | 5 +- configs/P2041RDB_SRIO_PCIE_BOOT_defconfig | 5 +- configs/P2041RDB_defconfig | 5 +- configs/P3041DS_NAND_SECURE_BOOT_defconfig | 5 +- configs/P3041DS_NAND_defconfig | 5 +- configs/P3041DS_SDCARD_defconfig | 5 +- configs/P3041DS_SECURE_BOOT_defconfig | 5 +- configs/P3041DS_SPIFLASH_defconfig | 5 +- configs/P3041DS_SRIO_PCIE_BOOT_defconfig | 5 +- configs/P3041DS_defconfig | 5 +- configs/P4080DS_SDCARD_defconfig | 5 +- configs/P4080DS_SECURE_BOOT_defconfig | 5 +- configs/P4080DS_SPIFLASH_defconfig | 5 +- configs/P4080DS_SRIO_PCIE_BOOT_defconfig | 5 +- configs/P4080DS_defconfig | 5 +- configs/P5020DS_NAND_SECURE_BOOT_defconfig | 5 +- configs/P5020DS_NAND_defconfig | 5 +- configs/P5020DS_SDCARD_defconfig | 5 +- configs/P5020DS_SECURE_BOOT_defconfig | 5 +- configs/P5020DS_SPIFLASH_defconfig | 5 +- configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 5 +- configs/P5020DS_defconfig | 5 +- configs/P5040DS_NAND_SECURE_BOOT_defconfig | 5 +- configs/P5040DS_NAND_defconfig | 5 +- configs/P5040DS_SDCARD_defconfig | 5 +- configs/P5040DS_SECURE_BOOT_defconfig | 5 +- configs/P5040DS_SPIFLASH_defconfig | 5 +- configs/P5040DS_defconfig | 5 +- configs/T1023RDB_NAND_defconfig | 5 +- configs/T1023RDB_SDCARD_defconfig | 5 +- configs/T1023RDB_SECURE_BOOT_defconfig | 5 +- configs/T1023RDB_SPIFLASH_defconfig | 5 +- configs/T1023RDB_defconfig | 5 +- configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 9 +- configs/T1024QDS_DDR4_defconfig | 9 +- configs/T1024QDS_NAND_defconfig | 9 +- configs/T1024QDS_SDCARD_defconfig | 9 +- configs/T1024QDS_SECURE_BOOT_defconfig | 9 +- configs/T1024QDS_SPIFLASH_defconfig | 9 +- configs/T1024QDS_defconfig | 9 +- configs/T1024RDB_NAND_defconfig | 5 +- configs/T1024RDB_SDCARD_defconfig | 5 +- configs/T1024RDB_SECURE_BOOT_defconfig | 5 +- configs/T1024RDB_SPIFLASH_defconfig | 5 +- configs/T1024RDB_defconfig | 5 +- configs/T1040D4RDB_NAND_defconfig | 5 +- configs/T1040D4RDB_SDCARD_defconfig | 5 +- configs/T1040D4RDB_SECURE_BOOT_defconfig | 5 +- configs/T1040D4RDB_SPIFLASH_defconfig | 5 +- configs/T1040D4RDB_defconfig | 5 +- configs/T1040QDS_DDR4_defconfig | 9 +- configs/T1040QDS_SECURE_BOOT_defconfig | 9 +- configs/T1040QDS_defconfig | 9 +- configs/T1040RDB_NAND_defconfig | 5 +- configs/T1040RDB_SDCARD_defconfig | 5 +- configs/T1040RDB_SECURE_BOOT_defconfig | 5 +- configs/T1040RDB_SPIFLASH_defconfig | 5 +- configs/T1040RDB_defconfig | 5 +- configs/T1042D4RDB_NAND_defconfig | 5 +- configs/T1042D4RDB_SDCARD_defconfig | 5 +- configs/T1042D4RDB_SECURE_BOOT_defconfig | 5 +- configs/T1042D4RDB_SPIFLASH_defconfig | 5 +- configs/T1042D4RDB_defconfig | 5 +- configs/T1042RDB_PI_NAND_defconfig | 5 +- configs/T1042RDB_PI_SDCARD_defconfig | 5 +- configs/T1042RDB_PI_SPIFLASH_defconfig | 5 +- configs/T1042RDB_PI_defconfig | 5 +- configs/T1042RDB_SECURE_BOOT_defconfig | 5 +- configs/T1042RDB_defconfig | 5 +- configs/T2080QDS_NAND_defconfig | 9 +- configs/T2080QDS_SDCARD_defconfig | 9 +- configs/T2080QDS_SECURE_BOOT_defconfig | 9 +- configs/T2080QDS_SPIFLASH_defconfig | 9 +- configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 9 +- configs/T2080QDS_defconfig | 9 +- configs/T2080RDB_NAND_defconfig | 5 +- configs/T2080RDB_SDCARD_defconfig | 5 +- configs/T2080RDB_SECURE_BOOT_defconfig | 5 +- configs/T2080RDB_SPIFLASH_defconfig | 5 +- configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 5 +- configs/T2080RDB_defconfig | 5 +- configs/T2081QDS_NAND_defconfig | 9 +- configs/T2081QDS_SDCARD_defconfig | 9 +- configs/T2081QDS_SPIFLASH_defconfig | 9 +- configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 9 +- configs/T2081QDS_defconfig | 9 +- configs/T4160QDS_NAND_defconfig | 5 +- configs/T4160QDS_SDCARD_defconfig | 5 +- configs/T4160QDS_SECURE_BOOT_defconfig | 5 +- configs/T4160QDS_defconfig | 5 +- configs/T4160RDB_defconfig | 5 +- configs/T4240QDS_NAND_defconfig | 5 +- configs/T4240QDS_SDCARD_defconfig | 5 +- configs/T4240QDS_SECURE_BOOT_defconfig | 5 +- configs/T4240QDS_SRIO_PCIE_BOOT_defconfig | 5 +- configs/T4240QDS_defconfig | 5 +- configs/T4240RDB_SDCARD_defconfig | 5 +- configs/T4240RDB_defconfig | 5 +- configs/UCP1020_SPIFLASH_defconfig | 9 +- configs/UCP1020_defconfig | 9 +- configs/alt_defconfig | 7 +- configs/am335x_boneblack_defconfig | 5 +- configs/am335x_boneblack_vboot_defconfig | 5 +- configs/am335x_evm_defconfig | 5 +- configs/am335x_evm_nor_defconfig | 5 +- configs/am335x_evm_norboot_defconfig | 5 +- configs/am335x_evm_spiboot_defconfig | 5 +- configs/am335x_evm_usbspl_defconfig | 5 +- configs/am335x_gp_evm_defconfig | 5 +- configs/am437x_gp_evm_defconfig | 5 +- configs/am437x_sk_evm_defconfig | 9 +- configs/am43xx_evm_defconfig | 7 +- configs/am43xx_evm_ethboot_defconfig | 5 +- configs/am43xx_evm_qspiboot_defconfig | 5 +- configs/am43xx_evm_usbhost_boot_defconfig | 5 +- configs/am57xx_evm_defconfig | 5 +- configs/aristainetos2_defconfig | 5 +- configs/aristainetos2b_defconfig | 5 +- configs/aristainetos_defconfig | 5 +- configs/at91sam9n12ek_mmc_defconfig | 5 +- configs/at91sam9n12ek_nandflash_defconfig | 5 +- configs/at91sam9n12ek_spiflash_defconfig | 5 +- configs/at91sam9x5ek_dataflash_defconfig | 5 +- configs/at91sam9x5ek_mmc_defconfig | 5 +- configs/at91sam9x5ek_nandflash_defconfig | 5 +- configs/at91sam9x5ek_spiflash_defconfig | 5 +- configs/atngw100_defconfig | 5 +- configs/atngw100mkii_defconfig | 5 +- configs/axm_defconfig | 5 +- configs/bayleybay_defconfig | 9 +- configs/beaver_defconfig | 5 +- configs/bf518f-ezbrd_defconfig | 7 +- configs/bf525-ucr2_defconfig | 5 +- configs/bf526-ezbrd_defconfig | 5 +- configs/bf527-ad7160-eval_defconfig | 5 +- configs/bf527-ezkit-v2_defconfig | 5 +- configs/bf527-ezkit_defconfig | 5 +- configs/bf527-sdp_defconfig | 16 +- configs/bf537-minotaur_defconfig | 5 +- configs/bf537-pnav_defconfig | 5 +- configs/bf537-srv1_defconfig | 5 +- configs/bf537-stamp_defconfig | 16 +- configs/bf548-ezkit_defconfig | 5 +- configs/bf561-acvilon_defconfig | 5 +- configs/bf609-ezkit_defconfig | 16 +- configs/bg0900_defconfig | 7 +- configs/birdland_bav335a_defconfig | 5 +- configs/birdland_bav335b_defconfig | 5 +- configs/blackstamp_defconfig | 5 +- configs/blackvme_defconfig | 5 +- configs/br4_defconfig | 5 +- configs/cardhu_defconfig | 5 +- configs/chromebook_link_defconfig | 9 +- configs/chromebox_panther_defconfig | 9 +- configs/clearfog_defconfig | 3 +- configs/cm_fx6_defconfig | 17 +- .../controlcenterd_36BIT_SDCARD_DEVELOP_defconfig | 5 +- configs/controlcenterd_36BIT_SDCARD_defconfig | 5 +- configs/coreboot-x86_defconfig | 9 +- configs/crownbay_defconfig | 11 +- configs/d2net_v2_defconfig | 5 +- configs/da850_am18xxevm_defconfig | 7 +- configs/da850evm_defconfig | 7 +- configs/da850evm_direct_nor_defconfig | 7 +- configs/dalmore_defconfig | 5 +- configs/db-88f6820-gp_defconfig | 7 +- configs/db-mv784mp-gp_defconfig | 7 +- configs/dra72_evm_defconfig | 9 +- configs/dra74_evm_defconfig | 9 +- configs/dra7xx_evm_defconfig | 7 +- configs/dra7xx_evm_qspiboot_defconfig | 5 +- configs/dra7xx_evm_uart3_defconfig | 5 +- configs/draco_defconfig | 5 +- configs/dreamplug_defconfig | 5 +- configs/ds414_defconfig | 7 +- configs/e2220-1170_defconfig | 5 +- configs/ea20_defconfig | 5 +- configs/ethernut5_defconfig | 5 +- configs/galileo_defconfig | 9 +- configs/gose_defconfig | 7 +- configs/gplugd_defconfig | 7 +- configs/inetspace_v2_defconfig | 5 +- configs/ip04_defconfig | 7 +- configs/jetson-tk1_defconfig | 5 +- configs/k2e_evm_defconfig | 5 +- configs/k2g_evm_defconfig | 5 +- configs/k2hk_evm_defconfig | 5 +- configs/k2l_evm_defconfig | 5 +- configs/km_kirkwood_128m16_defconfig | 5 +- configs/km_kirkwood_defconfig | 5 +- configs/km_kirkwood_pci_defconfig | 5 +- configs/kmcoge4_defconfig | 7 +- configs/kmcoge5un_defconfig | 5 +- configs/kmlion1_defconfig | 7 +- configs/kmnusa_defconfig | 5 +- configs/kmsugp1_defconfig | 5 +- configs/kmsuv31_defconfig | 5 +- configs/koelsch_defconfig | 7 +- configs/lager_defconfig | 7 +- configs/ls1021aqds_qspi_defconfig | 7 +- configs/ls1021atwr_qspi_defconfig | 8 +- configs/ls1021atwr_sdcard_qspi_defconfig | 7 +- configs/ls1043aqds_defconfig | 3 +- configs/ls1043aqds_lpuart_defconfig | 3 +- configs/ls1043aqds_nand_defconfig | 3 +- configs/ls1043aqds_nor_ddr3_defconfig | 3 +- configs/ls1043aqds_qspi_defconfig | 3 +- configs/ls1043aqds_sdcard_ifc_defconfig | 3 +- configs/ls1043aqds_sdcard_qspi_defconfig | 3 +- configs/ls1043ardb_SECURE_BOOT_defconfig | 3 +- configs/ls1043ardb_defconfig | 3 +- configs/ls1043ardb_nand_defconfig | 3 +- configs/ls1043ardb_sdcard_defconfig | 3 +- configs/ls2080aqds_defconfig | 2 +- configs/ls2080ardb_defconfig | 2 +- configs/ls2085aqds_defconfig | 2 +- configs/ls2085ardb_defconfig | 2 +- configs/lschlv2_defconfig | 5 +- configs/lsxhl_defconfig | 5 +- configs/m28evk_defconfig | 5 +- configs/marsboard_defconfig | 5 +- configs/maxbcm_defconfig | 11 +- configs/mgcoge3un_defconfig | 5 +- configs/minnowmax_defconfig | 11 +- configs/mx28evk_auart_console_defconfig | 5 +- configs/mx28evk_defconfig | 5 +- configs/mx28evk_nand_defconfig | 5 +- configs/mx28evk_spi_defconfig | 5 +- configs/mx6dlsabreauto_defconfig | 5 +- configs/mx6dlsabresd_defconfig | 5 +- configs/mx6qpsabreauto_defconfig | 5 +- configs/mx6qsabreauto_defconfig | 5 +- configs/mx6qsabrelite_defconfig | 5 +- configs/mx6qsabresd_defconfig | 5 +- configs/mx6sabresd_spl_defconfig | 5 +- configs/mx6slevk_defconfig | 5 +- configs/mx6slevk_spinor_defconfig | 5 +- configs/mx6slevk_spl_defconfig | 5 +- configs/mx6sxsabreauto_defconfig | 7 +- configs/mx6sxsabresd_defconfig | 5 +- configs/mx6sxsabresd_spl_defconfig | 3 +- configs/net2big_v2_defconfig | 5 +- configs/netspace_lite_v2_defconfig | 5 +- configs/netspace_max_v2_defconfig | 5 +- configs/netspace_mini_v2_defconfig | 5 +- configs/netspace_v2_defconfig | 5 +- configs/nitrogen6dl2g_defconfig | 5 +- configs/nitrogen6dl_defconfig | 5 +- configs/nitrogen6q2g_defconfig | 5 +- configs/nitrogen6q_defconfig | 5 +- configs/nitrogen6s1g_defconfig | 5 +- configs/nitrogen6s_defconfig | 5 +- configs/nyan-big_defconfig | 5 +- configs/omapl138_lcdk_defconfig | 7 +- configs/ot1200_defconfig | 11 +- configs/ot1200_spl_defconfig | 11 +- configs/p2371-0000_defconfig | 5 +- configs/p2371-2180_defconfig | 5 +- configs/p2571_defconfig | 5 +- configs/pcm051_rev1_defconfig | 5 +- configs/pcm051_rev3_defconfig | 5 +- configs/peach-pi_defconfig | 7 +- configs/peach-pit_defconfig | 7 +- configs/porter_defconfig | 7 +- configs/portl2_defconfig | 5 +- configs/pr1_defconfig | 5 +- configs/pxm2_defconfig | 5 +- configs/qemu-x86_defconfig | 9 +- configs/rastaban_defconfig | 5 +- configs/riotboard_defconfig | 5 +- configs/rut_defconfig | 5 +- configs/sama5d2_xplained_mmc_defconfig | 3 +- configs/sama5d2_xplained_spiflash_defconfig | 3 +- configs/sama5d3xek_mmc_defconfig | 5 +- configs/sama5d3xek_nandflash_defconfig | 5 +- configs/sama5d3xek_spiflash_defconfig | 5 +- configs/sama5d4_xplained_mmc_defconfig | 5 +- configs/sama5d4_xplained_nandflash_defconfig | 5 +- configs/sama5d4_xplained_spiflash_defconfig | 5 +- configs/sama5d4ek_mmc_defconfig | 5 +- configs/sama5d4ek_nandflash_defconfig | 5 +- configs/sama5d4ek_spiflash_defconfig | 5 +- configs/sandbox_defconfig | 19 +- configs/sh7752evb_defconfig | 7 +- configs/sh7753evb_defconfig | 7 +- configs/sh7757lcr_defconfig | 5 +- configs/silk_defconfig | 7 +- configs/smdk5250_defconfig | 7 +- configs/smdk5420_defconfig | 7 +- configs/snow_defconfig | 7 +- configs/socfpga_arria5_defconfig | 9 +- configs/socfpga_cyclone5_defconfig | 9 +- configs/socfpga_sockit_defconfig | 9 +- configs/socfpga_socrates_defconfig | 7 +- configs/socfpga_sr1500_defconfig | 5 +- configs/spring_defconfig | 7 +- configs/stout_defconfig | 7 +- configs/stv0991_defconfig | 4 +- configs/taurus_defconfig | 5 +- configs/tec-ng_defconfig | 5 +- configs/theadorable_debug_defconfig | 7 +- configs/theadorable_defconfig | 7 +- configs/thuban_defconfig | 5 +- configs/tqma6q_mba6_mmc_defconfig | 5 +- configs/tqma6q_mba6_spi_defconfig | 5 +- configs/tqma6s_mba6_mmc_defconfig | 5 +- configs/tqma6s_mba6_spi_defconfig | 5 +- configs/trimslice_defconfig | 5 +- configs/tseries_spi_defconfig | 5 +- configs/venice2_defconfig | 5 +- configs/vf610twr_defconfig | 3 +- configs/vf610twr_nand_defconfig | 3 +- configs/zynq_microzed_defconfig | 9 +- configs/zynq_zc702_defconfig | 11 +- configs/zynq_zc706_defconfig | 11 +- configs/zynq_zc770_xm010_defconfig | 13 +- configs/zynq_zc770_xm013_defconfig | 5 +- configs/zynq_zed_defconfig | 11 +- configs/zynq_zybo_defconfig | 5 +- doc/SPI/README.ti_qspi_dra_test | 2 +- doc/device-tree-bindings/mtd/jedec,spi-nor.txt | 78 ++ doc/mtd/spi-nor.txt | 81 ++ drivers/Makefile | 2 +- drivers/dfu/dfu_sf.c | 12 +- drivers/mtd/Kconfig | 2 +- drivers/mtd/spi-nor/Kconfig | 125 +++ drivers/mtd/spi-nor/Makefile | 20 + drivers/mtd/{spi => spi-nor}/fsl_espi_spl.c | 6 +- drivers/mtd/spi-nor/m25p80.c | 332 ++++++ .../sf_dataflash.c => spi-nor/mtd_dataflash.c} | 429 ++++--- drivers/mtd/{spi => spi-nor}/sandbox.c | 51 +- drivers/mtd/spi-nor/spi-nor-ids.c | 283 +++++ drivers/mtd/spi-nor/spi-nor-probe.c | 52 + drivers/mtd/spi-nor/spi-nor.c | 1141 +++++++++++++++++++ drivers/mtd/{spi => spi-nor}/spi_spl_load.c | 7 +- drivers/mtd/spi/Kconfig | 131 --- drivers/mtd/spi/Makefile | 18 - drivers/mtd/spi/sf-uclass.c | 103 -- drivers/mtd/spi/sf.c | 58 - drivers/mtd/spi/sf_internal.h | 243 ---- drivers/mtd/spi/sf_mtd.c | 104 -- drivers/mtd/spi/sf_params.c | 146 --- drivers/mtd/spi/sf_probe.c | 181 --- drivers/mtd/spi/spi_flash.c | 1185 -------------------- drivers/net/fm/fm.c | 2 +- drivers/net/phy/cortina.c | 2 +- drivers/spi/fsl_qspi.c | 18 +- drivers/spi/ich.c | 6 +- drivers/spi/spi-uclass.c | 35 +- drivers/spi/spi.c | 24 + drivers/spi/ti_qspi.c | 6 +- examples/standalone/Makefile | 2 +- include/configs/MPC8536DS.h | 2 +- include/configs/P1010RDB.h | 3 +- include/configs/P1022DS.h | 3 +- include/configs/T102xQDS.h | 5 +- include/configs/T102xRDB.h | 5 +- include/configs/T104xRDB.h | 5 +- include/configs/T208xQDS.h | 7 +- include/configs/T208xRDB.h | 7 +- include/configs/UCP1020.h | 4 +- include/configs/am335x_evm.h | 3 +- include/configs/am43xx_evm.h | 2 +- include/configs/aristainetos-common.h | 1 - include/configs/at91sam9n12ek.h | 3 +- include/configs/at91sam9x5ek.h | 3 +- include/configs/bav335x.h | 3 +- include/configs/bfin_adi_common.h | 2 +- include/configs/cgtqmx6eval.h | 10 +- include/configs/chromebook_jerry.h | 5 +- include/configs/clearfog.h | 5 +- include/configs/cm_fx6.h | 3 +- include/configs/cm_t43.h | 9 +- include/configs/da850evm.h | 6 +- include/configs/db-88f6820-gp.h | 3 +- include/configs/db-mv784mp-gp.h | 3 +- include/configs/dra7xx_evm.h | 5 +- include/configs/dreamplug.h | 2 +- include/configs/ds414.h | 3 +- include/configs/exynos5-common.h | 2 +- include/configs/gw_ventana.h | 13 +- include/configs/km/kmp204x-common.h | 2 +- include/configs/ls1021aqds.h | 2 - include/configs/ls1021atwr.h | 1 - include/configs/ls1043a_common.h | 8 +- include/configs/ls1043aqds.h | 2 +- include/configs/ls2080aqds.h | 3 +- include/configs/ls2080ardb.h | 5 +- include/configs/lsxl.h | 2 +- include/configs/maxbcm.h | 3 +- include/configs/mx6ul_14x14_evk.h | 7 +- include/configs/mx7dsabresd.h | 7 +- include/configs/omapl138_lcdk.h | 3 +- include/configs/ot1200.h | 3 +- include/configs/p1_p2_rdb_pc.h | 5 +- include/configs/pcm051.h | 3 +- include/configs/pcm052.h | 3 +- include/configs/rk3036_common.h | 4 +- include/configs/rk3288_common.h | 2 +- include/configs/sama5d2_xplained.h | 5 +- include/configs/sama5d3xek.h | 3 +- include/configs/sama5d4_xplained.h | 3 +- include/configs/sama5d4ek.h | 3 +- include/configs/siemens-am33x-common.h | 3 +- include/configs/socfpga_common.h | 8 +- include/configs/taurus.h | 3 +- include/configs/tegra-common-usb-gadget.h | 2 +- include/configs/theadorable.h | 3 +- include/configs/ti_armv7_keystone2.h | 3 +- include/configs/tseries.h | 3 +- include/configs/zynq-common.h | 6 +- include/dm/uclass-id.h | 1 - include/linux/err.h | 5 + include/linux/mtd/spi-nor.h | 253 +++++ include/spi.h | 33 +- include/spi_flash.h | 233 +--- 566 files changed, 4437 insertions(+), 3863 deletions(-) create mode 100644 doc/device-tree-bindings/mtd/jedec,spi-nor.txt create mode 100644 doc/mtd/spi-nor.txt create mode 100644 drivers/mtd/spi-nor/Kconfig create mode 100644 drivers/mtd/spi-nor/Makefile rename drivers/mtd/{spi => spi-nor}/fsl_espi_spl.c (97%) create mode 100644 drivers/mtd/spi-nor/m25p80.c rename drivers/mtd/{spi/sf_dataflash.c => spi-nor/mtd_dataflash.c} (61%) rename drivers/mtd/{spi => spi-nor}/sandbox.c (95%) create mode 100644 drivers/mtd/spi-nor/spi-nor-ids.c create mode 100644 drivers/mtd/spi-nor/spi-nor-probe.c create mode 100644 drivers/mtd/spi-nor/spi-nor.c rename drivers/mtd/{spi => spi-nor}/spi_spl_load.c (94%) delete mode 100644 drivers/mtd/spi/Kconfig delete mode 100644 drivers/mtd/spi/Makefile delete mode 100644 drivers/mtd/spi/sf-uclass.c delete mode 100644 drivers/mtd/spi/sf.c delete mode 100644 drivers/mtd/spi/sf_internal.h delete mode 100644 drivers/mtd/spi/sf_mtd.c delete mode 100644 drivers/mtd/spi/sf_params.c delete mode 100644 drivers/mtd/spi/sf_probe.c delete mode 100644 drivers/mtd/spi/spi_flash.c create mode 100644 include/linux/mtd/spi-nor.h -- 1.9.1

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[U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support on Minnowmax
by Saket Sinha 21 Mar '16

21 Mar '16

This series adds ACPI table support on Minnowmax. Saket Sinha (2): x86: Add ACPI table support to Minnowmax x86: Add DSDT table for supporting ACPI on Minnowmax board/intel/minnowmax/Makefile | 1 + board/intel/minnowmax/acpi.c | 234 +++++++++++++++++++++++ board/intel/minnowmax/acpi/cpu.asl | 65 +++++++ board/intel/minnowmax/acpi/device_nvs.asl | 75 ++++++++ board/intel/minnowmax/acpi/globalnvs.asl | 88 +++++++++ board/intel/minnowmax/acpi/mainboard.asl | 13 ++ board/intel/minnowmax/acpi/platform.asl | 62 ++++++ board/intel/minnowmax/acpi/sleepstates.asl | 14 ++ board/intel/minnowmax/acpi/southcluster.asl | 286 ++++++++++++++++++++++++++++ board/intel/minnowmax/dsdt.asl | 46 +++++ 10 files changed, 884 insertions(+) create mode 100644 board/intel/minnowmax/acpi.c create mode 100644 board/intel/minnowmax/acpi/cpu.asl create mode 100644 board/intel/minnowmax/acpi/device_nvs.asl create mode 100644 board/intel/minnowmax/acpi/globalnvs.asl create mode 100644 board/intel/minnowmax/acpi/mainboard.asl create mode 100644 board/intel/minnowmax/acpi/platform.asl create mode 100644 board/intel/minnowmax/acpi/sleepstates.asl create mode 100644 board/intel/minnowmax/acpi/southcluster.asl create mode 100644 board/intel/minnowmax/dsdt.asl -- 2.1.4

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[U-Boot] [PATCH] sunxi: Support SID e-fuses on A83T and H3
by Chen-Yu Tsai 20 Mar '16

20 Mar '16

On the A83T and H3, the SID block is at a different address. Furthurmore, the e-fuses are at an offset of 0x200 within the hardware's address space. Signed-off-by: Chen-Yu Tsai <wens(a)csie.org> --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 0cdefdc..f797649 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -74,7 +74,14 @@ #define SUNXI_AD_DA_BASE 0x01c22c00 #define SUNXI_KEYPAD_BASE 0x01c23000 #define SUNXI_TZPC_BASE 0x01c23400 + +#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3) +/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */ +#define SUNXI_SID_BASE 0x01c14200 +#else #define SUNXI_SID_BASE 0x01c23800 +#endif + #define SUNXI_SJTAG_BASE 0x01c23c00 #define SUNXI_TP_BASE 0x01c25000 -- 2.7.0

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[U-Boot] [PATCH v4 00/14] Add Support for Secure Boot on LS208x
by Saksham Jain 18 Mar '16

18 Mar '16

Secure Boot ESBC has been enabled on FSL LS208x platforms. Changes for v2: - changed function fsl_secboot_validate to return address of image - corrected Bootscript header for ls1043 and ls1021 Changes for v3: - minor changes to remove compilation warnings Changes ofr v4: - removed IE Key extenstion support. Methodology not fixed yet. - minor changes in commit messages (clean up) Saksham Jain (14): armv8: ls2080: Add SFP Configs for LS2080/LS2085 armv8: ls2080: Add Secure Boot configs: SEC, Security Monitor, SRK and RCW SECURE BOOT: Add new ESBC header for ls-ch3 Secure Boot SECURE BOOT: Add Secure Boot support on ls2080aqds/rdb armv8: fsl-lsch3: Add bootscript header address for Secure Boot SECURE BOOT: Copy Bootscript and header from NOR to DDR for LS2080/5 SECURE BOOT: Change env variable "fdt_high" for LS2080a and LS2085a armv8 : ls2080: Add config for endianess of CCSR GUR armv8: fsl-lsch3: Disable SMMU during Secure Boot crypto/fsl: Correct 64bit Write when MMU disabled crypto/fsl: Make CAAM transactions cacheable SECURE_BOOT: Use default bootargs during Secure Boot SECURE BOOT: Halt execution when secure boot fail after reset request SECURE BOOT: Change fsl_secboot_validate function to output image addr arch/arm/cpu/armv8/fsl-layerscape/soc.c | 18 +++++- arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 28 +++++++++ arch/arm/include/asm/fsl_secure_boot.h | 50 ++++++++++++++-- board/freescale/common/cmd_esbc_validate.c | 14 ++++- board/freescale/common/fsl_validate.c | 66 +++++++++++++++------ board/freescale/ls2080aqds/ls2080aqds.c | 5 +- board/freescale/ls2080ardb/ls2080ardb.c | 5 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 15 +++++ configs/ls2080ardb_SECURE_BOOT_defconfig | 15 +++++ configs/ls2085aqds_SECURE_BOOT_defconfig | 15 +++++ configs/ls2085ardb_SECURE_BOOT_defconfig | 15 +++++ drivers/crypto/fsl/desc_constr.h | 7 +-- drivers/crypto/fsl/jr.c | 13 +++++ drivers/crypto/fsl/jr.h | 3 + include/config_fsl_chain_trust.h | 25 +++++--- include/configs/ls2080aqds.h | 2 + include/configs/ls2080ardb.h | 2 + include/fsl_secboot_err.h | 3 + include/fsl_sfp.h | 3 +- include/fsl_validate.h | 67 ++++++++++++++++++---- 21 files changed, 341 insertions(+), 48 deletions(-) create mode 100644 configs/ls2080aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2080ardb_SECURE_BOOT_defconfig create mode 100644 configs/ls2085aqds_SECURE_BOOT_defconfig create mode 100644 configs/ls2085ardb_SECURE_BOOT_defconfig -- 1.8.1.4

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