February 2016 - U-Boot

[U-Boot] [PATCH 0/2] board: atmel: add SAMA5D2 PTC Engineering board
by Wenyou Yang 03 May '16

03 May '16

This board supports booting from NAND Flash and spi Flash. Wenyou Yang (2): ARM: at91: sama5d2: add macro & field definitions board: atmel: add SAMA5D2 PTC Engineering board arch/arm/mach-at91/Kconfig | 6 + arch/arm/mach-at91/include/mach/sama5_sfr.h | 24 +++ arch/arm/mach-at91/include/mach/sama5d2.h | 5 + board/atmel/sama5d2_ptc/Kconfig | 15 ++ board/atmel/sama5d2_ptc/MAINTAINERS | 7 + board/atmel/sama5d2_ptc/Makefile | 8 + board/atmel/sama5d2_ptc/sama5d2_ptc.c | 285 +++++++++++++++++++++++++++ configs/sama5d2_ptc_nandflash_defconfig | 12 ++ configs/sama5d2_ptc_spiflash_defconfig | 12 ++ include/configs/sama5d2_ptc.h | 155 +++++++++++++++ 10 files changed, 529 insertions(+) create mode 100644 board/atmel/sama5d2_ptc/Kconfig create mode 100644 board/atmel/sama5d2_ptc/MAINTAINERS create mode 100644 board/atmel/sama5d2_ptc/Makefile create mode 100644 board/atmel/sama5d2_ptc/sama5d2_ptc.c create mode 100644 configs/sama5d2_ptc_nandflash_defconfig create mode 100644 configs/sama5d2_ptc_spiflash_defconfig create mode 100644 include/configs/sama5d2_ptc.h -- 1.7.9.5

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[U-Boot] [PATCH] spl_mmc: allow to load raw image
by Masahiro Yamada 02 May '16

02 May '16

The function spl_parse_image_header() falls back to a raw image if the U-Boot header is missing and CONFIG_SPL_PANIC_ON_RAW_IMAGE is undefined. While, the bad magic checking here makes the spl_parse_image_header() unreachable in case of the missing header. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- common/spl/spl_mmc.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index c27a250..df406e3 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -33,11 +33,6 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) if (count == 0) goto end; - if (image_get_magic(header) != IH_MAGIC) { - puts("bad magic\n"); - return -1; - } - spl_parse_image_header(header); /* convert size to sectors - round up */ -- 1.9.1

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[U-Boot] [PATCH v2 00/27] spl: Support loading a FIT image containing U-Boot
by Simon Glass 02 May '16

02 May '16

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[U-Boot] [PATCH 0/8] net: Split out the Ethernet uclass into its own file
by Simon Glass 01 May '16

01 May '16

Every other uclass is in its own file. It makes sense to put the Ethernet uclass code into its own file too. The result is less code in each file, and it becomes easier to see which code is related to driver model. This series creates a new common file to hold the common code, moves the driver-model into its own file and tidies up. Some boards use PCI to obtain Ethernet. With driver model, unless this is mentioned in the device tree, the Ethernet device will not be present on initial startup. So we need to probe PCI just in case there is a device there. Simon Glass (8): tegra: Report errors from PCI init net: Don't call board/cpu_eth_init() with driver model net: Move common init into a new eth_common.c file net: Move environment functions to the common file net: Move remaining common functions to eth_common.c net: Move driver-model code into its own file net: Rename eth.c to eth_lecacy.c net: Probe PCI before looking for ethernet devices drivers/pci/pci_tegra.c | 6 +- net/Makefile | 7 +- net/{eth.c => eth-uclass.c} | 601 +------------------------------------------- net/eth_common.c | 166 ++++++++++++ net/eth_internal.h | 40 +++ net/eth_legacy.c | 439 ++++++++++++++++++++++++++++++++ 6 files changed, 664 insertions(+), 595 deletions(-) rename net/{eth.c => eth-uclass.c} (50%) create mode 100644 net/eth_common.c create mode 100644 net/eth_internal.h create mode 100644 net/eth_legacy.c -- 2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH] net: Add mv88e60xx support to the mv88e61xx driver
by Joshua Scott 26 Apr '16

26 Apr '16

The Marvell Link Street mv88e60xx is a series of FastEthernet switch chips, some of which also support Gigabit ports. It is similar to the mv88e61xx series which support Gigabit on all ports. There is already a driver for the mv88e61xx in U-Boot, and this patch updates it to also work with the mv88e60xx. The main change that was required was the size of the port bitmaps. Previously, 8-bit port bitmaps were in use, as the driver had only been used with six-port mv88e61xx devices. This has been changed so that 16-bit port bitmaps are now used, which covers the largest port-counts available for the mv88e60xx / mv88e61xx. Reviewed-by: Chris Packham <chris.packham(a)alliedtelesis.co.nz> Signed-off-by: Joshua Scott <joshua.scott(a)alliedtelesis.co.nz> --- drivers/net/phy/mv88e61xx.c | 29 +++++++++++++++++++++-------- drivers/net/phy/mv88e61xx.h | 2 -- include/netdev.h | 20 +++++++++++++++----- 3 files changed, 36 insertions(+), 15 deletions(-) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 302abe8..79204f3 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -215,17 +215,17 @@ static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig) u32 port_mask = swconfig->ports_enabled; /* apply internal vlan config */ - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + for (prt = 0; prt < swconfig->numports; prt++) { /* only for enabled ports */ if ((1 << prt) & port_mask) { /* take vlan map from swconfig */ - u8 vlanmap = swconfig->vlancfg[prt]; + u16 vlanmap = swconfig->vlancfg[prt]; /* remove disabled ports from vlan map */ vlanmap &= swconfig->ports_enabled; /* apply vlan map to port */ RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_VMAP_REG, &reg); - reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1); + reg &= ~((1 << swconfig->numports) - 1); reg |= vlanmap; WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_VMAP_REG, reg); @@ -331,32 +331,44 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) return -1; } - if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) { + if (!(swconfig->cpuport & ((1 << 4) | (1 << 5) | (1 << 10)))) { swconfig->cpuport = (1 << 5); printf("Invalid cpu port config, using default port5\n"); } RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, &reg); switch (reg &= 0xfff0) { + case 0x0980: + idstr = "88E6096"; + swconfig->numports = 0x0b; + break; + case 0x0990: + idstr = "88E6097"; + swconfig->numports = 0x0b; + break; case 0x1610: idstr = "88E6161"; + swconfig->numports = 0x06; break; case 0x1650: idstr = "88E6165"; + swconfig->numports = 0x06; break; case 0x1210: idstr = "88E6123"; + swconfig->numports = 0x06; /* ports 2,3,4 not available */ swconfig->ports_enabled &= 0x023; break; default: /* Could not detect switch id */ idstr = "88E61??"; + swconfig->numports = 0x06; break; } /* be sure all ports are disabled */ - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + for (prt = 0; prt < swconfig->numports; prt++) { RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, &reg); reg &= ~0x3; WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg); @@ -405,12 +417,13 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e); } - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + for (prt = 0; prt < swconfig->numports; prt++) { /* configure port's PHY */ if (!((1 << prt) & swconfig->cpuport)) { - /* port 4 has phy 6, not 4 */ - int phy = (prt == 4) ? 6 : prt; + /* 88e61xx: port 4 has phy 6, not 4 */ + int phy = (swconfig->numports == 6 && + prt == 4) ? 6 : prt; if (mv88361xx_powerup(swconfig, phy)) return -1; if (mv88361xx_reverse_mdipn(swconfig, phy)) diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h index 9c62e4a..b289f21 100644 --- a/drivers/net/phy/mv88e61xx.h +++ b/drivers/net/phy/mv88e61xx.h @@ -11,8 +11,6 @@ #include <miiphy.h> -#define MV88E61XX_CPU_PORT 0x5 - #define MV88E61XX_PHY_TIMEOUT 100000 /* port dev-addr (= port + 0x10) */ diff --git a/include/netdev.h b/include/netdev.h index 34651ab..cbd0420 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -154,7 +154,9 @@ static inline int pci_eth_init(bd_t *bis) #if defined(CONFIG_MV88E61XX_SWITCH) /* constants for any 88E61xx switch */ -#define MV88E61XX_MAX_PORTS_NUM 6 +/* Allow enough space in the struct to fit 11 ports, as this is + * the number used in the mv88e60xx */ +#define MV88E61XX_MAX_PORTS_NUM 0x0b enum mv88e61xx_cfg_mdip { MV88E61XX_MDIP_NOCHANGE, @@ -180,13 +182,14 @@ enum mv88e61xx_cfg_prtstt { struct mv88e61xx_config { char *name; - u8 vlancfg[MV88E61XX_MAX_PORTS_NUM]; + u16 vlancfg[MV88E61XX_MAX_PORTS_NUM]; enum mv88e61xx_cfg_rgmiid rgmii_delay; enum mv88e61xx_cfg_prtstt portstate; enum mv88e61xx_cfg_ledinit led_init; enum mv88e61xx_cfg_mdip mdip; + u32 numports; u32 ports_enabled; - u8 cpuport; + u32 cpuport; }; /* @@ -196,10 +199,17 @@ struct mv88e61xx_config { */ /* Switch mode : routes any port to any port */ -#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F } +#define MV88E61XX_VLANCFG_SWITCH { 0x003F, 0x003F, 0x003F, 0x003F, 0x003F, \ + 0x003F, 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000 } /* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */ -#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F } +#define MV88E61XX_VLANCFG_ROUTER { 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, \ + 0x001F, 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000 } +#define MV88E60XX_VLANCFG_ROUTER { 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, \ + 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, \ + 0x03ff } int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); #endif /* CONFIG_MV88E61XX_SWITCH */ -- 1.9.1

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[U-Boot] [PATCH 1/3] phy: Add phy driver support for xilinx PCS/PMA core
by Michal Simek 26 Apr '16

26 Apr '16

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Add phy driver support for xilinx PCS/PMA core Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/phy/Makefile | 1 + drivers/net/phy/phy.c | 3 + drivers/net/phy/xilinx_phy.c | 144 +++++++++++++++++++++++++++++++++++++++++++ include/phy.h | 1 + 4 files changed, 149 insertions(+) create mode 100644 drivers/net/phy/xilinx_phy.c diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 9e4d4927e676..1e299b97b961 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -25,4 +25,5 @@ obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o obj-$(CONFIG_PHY_TI) += ti.o +obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 17866a244b3a..23c82bb36e93 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -503,6 +503,9 @@ int phy_init(void) #ifdef CONFIG_PHY_VITESSE phy_vitesse_init(); #endif +#ifdef CONFIG_PHY_XILINX + phy_xilinx_init(); +#endif return 0; } diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c new file mode 100644 index 000000000000..f3eaf2e97ced --- /dev/null +++ b/drivers/net/phy/xilinx_phy.c @@ -0,0 +1,144 @@ +/* + * Xilinx PCS/PMA Core phy driver + * + * Copyright (C) 2015 - 2016 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <phy.h> +#include <dm.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MII_PHY_STATUS_SPD_MASK 0x0C00 +#define MII_PHY_STATUS_FULLDUPLEX 0x1000 +#define MII_PHY_STATUS_1000 0x0800 +#define MII_PHY_STATUS_100 0x0400 +#define XPCSPMA_PHY_CTRL_ISOLATE_DISABLE 0xFBFF + +/* Mask used for ID comparisons */ +#define XILINX_PHY_ID_MASK 0xfffffff0 + +/* Known PHY IDs */ +#define XILINX_PHY_ID 0x01740c00 + +/* struct phy_device dev_flags definitions */ +#define XAE_PHY_TYPE_MII 0 +#define XAE_PHY_TYPE_GMII 1 +#define XAE_PHY_TYPE_RGMII_1_3 2 +#define XAE_PHY_TYPE_RGMII_2_0 3 +#define XAE_PHY_TYPE_SGMII 4 +#define XAE_PHY_TYPE_1000BASE_X 5 + +static int xilinxphy_startup(struct phy_device *phydev) +{ + int err; + int status = 0; + + debug("%s\n", __func__); + /* Update the link, but return if there + * was an error + */ + err = genphy_update_link(phydev); + if (err) + return err; + + if (AUTONEG_ENABLE == phydev->autoneg) { + status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); + status = status & MII_PHY_STATUS_SPD_MASK; + + if (status & MII_PHY_STATUS_FULLDUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + switch (status) { + case MII_PHY_STATUS_1000: + phydev->speed = SPEED_1000; + break; + + case MII_PHY_STATUS_100: + phydev->speed = SPEED_100; + break; + + default: + phydev->speed = SPEED_10; + break; + } + } else { + int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + + if (bmcr < 0) + return bmcr; + + if (bmcr & BMCR_FULLDPLX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + if (bmcr & BMCR_SPEED1000) + phydev->speed = SPEED_1000; + else if (bmcr & BMCR_SPEED100) + phydev->speed = SPEED_100; + else + phydev->speed = SPEED_10; + } + + /* + * For 1000BASE-X Phy Mode the speed/duplex will always be + * 1000Mbps/fullduplex + */ + if (phydev->flags == XAE_PHY_TYPE_1000BASE_X) { + phydev->duplex = DUPLEX_FULL; + phydev->speed = SPEED_1000; + } + + return 0; +} + +static int xilinxphy_of_init(struct phy_device *phydev) +{ + struct udevice *dev = (struct udevice *)&phydev->dev; + u32 phytype; + + debug("%s\n", __func__); + phytype = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "phy-type", -1); + if (phytype == XAE_PHY_TYPE_1000BASE_X) + phydev->flags |= XAE_PHY_TYPE_1000BASE_X; + + return 0; +} + +static int xilinxphy_config(struct phy_device *phydev) +{ + int temp; + + debug("%s\n", __func__); + xilinxphy_of_init(phydev); + temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + temp &= XPCSPMA_PHY_CTRL_ISOLATE_DISABLE; + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp); + + return 0; +} + +static struct phy_driver xilinxphy_driver = { + .uid = XILINX_PHY_ID, + .mask = XILINX_PHY_ID_MASK, + .name = "Xilinx PCS/PMA PHY", + .features = PHY_GBIT_FEATURES, + .config = &xilinxphy_config, + .startup = &xilinxphy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_xilinx_init(void) +{ + debug("%s\n", __func__); + phy_register(&xilinxphy_driver); + + return 0; +} diff --git a/include/phy.h b/include/phy.h index 09bbe483a4b1..21459a8c8093 100644 --- a/include/phy.h +++ b/include/phy.h @@ -264,6 +264,7 @@ int phy_smsc_init(void); int phy_teranetics_init(void); int phy_ti_init(void); int phy_vitesse_init(void); +int phy_xilinx_init(void); int board_phy_config(struct phy_device *phydev); int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); -- 1.9.1

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[U-Boot] [PATCH] mtd, ubi: set free_count to zero before walking through erase list
by Heiko Schocher 25 Apr '16

25 Apr '16

Set free_count to zero before walking through ai->erase list in wl_init(). As U-Boot has no workqueue/threads, it immediately calls erase_worker(), which increase for each erased block free_count. Without this patch, free_count gets after this initialized to zero in wl_init(), so the free_count variable always has the maybe wrong value 0. Detected this behaviour on the dxr2 board, where the UBI fastmap gets not written when attaching/dettaching on an empty NAND. It drops instead the error message: could not find any anchor PEB With this patch, fastmap gets written on dettach. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- added Richard to this EMail, as maybe this could be a problem in linux too ... ? drivers/mtd/ubi/wl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index 507b091..e823ca5 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -1528,6 +1528,7 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai) INIT_LIST_HEAD(&ubi->pq[i]); ubi->pq_head = 0; + ubi->free_count = 0; list_for_each_entry_safe(aeb, tmp, &ai->erase, u.list) { cond_resched(); @@ -1546,7 +1547,6 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai) found_pebs++; } - ubi->free_count = 0; list_for_each_entry(aeb, &ai->free, u.list) { cond_resched(); -- 2.5.0

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[U-Boot] [PATCH v2 1/2] m68k: add malloc memory for early malloc
by Angelo Dureghello 23 Apr '16

23 Apr '16

To use serial uclass and DM, CONFIG_SYS_MALLOC_F must be used. So CONFIG_SYS_GENERIC_GLOBAL_DATA has been undefined and call to board_init_f_mem() is added for all cpu's. Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- Changes in v2: None arch/m68k/cpu/mcf5227x/start.S | 8 ++++++++ arch/m68k/cpu/mcf523x/start.S | 8 ++++++++ arch/m68k/cpu/mcf52x2/start.S | 8 ++++++++ arch/m68k/cpu/mcf530x/cpu_init.c | 2 +- arch/m68k/cpu/mcf530x/start.S | 8 ++++++++ arch/m68k/cpu/mcf532x/start.S | 8 ++++++++ arch/m68k/cpu/mcf5445x/start.S | 8 ++++++++ arch/m68k/cpu/mcf547x_8x/start.S | 8 ++++++++ arch/m68k/include/asm/config.h | 2 -- 9 files changed, 57 insertions(+), 3 deletions(-) diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S index 23024f9..bcb5611 100644 --- a/arch/m68k/cpu/mcf5227x/start.S +++ b/arch/m68k/cpu/mcf5227x/start.S @@ -379,6 +379,14 @@ _start: move.l #__got_start, %a5 /* put relocation table address to a5 */ + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S index 8a23e72..14b3025 100644 --- a/arch/m68k/cpu/mcf523x/start.S +++ b/arch/m68k/cpu/mcf523x/start.S @@ -141,6 +141,14 @@ _start: move.l #__got_start, %a5 /* put relocation table address to a5 */ + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index 8a59496..abb9291 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -198,6 +198,14 @@ _after_flashbar_copy: move.l #__got_start, %a5 /* put relocation table address to a5 */ + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c index 80dc239..b09eed8 100644 --- a/arch/m68k/cpu/mcf530x/cpu_init.c +++ b/arch/m68k/cpu/mcf530x/cpu_init.c @@ -142,7 +142,7 @@ int cpu_init_r(void) return 0; } -void uart_port_conf(void) +void uart_port_conf(int port) { } diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index 097958a..d9034e1 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -137,6 +137,14 @@ _start: /* put relocation table address to a5 */ move.l #__got_start, %a5 + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + /* run low-level CPU init code (from flash) */ bsr cpu_init_f diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index 3b9ede0..98a5401 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -155,6 +155,14 @@ _start: move.l #__got_start, %a5 /* put relocation table address to a5 */ + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index 979eb5a..340ab84 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -664,6 +664,14 @@ _start: move.l #__got_start, %a5 /* put relocation table address to a5 */ + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S index 75de22d..0468d1a 100644 --- a/arch/m68k/cpu/mcf547x_8x/start.S +++ b/arch/m68k/cpu/mcf547x_8x/start.S @@ -148,6 +148,14 @@ _start: move.l #__got_start, %a5 /* put relocation table address to a5 */ + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + jbsr cpu_init_f /* run low-level CPU init code (from flash) */ jbsr board_init_f /* run low-level board init code (from flash) */ diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h index e1458ac..9c4d3fb 100644 --- a/arch/m68k/include/asm/config.h +++ b/arch/m68k/include/asm/config.h @@ -7,8 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_GENERIC_GLOBAL_DATA - #define CONFIG_NEEDS_MANUAL_RELOC #define CONFIG_LMB -- 2.5.3

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[U-Boot] [PATCH] exynos: Set CNTFRQ
by Alexander Graf 14 Apr '16

14 Apr '16

Commit 73a1cb27 moved the check whether we should set the architected timer frequency from CONFIG_SYS_CLK_FREQ to CONFIG_TIMER_CLK_FREQ, but did not update all users of it. The one where I (finally) realized why KVM didn't work is the Arndale board, so this patch adds the respective define to it. Signed-off-by: Alexander Graf <agraf(a)suse.de> Fixes: 73a1cb27 --- include/configs/exynos-common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 852829c..c4e731f 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -31,6 +31,7 @@ /* input clock of PLL: 24MHz input clock */ #define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_TIMER_CLK_FREQ 24000000 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG -- 2.6.2

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[U-Boot] Newbie SPL question for socfpga_sockit
by George Broz 13 Apr '16

13 Apr '16

Hello, Sorry for the newbie question... I have an Altera/Terasic board (socfpga_sockit) that has issues recognizing USB storage devices (roughly 60% good / 40% bad): SOCFPGA_CYCLONE5 # usb start (Re)start USB... USB0: scanning bus 0 for devices... DW_USB: Transfer completion interrupt timeout Timed out waiting for channel to disable 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found The pre-made U-Boot SPL & image that come with the board have version: U-Boot 2013.01.01 (Aug 08 2014 - 10:46:23) (Old!) I need to rebuild U-Boot for this board to add md5sum and hopefully fix the USB issues. When I've rebuilt the u-boot.img from the 2013.01.01 branch of the (Altera maintained) source, U-boot boots, but the USB problems get worse (100% bad): USB0: Core Release: 2.93a dwc_otg_core_host_init: Unable to clear halt on channel 1 (timeout HCCHAR 0xC0000000 @ffb40520) dwc_otg_core_host_init: Unable to clear halt on channel 2 (timeout HCCHAR 0xC0000000 @ffb40540 (I've confirmed that CONFIG_CMD_USB and CONFIG_USB_STORAGE are defined and have tried turning on and off 'dcache' as suggested elsewhere to no avail). If I try a later release (e.g. v2016.01 which seems to support the Terasic board explicitly) the boot process stops just after loading the SPL. At this point I have only been changing the u-boot.img component, not the SPL (in the a2 partition of the MMC). The documentation from Altera about generating the SPL seems to require using Qsys/Quartus tools which I'd really like to avoid. I can produce u-boot-spl.bin / u-boot.img from make socfpga_sockit_defconfig; make all. My newbie question ... should be I able to use directly the u-boot-spl.bin generated by the build to replace the SPL on the board? (I'm hoping the USB issues resolve themselves when I'm able to get the later version of U-Boot running...) Thanks for any input... --George Broz Moog Industrial Group

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