August 2015 - U-Boot

[U-Boot] [PATCH 2/4] armv8: fsl-lsch3: Initiaze 4 MACs per QSGMII in dpmac_info
by Prabhakar Kushwaha 07 Aug '15

07 Aug '15

Every QSGMII SerDes Protocol usage 4 MACs. So add/repeat QSGMII information for 4 MACs in dpmac_info strucuture. Signed-off-by: King Chung Lo(a)freescale.com <KingChungLo(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c | 33 ++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c index 02ca126..ae08343 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c @@ -90,7 +90,38 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, else { serdes_prtcl_map[lane_prtcl] = 1; #ifdef CONFIG_FSL_MC_ENET - wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl); + switch (lane_prtcl) { + case QSGMII_A: + wriop_init_dpmac(sd, 5, (int)lane_prtcl); + wriop_init_dpmac(sd, 6, (int)lane_prtcl); + wriop_init_dpmac(sd, 7, (int)lane_prtcl); + wriop_init_dpmac(sd, 8, (int)lane_prtcl); + break; + case QSGMII_B: + wriop_init_dpmac(sd, 1, (int)lane_prtcl); + wriop_init_dpmac(sd, 2, (int)lane_prtcl); + wriop_init_dpmac(sd, 3, (int)lane_prtcl); + wriop_init_dpmac(sd, 4, (int)lane_prtcl); + break; + case QSGMII_C: + wriop_init_dpmac(sd, 13, (int)lane_prtcl); + wriop_init_dpmac(sd, 14, (int)lane_prtcl); + wriop_init_dpmac(sd, 15, (int)lane_prtcl); + wriop_init_dpmac(sd, 16, (int)lane_prtcl); + break; + case QSGMII_D: + wriop_init_dpmac(sd, 9, (int)lane_prtcl); + wriop_init_dpmac(sd, 10, (int)lane_prtcl); + wriop_init_dpmac(sd, 11, (int)lane_prtcl); + wriop_init_dpmac(sd, 12, (int)lane_prtcl); + break; + default: + if (lane_prtcl >= SGMII1 && + lane_prtcl <= SGMII16) + wriop_init_dpmac(sd, lane + 1, + (int)lane_prtcl); + break; + } #endif } } -- 1.9.1

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[U-Boot] [PATCH v1 1/2] cmd_sf: Add command "sf info" to show current device info
by Haikun Wang 07 Aug '15

07 Aug '15

Add command "sf info" to show the information of the current SPI flash device. Signed-off-by: Haikun Wang <haikun.wang(a)freescale.com> --- In current sf driver, we show the debug information during the flash probe period. In case of without DM SPI, we need to run command "sf probe" to get the debug information of the current SPI flash device. "sf probe" will re-identify the device every time and it reduce the efficiency. We can get the debug information without any re-identify process using "sf info". In case of using DM SPI, if we disable CONFIG_DM_DEVICE_REMOVE "sf probe" will only call the flash driver's probe function the first time you run it and no information will show after the first. It is recommended that only call the flash driver's probe function once during u-boot period. You can get the debug information using "sf info" in this case. Changes in v1: None. common/cmd_sf.c | 43 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 6aabf39..38841fa 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -503,6 +503,44 @@ static int do_spi_flash_test(int argc, char * const argv[]) } #endif /* CONFIG_CMD_SF_TEST */ +static int do_spi_flash_info(struct spi_flash *flash, bool dm_column_style) +{ + if (dm_column_style) { + struct udevice *bus; + struct udevice *dev; + struct dm_spi_slave_platdata *plat; + + dev = flash->dev; + bus = dev->parent; + plat = dev_get_parent_platdata(dev); + + printf("Device: %s\n", dev->name); + printf("Chipselect: %d\n", plat->cs); + printf("Bind Driver: %s\n", dev->driver->name); + printf("SPI bus: %s\n", bus->name); + printf("SPI bus number: %d\n", bus->seq); + printf("Flash type: %s\n", flash->name); + printf("Page size: "); + print_size(flash->page_size, "\n"); + printf("Erase size: "); + print_size(flash->erase_size, "\n"); + printf("Total size: "); + print_size(flash->size, "\n"); + if (flash->memory_map) + printf("Mapped at %p\n", flash->memory_map); + } else { + printf("SF: Detected %s with page size ", flash->name); + print_size(flash->page_size, ", erase size "); + print_size(flash->erase_size, ", total "); + print_size(flash->size, ""); + if (flash->memory_map) + printf(", mapped at %p", flash->memory_map); + puts("\n"); + } + + return 0; +} + static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -537,6 +575,8 @@ static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, else if (!strcmp(cmd, "test")) ret = do_spi_flash_test(argc, argv); #endif + else if (!strcmp(cmd, "info")) + ret = do_spi_flash_info(flash, IS_ENABLED(CONFIG_DM_SPI_FLASH)); else ret = -1; @@ -567,6 +607,7 @@ U_BOOT_CMD( "sf erase offset [+]len - erase `len' bytes from `offset'\n" " `+len' round up `len' to block size\n" "sf update addr offset len - erase and write `len' bytes from memory\n" - " at `addr' to flash at `offset'" + " at `addr' to flash at `offset'\n" + "sf info - display info of the current SPI Flash device\n" SF_TEST_HELP ); -- 2.1.0.27.g96db324

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[U-Boot] Wrong release date for v2015.10 on the denx.de
by Bin Meng 07 Aug '15

07 Aug '15

Hi Wolfgang, By checking http://www.denx.de/wiki/U-Boot/ReleaseCycle, it says: "Release "v2015.10" is scheduled in 66 days — on Aug 12, 2015." This Aug 12 date is wrong. Could you please fix it? Also I noticed that there is no statistics for v2015.07 release on this page. Is it coming? Regards, Bin

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[U-Boot] [PATCH] patman: Don't run patman when it is imported as a module
by Simon Glass 07 Aug '15

07 Aug '15

Commit 488d19c (patman: add distutils based installer) has the side effect of making patman run twice with each invocation. Fix this by checking for 'main program' invocation in patman.py. This is good practice in any case. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- tools/patman/patman.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tools/patman/patman.py b/tools/patman/patman.py index e76fc42..6fe8fe0 100755 --- a/tools/patman/patman.py +++ b/tools/patman/patman.py @@ -74,8 +74,11 @@ specified by tags you place in the commits. Use -n to do a dry run first.""" settings.Setup(parser, options.project, '') (options, args) = parser.parse_args() +if __name__ != "__main__": + pass + # Run our meagre tests -if options.test: +elif options.test: import doctest sys.argv = [sys.argv[0]] -- 2.5.0.rc2.392.g76e840b

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[U-Boot] [PATCH 00/15] x86: minnowmax: Add interrupt support
by Simon Glass 07 Aug '15

07 Aug '15

This series brings in interrupt support for Minnowmax, so that PCI interrupts are correctly set up for Linux. It also includes a few small improvements to the PCI driver model implementation and tidies up some nits in the code. The existing pirq routing code does not seem to support the Atom used in the Minnowmax. I'd like to figure that out before applying the RFC patch. Simon Glass (15): pci: Add a constant for an invalid interrupt pci: Indicate prefetchable memory allocate when debugging dm: Add a return value comment to device_get_child() dm: pci: Provide friendly config access functions dm: pci: Add a way to iterate through all PCI devices x86: Move Chrome OS options to defconfig x86: Move CONFIG_X86_SERIAL to Kconfig x86: Re-order efi-x86_defconfig x86: Drop CONFIG_DCACHE_RAM_MRC_VAR_SIZE from header file x86: dts: Fix typo in intel,irq-router.txt x86: Tidy up the PIRQ routing code a little x86: Split out fsp_init_phase_pci() code into a new function x86: minnowmax: Drop the old PCI settings RFC: x86: minnowmax: Add interrupt routing setup x86: Update README to explain booting Ubuntu on Minnowmax arch/x86/cpu/baytrail/valleyview.c | 492 +++++++++++++++++++++ arch/x86/cpu/irq.c | 40 +- arch/x86/dts/minnowmax.dts | 28 ++ arch/x86/include/asm/fsp/fsp_support.h | 7 + arch/x86/lib/fsp/fsp_common.c | 11 +- configs/chromebook_link_defconfig | 3 + configs/chromebox_panther_defconfig | 3 + configs/efi-x86_defconfig | 10 +- doc/README.x86 | 275 ++++++++++++ doc/device-tree-bindings/misc/intel,irq-router.txt | 4 +- drivers/pci/pci-uclass.c | 134 ++++++ drivers/pci/pci.c | 3 +- drivers/pci/pci_auto.c | 5 +- drivers/serial/Kconfig | 10 + include/configs/crownbay.h | 1 - include/configs/galileo.h | 2 - include/configs/minnowmax.h | 14 +- include/configs/qemu-x86.h | 2 - include/configs/x86-chromebook.h | 6 - include/dm/device.h | 2 + include/pci.h | 44 ++ 21 files changed, 1032 insertions(+), 64 deletions(-) -- 2.5.0.rc2.392.g76e840b

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[U-Boot] [PATCH v3 00/25] dm: Introduce Rockchip RK3288 support
by Simon Glass 07 Aug '15

07 Aug '15

The Rockchip RK3288 is based on a quad-core Cortex-A17 CPU and has a good set of peripherals. Various full-featured U-Boot ports are available and this is an attempt to bring those features into mainline. With this series the Firefly RK3288 can boot to a prompt from an SD card. Since much of the code is generic, this also supports the Radxa Rock Pro. Since there is no device tree available for that yet, it uses the same config and device tree as the Firefly. This works because not all peripherals are supported, so the differences don't matter. Support for booting from USB OTG is also provided, using the on-chip boot ROM and the rkflashtool utility. This can boot as far as SPL, but there is no support for reading U-Boot proper from USB as yet. This requires implementing a suitable protocol (perhaps DFU or Rockchip's proprietary one) in SPL. Support is also provided for the Haier Chromebook, which is based on the same SoC. In this case it boots from SPI rather than an SD card. The basic approach here is to use driver model for everything, so this series adds several new uclasses. Some of these have been discussed for a while. The list is: - Clocks - setting and getting PLL and peripheral clocks - Pinctrl - adjusting pin multiplexing settings - Reset - reseting the board or SoC - RAM - setting up RAM controllers and detecting the available RAM - MMC - MMC controllers (using the existing block device framework) - LEDs - turning LEDs on and off, with only a GPIO driver so far Trivial support is also added for regmap and syscon controllers, modelled on how the kernel does this. This series avoids hard-coding RK3288-specific code into the build. There is a CONFIG_ROCKCHIP_RK3288 but it only *adds* support for RK3288. In principle another CONFIG could add support for a different Rockchip SoC with only the device tree selecting which one U-Boot works on. Support is provided in mkimage to build these image types: - rkimage - suitable for packaging up SPL to be sent to the boot ROM over USB OTG - rksd - suitable for writing to an SD card Much of the source and ideas for this series came from downstream Rockchip U-Boot trees. SDRAM init came from Coreboot. In most cases it has been pretty heavily cleaned up / rewritten to meet U-Boot style and remove hard-coding of things. Drivers are provided for: - Clocks - Pinctrl - SoC reset - DDR3 SDRAM - I2C - SPI - GPIOs - LEDs using GPIOS - MMC - Firefly main PMIC (ACT8846) and included regulators These are lightly tested and doubtless some problems exist with some, particularly I2C. One problem with device tree is that U-Boot has no way of dropping features it does not need or use. For SPL this problem needs to be solved and this series uses a new 'fdtgrep' tool for this. The 45KB Firefly device tree reduces to a 6KB bytes when unused material is removed. SDRAM timings are also in the device tree. This series includes some changes aimed at reduce code size in SPL, including: - dropping alias sequence support (the aliases node) since many boards just use a single UART in SPL - adding a smaller panic() function that does not support printf()-format strings - removing device unbind code which will never be used in SPL There is a large amount of additional work to bring other Rockchip drivers and features into mainline U-Boot, so this is only a start. Changes in v3: - Update clock rate to always be 24MHz - Add device tree bindings for CRU and DMC - Make use of additional features since version 2 - Update README to mention available drivers - Add various new patches to get RK3288 booting to a prompt Changes in v2: - Tidy up license headers and remove SPL #ifdefs - Tidy up license headers and remove SPL #ifdefs - Drop use of CONFIG_USE_PRIVATE_LIBGCC=y - Tidy up license headers and remove SPL #ifdefs Simon Glass (25): rockchip: Add serial support rockchip: Bring in RK3288 device tree file includes and bindings rockchip: rk3288: dts: Make core devices available early mkimage: Allow padding to any length mkimage: Allow the original file size to be recorded rockchip: Add the rkimage format to mkimage rockchip: Add support for the SD image rockchip: Add support for the SPI image rockchip: gpio: Add rockchip GPIO driver rockchip: Add basic peripheral and clock definitions power: Add support for ACT8846 PMIC power: regulator: Add a driver for ACT8846 regulators rockchip: rk3288: Add clock driver rockchip: rk3288: Add header files for PMU and GRF rockchip: rk3288: Add SoC reset driver rockchip: rk3288: Add a simple syscon driver rockchip: rk3288: Add pinctrl driver rockchip: rk3288: Add SDRAM init rockchip: Add an MMC driver rockchip: Add core SoC start-up code rockchip: Add I2C driver rockchip: Add SPI driver rockchip: Add basic support for firefly-rk3288 rockchip: Add basic support for jerry rockchip: Add a simple README arch/arm/Kconfig | 10 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 3 + arch/arm/dts/cros-ec-sbs.dtsi | 16 + arch/arm/dts/rk3288-firefly.dts | 75 + arch/arm/dts/rk3288-firefly.dtsi | 457 ++++++ arch/arm/dts/rk3288-jerry.dts | 203 +++ arch/arm/dts/rk3288-thermal.dtsi | 88 ++ arch/arm/dts/rk3288-veyron-chromebook.dtsi | 200 +++ arch/arm/dts/rk3288-veyron.dtsi | 844 +++++++++++ arch/arm/dts/rk3288.dtsi | 1473 ++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/clock.h | 45 + arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 185 +++ arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 484 +++++++ arch/arm/include/asm/arch-rockchip/gpio.h | 28 + arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 768 ++++++++++ arch/arm/include/asm/arch-rockchip/hardware.h | 20 + arch/arm/include/asm/arch-rockchip/i2c.h | 70 + arch/arm/include/asm/arch-rockchip/periph.h | 54 + arch/arm/include/asm/arch-rockchip/pmu_rk3288.h | 89 ++ arch/arm/include/asm/arch-rockchip/sdram.h | 92 ++ arch/arm/mach-rockchip/Kconfig | 41 + arch/arm/mach-rockchip/Makefile | 13 + arch/arm/mach-rockchip/board-spl.c | 290 ++++ arch/arm/mach-rockchip/board.c | 46 + arch/arm/mach-rockchip/common.c | 28 + arch/arm/mach-rockchip/rk3288/Kconfig | 26 + arch/arm/mach-rockchip/rk3288/Makefile | 9 + arch/arm/mach-rockchip/rk3288/reset_rk3288.c | 47 + arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 878 ++++++++++++ arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 25 + board/firefly/firefly-rk3288/Kconfig | 15 + board/firefly/firefly-rk3288/MAINTAINERS | 6 + board/firefly/firefly-rk3288/Makefile | 7 + board/firefly/firefly-rk3288/firefly-rk3288.c | 7 + board/google/chromebook_jerry/Kconfig | 15 + board/google/chromebook_jerry/MAINTAINERS | 6 + board/google/chromebook_jerry/Makefile | 7 + board/google/chromebook_jerry/jerry.c | 7 + board/google/common/Makefile | 2 +- common/image.c | 3 + configs/chromebook_jerry_defconfig | 37 + configs/firefly-rk3288_defconfig | 36 + doc/README.rockchip | 246 ++++ .../clock/rockchip,rk3188-cru.txt | 61 + .../clock/rockchip,rk3288-cru.txt | 61 + .../clock/rockchip,rk3288-dmc.txt | 155 ++ doc/device-tree-bindings/clock/rockchip.txt | 77 + .../pinctrl/rockchip,pinctrl.txt | 157 +++ .../thermal/rockchip-thermal.txt | 68 + drivers/clk/Makefile | 1 + drivers/clk/clk_rk3288.c | 618 ++++++++ drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/rk_gpio.c | 123 ++ drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/rk_i2c.c | 391 ++++++ drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/rockchip_mmc.c | 98 ++ drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/rockchip/Makefile | 8 + drivers/pinctrl/rockchip/pinctrl_rk3288.c | 429 ++++++ drivers/power/pmic/Kconfig | 9 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/act8846.c | 90 ++ drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/act8846.c | 155 ++ drivers/serial/Kconfig | 9 + drivers/serial/Makefile | 1 + drivers/serial/serial_rockchip.c | 43 + drivers/spi/Kconfig | 10 + drivers/spi/Makefile | 1 + drivers/spi/rk_spi.c | 375 +++++ drivers/spi/rk_spi.h | 121 ++ include/configs/chromebook_jerry.h | 16 + include/configs/firefly-rk3288.h | 15 + include/configs/rk3288_common.h | 101 ++ include/dt-bindings/clock/rk3288-cru.h | 370 +++++ include/dt-bindings/clock/rockchip,rk808.h | 11 + include/dt-bindings/pinctrl/rockchip.h | 26 + include/dt-bindings/power-domain/rk3288.h | 11 + include/image.h | 5 +- include/power/act8846_pmic.h | 37 + tools/Makefile | 3 + tools/imagetool.h | 1 + tools/mkimage.c | 23 +- tools/rkcommon.c | 72 + tools/rkcommon.h | 28 + tools/rkimage.c | 65 + tools/rksd.c | 102 ++ tools/rkspi.c | 119 ++ 95 files changed, 11106 insertions(+), 13 deletions(-) create mode 100644 arch/arm/dts/cros-ec-sbs.dtsi create mode 100644 arch/arm/dts/rk3288-firefly.dts create mode 100644 arch/arm/dts/rk3288-firefly.dtsi create mode 100644 arch/arm/dts/rk3288-jerry.dts create mode 100644 arch/arm/dts/rk3288-thermal.dtsi create mode 100644 arch/arm/dts/rk3288-veyron-chromebook.dtsi create mode 100644 arch/arm/dts/rk3288-veyron.dtsi create mode 100644 arch/arm/dts/rk3288.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/clock.h create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/gpio.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/hardware.h create mode 100644 arch/arm/include/asm/arch-rockchip/i2c.h create mode 100644 arch/arm/include/asm/arch-rockchip/periph.h create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3288.h create mode 100644 arch/arm/include/asm/arch-rockchip/sdram.h create mode 100644 arch/arm/mach-rockchip/Kconfig create mode 100644 arch/arm/mach-rockchip/Makefile create mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/board.c create mode 100644 arch/arm/mach-rockchip/common.c create mode 100644 arch/arm/mach-rockchip/rk3288/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3288/Makefile create mode 100644 arch/arm/mach-rockchip/rk3288/reset_rk3288.c create mode 100644 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c create mode 100644 arch/arm/mach-rockchip/rk3288/syscon_rk3288.c create mode 100644 board/firefly/firefly-rk3288/Kconfig create mode 100644 board/firefly/firefly-rk3288/MAINTAINERS create mode 100644 board/firefly/firefly-rk3288/Makefile create mode 100644 board/firefly/firefly-rk3288/firefly-rk3288.c create mode 100644 board/google/chromebook_jerry/Kconfig create mode 100644 board/google/chromebook_jerry/MAINTAINERS create mode 100644 board/google/chromebook_jerry/Makefile create mode 100644 board/google/chromebook_jerry/jerry.c create mode 100644 configs/chromebook_jerry_defconfig create mode 100644 configs/firefly-rk3288_defconfig create mode 100644 doc/README.rockchip create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt create mode 100644 doc/device-tree-bindings/clock/rockchip.txt create mode 100644 doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt create mode 100644 doc/device-tree-bindings/thermal/rockchip-thermal.txt create mode 100644 drivers/clk/clk_rk3288.c create mode 100644 drivers/gpio/rk_gpio.c create mode 100644 drivers/i2c/rk_i2c.c create mode 100644 drivers/mmc/rockchip_mmc.c create mode 100644 drivers/pinctrl/rockchip/Makefile create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3288.c create mode 100644 drivers/power/pmic/act8846.c create mode 100644 drivers/power/regulator/act8846.c create mode 100644 drivers/serial/serial_rockchip.c create mode 100644 drivers/spi/rk_spi.c create mode 100644 drivers/spi/rk_spi.h create mode 100644 include/configs/chromebook_jerry.h create mode 100644 include/configs/firefly-rk3288.h create mode 100644 include/configs/rk3288_common.h create mode 100644 include/dt-bindings/clock/rk3288-cru.h create mode 100644 include/dt-bindings/clock/rockchip,rk808.h create mode 100644 include/dt-bindings/pinctrl/rockchip.h create mode 100644 include/dt-bindings/power-domain/rk3288.h create mode 100644 include/power/act8846_pmic.h create mode 100644 tools/rkcommon.c create mode 100644 tools/rkcommon.h create mode 100644 tools/rkimage.c create mode 100644 tools/rksd.c create mode 100644 tools/rkspi.c -- 2.4.3.573.g4eafbef

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[U-Boot] [PATCH] imx: usb: ehci-mx6: wait_for_bit to check reg status
by Adrian Alonso 07 Aug '15

07 Aug '15

Add wait_for_bit to check reg bit status and replace unbounded loops to check usb command status Signed-off-by: Adrian Alonso <aalonso(a)freescale.com> --- Patch depends on the following patch set: imx: usb: ehci-mx6: add usb support for imx7d soc imx: usb: ehci-mx6: document board specific functions imx: usb: ehci-mx6: reg accessor cleanups drivers/usb/host/ehci-mx6.c | 37 +++++++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 54f8684..2666351 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -117,12 +117,39 @@ static void usb_power_config(int index) pll_480_ctrl_set); } +static int wait_for_bit(u32 *reg, const u32 mask, bool set) +{ + u32 val; + const unsigned int timeout = 10000; + unsigned long start = get_timer(0); + + while(1) { + val = readl(reg); + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + if (get_timer(start) > timeout) + break; + + udelay(1); + } + + debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", + __func__, reg, mask, set); + + return -ETIMEDOUT; +} + /* Return 0 : host node, <>0 : device mode */ static int usb_phy_enable(int index, struct usb_ehci *ehci) { void __iomem *phy_reg; void __iomem *phy_ctrl; void __iomem *usb_cmd; + int ret; if (index >= ARRAY_SIZE(phy_bases)) return 0; @@ -133,12 +160,14 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci) /* Stop then Reset */ clrbits_le32(usb_cmd, UCMD_RUN_STOP); - while (readl(usb_cmd) & UCMD_RUN_STOP) - ; + ret = wait_for_bit(usb_cmd, UCMD_RUN_STOP, 0); + if (ret) + return ret; setbits_le32(usb_cmd, UCMD_RESET); - while (readl(usb_cmd) & UCMD_RESET) - ; + ret = wait_for_bit(usb_cmd, UCMD_RESET, 0); + if (ret) + return ret; /* Reset USBPHY module */ setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); -- 2.1.4

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[U-Boot] [PATCH 1/3][v3] imx: usb: ehci-mx6: reg accessor cleanups
by Adrian Alonso 07 Aug '15

07 Aug '15

Cleanup read/write register access, use clr/set bits_le32 Signed-off-by: Adrian Alonso <aalonso(a)freescale.com> --- Changes for V2: Split from patch imx: usb: ehci-mx6: add usb support for imx7d soc Changes for V3: Resend drivers/usb/host/ehci-mx6.c | 51 ++++++++++++++++----------------------------- 1 file changed, 18 insertions(+), 33 deletions(-) diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 951dd3b..0f94c8b 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -67,7 +67,7 @@ static void usb_internal_phy_clock_gate(int index, int on) phy_reg = (void __iomem *)phy_bases[index]; phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; - __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg); + writel(USBPHY_CTRL_CLKGATE, phy_reg); } static void usb_power_config(int index) @@ -100,14 +100,14 @@ static void usb_power_config(int index) * is totally controlled by IC, so the Software only needs * to enable them at initializtion. */ - __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B | + writel(ANADIG_USB2_CHRG_DETECT_EN_B | ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, chrg_detect); - __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, + writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, pll_480_ctrl_clr); - __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | + writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | ANADIG_USB2_PLL_480_CTRL_POWER | ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, pll_480_ctrl_set); @@ -119,7 +119,6 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci) void __iomem *phy_reg; void __iomem *phy_ctrl; void __iomem *usb_cmd; - u32 val; if (index >= ARRAY_SIZE(phy_bases)) return 0; @@ -129,36 +128,27 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci) usb_cmd = (void __iomem *)&ehci->usbcmd; /* Stop then Reset */ - val = __raw_readl(usb_cmd); - val &= ~UCMD_RUN_STOP; - __raw_writel(val, usb_cmd); - while (__raw_readl(usb_cmd) & UCMD_RUN_STOP) + clrbits_le32(usb_cmd, UCMD_RUN_STOP); + while (readl(usb_cmd) & UCMD_RUN_STOP) ; - val = __raw_readl(usb_cmd); - val |= UCMD_RESET; - __raw_writel(val, usb_cmd); - while (__raw_readl(usb_cmd) & UCMD_RESET) + setbits_le32(usb_cmd, UCMD_RESET); + while (readl(usb_cmd) & UCMD_RESET) ; /* Reset USBPHY module */ - val = __raw_readl(phy_ctrl); - val |= USBPHY_CTRL_SFTRST; - __raw_writel(val, phy_ctrl); + setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); udelay(10); /* Remove CLKGATE and SFTRST */ - val = __raw_readl(phy_ctrl); - val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); - __raw_writel(val, phy_ctrl); + clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); udelay(10); /* Power up the PHY */ - __raw_writel(0, phy_reg + USBPHY_PWD); + writel(0, phy_reg + USBPHY_PWD); /* enable FS/LS device */ - val = __raw_readl(phy_ctrl); - val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3); - __raw_writel(val, phy_ctrl); + setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | + USBPHY_CTRL_ENUTMILEVEL3); return 0; } @@ -177,20 +167,15 @@ static void usb_oc_config(int index) struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET); void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); - u32 val; - val = __raw_readl(ctrl); #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 /* mx6qarm2 seems to required a different setting*/ - val &= ~UCTRL_OVER_CUR_POL; + clrbits_le32(ctrl, UCTRL_OVER_CUR_POL); #else - val |= UCTRL_OVER_CUR_POL; + setbits_le32(ctrl, UCTRL_OVER_CUR_POL); #endif - __raw_writel(val, ctrl); - val = __raw_readl(ctrl); - val |= UCTRL_OVER_CUR_DIS; - __raw_writel(val, ctrl); + setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); } int usb_phy_mode(int port) @@ -202,7 +187,7 @@ int usb_phy_mode(int port) phy_reg = (void __iomem *)phy_bases[port]; phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); - val = __raw_readl(phy_ctrl); + val = readl(phy_ctrl); if (val & USBPHY_CTRL_OTG_ID) return USB_INIT_DEVICE; @@ -257,7 +242,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (type == USB_INIT_DEVICE) return 0; setbits_le32(&ehci->usbmode, CM_HOST); - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); mdelay(10); -- 2.1.4

2 3

[U-Boot] [PATCH v5 1/5] dma: lpc32xx: add DMA driver
by slemieux.tyco＠gmail.com 06 Aug '15

06 Aug '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Incorporate DMA driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx DMA driver - lpc3250 header file DMA registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- Changes from v4 to v5: * Addressed Marek's comments on LPC32xx DMA driver: - Move macro use by the DMA client to write the next DMA linked list item address to NAND SLC driver. - updated "lpc32xx_dma_wait_status()" implementation to make if stetement easier to read. - updated multiline comments style. Changes from v3 to v4: * Addressed Marek's comments on LPC32xx DMA driver: - updated multiline comments style. - use "u32" instead of "uint32_t". - fixed unbounded loop. Changes from v2 to v3: * Addressed Marek's comments on LPC32xx DMA driver: - use defined in header file instead of local definition. - remove for loop and use "ffz()". * Provide define to assign next DMA linked list item address to removed typecast in DMA client (ex. NAND SLC). Changes from v1 to v2: * Moved the DMA patch as the first patch of the series. * The NAND SLC patch (link below) is applied before this patch: https://patchwork.ozlabs.org/patch/497308/ Update to the legacy driver to integrate with the latest u-boot: 1) Fixed checkpatch script output in legacy code. 2) Use LPC32xx definition from "cpu.h" and "clk.h". 3) Incorporate DMA specific register definition from "lpc3250.h" header file from legacy BSP patch from LPCLinux. 4) Use u-boot API for register access to remove the volatile in register definition taken from "lpc3250.h" header file. 5) Add DMA interface to "dma.h". 6) Add dma clock control register bits (clk.h). 7) Add functions to initialize the DMA clock. The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2) was downloaded from the LPCLinux Web site. arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 + arch/arm/include/asm/arch-lpc32xx/clk.h | 3 + arch/arm/include/asm/arch-lpc32xx/dma.h | 37 ++++++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + drivers/dma/Makefile | 1 + drivers/dma/lpc32xx_dma.c | 163 ++++++++++++++++++++++++++ 6 files changed, 211 insertions(+) create mode 100644 arch/arm/include/asm/arch-lpc32xx/dma.h create mode 100644 drivers/dma/lpc32xx_dma.c diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index c0c9c6c..0d2ef7a 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -65,6 +65,12 @@ void lpc32xx_slc_nand_init(void) writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl); } +void lpc32xx_dma_init(void) +{ + /* Enable DMA interface */ + setbits_le32(&clk->dmaclk_ctrl, DMA_CLK_ENABLE); +} + void lpc32xx_i2c_init(unsigned int devnum) { /* Enable I2C interface */ diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 010211a..663f6bc 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -158,6 +158,9 @@ struct clk_pm_regs { #define CLK_NAND_SLC_SELECT (1 << 2) #define CLK_NAND_MLC_INT (1 << 5) +/* DMA Clock Control Register bits */ +#define DMA_CLK_ENABLE (1 << 0) + /* SSP Clock Control Register bits */ #define CLK_SSP0_ENABLE_CLOCK (1 << 0) diff --git a/arch/arm/include/asm/arch-lpc32xx/dma.h b/arch/arm/include/asm/arch-lpc32xx/dma.h new file mode 100644 index 0000000..15d829c --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/dma.h @@ -0,0 +1,37 @@ +/* + * LPC32xx DMA Controller Interface + * + * Copyright (C) 2008-2015 by NXP Semiconductors + * All rights reserved. + * + * @Author: Kevin Wells + * @Descr: Definitions for LPC3250 chip + * @References: NXP LPC3250 User's Guide + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _LPC32XX_DMA_H +#define _LPC32XX_DMA_H + +#include <common.h> + +/* + * DMA linked list structure used with a channel's LLI register; + * refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3 + * tables 84, 85, 86 & 87 for details. + */ +struct lpc32xx_dmac_ll { + u32 dma_src; + u32 dma_dest; + u32 next_lli; + u32 next_ctrl; +}; + +int lpc32xx_dma_get_channel(void); +int lpc32xx_dma_start_xfer(int channel, const struct lpc32xx_dmac_ll *desc, + u32 config); +int lpc32xx_dma_wait_status(int channel); +void lpc32xx_dma_put_channel(int channel); + +#endif /* _LPC32XX_DMA_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index 0845f83..7f997d9 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -13,6 +13,7 @@ void lpc32xx_uart_init(unsigned int uart_id); void lpc32xx_mac_init(void); void lpc32xx_mlc_nand_init(void); void lpc32xx_slc_nand_init(void); +void lpc32xx_dma_init(void); void lpc32xx_i2c_init(unsigned int devnum); void lpc32xx_ssp_init(void); #if defined(CONFIG_SPL_BUILD) diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 4c8fcc2..f95fe70 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_APBH_DMA) += apbh_dma.o obj-$(CONFIG_FSL_DMA) += fsl_dma.o obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o obj-$(CONFIG_TI_EDMA3) += ti-edma3.o +obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o diff --git a/drivers/dma/lpc32xx_dma.c b/drivers/dma/lpc32xx_dma.c new file mode 100644 index 0000000..0452013 --- /dev/null +++ b/drivers/dma/lpc32xx_dma.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2008-2015 by NXP Semiconductors + * All rights reserved. + * + * @Author: Kevin Wells + * @Descr: LPC3250 DMA controller interface support functions + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/dma.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> + +/* + * Notes: + * + * Only bitfield masks/values which are actually used by the driver + * are defined. + */ + +/* DMA controller channel register structure */ +struct dmac_chan_reg { + u32 src_addr; + u32 dest_addr; + u32 lli; + u32 control; + u32 config_ch; + u32 reserved[3]; +}; + +/* DMA controller register structures */ +struct dma_reg { + u32 int_stat; + u32 int_tc_stat; + u32 int_tc_clear; + u32 int_err_stat; + u32 int_err_clear; + u32 raw_tc_stat; + u32 raw_err_stat; + u32 chan_enable; + u32 sw_burst_req; + u32 sw_single_req; + u32 sw_last_burst_req; + u32 sw_last_single_req; + u32 config; + u32 sync; + u32 reserved[50]; + struct dmac_chan_reg dma_chan[8]; +}; + +/* Macro pointing to DMA registers */ +#define DMA_NO_OF_CHANNELS 8 + +/* config register definitions */ +#define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */ + +static u32 alloc_ch; + +static struct dma_reg *dma = (struct dma_reg *)DMA_BASE; + +int lpc32xx_dma_get_channel(void) +{ + int i; + + if (!alloc_ch) { /* First time caller */ + /* + * DMA clock are enable by "lpc32xx_dma_init()" and should + * be call by board "board_early_init_f()" function. + */ + + /* + * Make sure DMA controller and all channels are disabled. + * Controller is in little-endian mode. Disable sync signals. + */ + writel(0, &dma->config); + writel(0, &dma->sync); + + /* Clear interrupt and error statuses */ + writel(0xFF, &dma->int_tc_clear); + writel(0xFF, &dma->raw_tc_stat); + writel(0xFF, &dma->int_err_clear); + writel(0xFF, &dma->raw_err_stat); + + /* Enable DMA controller */ + writel(DMAC_CTRL_ENABLE, &dma->config); + } + + i = ffz(alloc_ch); + + /* Check if all the available channels are busy */ + if (unlikely(i == DMA_NO_OF_CHANNELS)) + return -1; + alloc_ch |= BIT_MASK(i); + return i; +} + +int lpc32xx_dma_start_xfer(int channel, const struct lpc32xx_dmac_ll *desc, + u32 config) +{ + if (unlikely((BIT_MASK(channel) & alloc_ch) == 0)) { + printf("ERR: Request for xfer on unallocated channel %d\r\n", + channel); + BUG(); + } + writel(BIT_MASK(channel), &dma->int_tc_clear); + writel(BIT_MASK(channel), &dma->int_err_clear); + writel(desc->dma_src, &dma->dma_chan[channel].src_addr); + writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr); + writel(desc->next_lli, &dma->dma_chan[channel].lli); + writel(desc->next_ctrl, &dma->dma_chan[channel].control); + writel(config, &dma->dma_chan[channel].config_ch); + + return 0; +} + +int lpc32xx_dma_wait_status(int channel) +{ + unsigned long start; + u32 reg; + + start = get_timer(0); + while (1) { + reg = readl(&dma->raw_tc_stat); + reg |= readl(dma->raw_err_stat); + if (reg & BIT_MASK(channel)) + break; + + if (get_timer(start) > 10000) + return -1; + + udelay(1); + } + + if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) { + setbits_le32(&dma->int_err_clear, BIT_MASK(channel)); + setbits_le32(&dma->raw_err_stat, BIT_MASK(channel)); + return -1; + } + setbits_le32(&dma->int_tc_clear, BIT_MASK(channel)); + setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel)); + return 0; +} + +void lpc32xx_dma_put_channel(int channel) +{ + /* Check if given channel no is valid */ + if (channel >= DMA_NO_OF_CHANNELS || channel < 0) + return; + alloc_ch &= ~BIT_MASK(channel); + + /* Shut down channel */ + writel(0, &dma->dma_chan[channel].control); + writel(0, &dma->dma_chan[channel].config_ch); + clrbits_le32(&dma->sync, BIT_MASK(channel)); + + if (!alloc_ch) + /* Disable DMA controller */ + clrbits_le32(&dma->config, DMAC_CTRL_ENABLE); +} -- 1.8.3.1

4 5

[U-Boot] [PATCH V4 1/2] ARM: tegra: Add e2220-1170 board
by Stephen Warren 06 Aug '15

06 Aug '15

From: Stephen Warren <swarren(a)nvidia.com> E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various expansion modules. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- v4: Remove a couple unused #defines from config header. v3: * More descriptions. * Add auto-generation notice to pinmux header. * Incorporate equivalent cleanups to those made to p2571. v2: Use named constants for PMIC I2C and register addresses. --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra210-e2220-1170.dts | 58 +++++ arch/arm/mach-tegra/tegra210/Kconfig | 8 + board/nvidia/e2220-1170/Kconfig | 12 + board/nvidia/e2220-1170/MAINTAINERS | 6 + board/nvidia/e2220-1170/Makefile | 8 + board/nvidia/e2220-1170/e2220-1170.c | 51 ++++ board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 277 +++++++++++++++++++++ configs/e2220-1170_defconfig | 17 ++ include/configs/e2220-1170.h | 65 +++++ 10 files changed, 503 insertions(+) create mode 100644 arch/arm/dts/tegra210-e2220-1170.dts create mode 100644 board/nvidia/e2220-1170/Kconfig create mode 100644 board/nvidia/e2220-1170/MAINTAINERS create mode 100644 board/nvidia/e2220-1170/Makefile create mode 100644 board/nvidia/e2220-1170/e2220-1170.c create mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h create mode 100644 configs/e2220-1170_defconfig create mode 100644 include/configs/e2220-1170.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ba6355379cba..d8e1841eb4d8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ tegra124-venice2.dtb \ + tegra210-e2220-1170.dtb \ tegra210-p2571.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-sld3-ref.dtb \ diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210-e2220-1170.dts new file mode 100644 index 000000000000..75efbba1061e --- /dev/null +++ b/arch/arm/dts/tegra210-e2220-1170.dts @@ -0,0 +1,58 @@ +/dts-v1/; + +#include "tegra210.dtsi" + +/ { + model = "NVIDIA E2220-1170"; + compatible = "nvidia,e2220-1170", "nvidia,tegra210"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@0,7000d000"; + sdhci0 = "/sdhci@0,700b0600"; + sdhci1 = "/sdhci@0,700b0000"; + usb0 = "/usb@0,7d000000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + sdhci@0,700b0000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@0,700b0600 { + status = "okay"; + bus-width = <8>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + usb@0,7d000000 { + status = "okay"; + dr_mode = "peripheral"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig index 147e6a83d722..a33fc5ce76b7 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -3,6 +3,13 @@ if TEGRA210 choice prompt "Tegra210 board select" +config TARGET_E2220_1170 + bool "NVIDIA Tegra210 E2220-1170 board" + help + E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM, + eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various + expansion modules. + config TARGET_P2571 bool "NVIDIA Tegra210 P2571 base board" help @@ -13,6 +20,7 @@ endchoice config SYS_SOC default "tegra210" +source "board/nvidia/e2220-1170/Kconfig" source "board/nvidia/p2571/Kconfig" endif diff --git a/board/nvidia/e2220-1170/Kconfig b/board/nvidia/e2220-1170/Kconfig new file mode 100644 index 000000000000..0a30f4936223 --- /dev/null +++ b/board/nvidia/e2220-1170/Kconfig @@ -0,0 +1,12 @@ +if TARGET_E2220_1170 + +config SYS_BOARD + default "e2220-1170" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "e2220-1170" + +endif diff --git a/board/nvidia/e2220-1170/MAINTAINERS b/board/nvidia/e2220-1170/MAINTAINERS new file mode 100644 index 000000000000..0abb37884018 --- /dev/null +++ b/board/nvidia/e2220-1170/MAINTAINERS @@ -0,0 +1,6 @@ +E2220-1170 BOARD +M: Tom Warren <twarren(a)nvidia.com> +S: Maintained +F: board/nvidia/e2220-1170/ +F: include/configs/e2220-1170.h +F: configs/e2220-1170_defconfig diff --git a/board/nvidia/e2220-1170/Makefile b/board/nvidia/e2220-1170/Makefile new file mode 100644 index 000000000000..c956b1972deb --- /dev/null +++ b/board/nvidia/e2220-1170/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2013-2015 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += e2220-1170.o diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c new file mode 100644 index 000000000000..d66a72e5204c --- /dev/null +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include "../p2571/max77620_init.h" +#include "pinmux-config-e2220-1170.h" + +void pin_mux_mmc(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); +} + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_clear_tristate_input_clamping(); + + gpio_config_table(e2220_1170_gpio_inits, + ARRAY_SIZE(e2220_1170_gpio_inits)); + + pinmux_config_pingrp_table(e2220_1170_pingrps, + ARRAY_SIZE(e2220_1170_pingrps)); + + pinmux_config_drvgrp_table(e2220_1170_drvgrps, + ARRAY_SIZE(e2220_1170_drvgrps)); +} diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h new file mode 100644 index 000000000000..7eb1e6c1b3e9 --- /dev/null +++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * THIS FILE IS AUTO-GENERATED - DO NOT EDIT! + * + * To generate this file, use the tegra-pinmux-scripts tool available from + * https://github.com/NVIDIA/tegra-pinmux-scripts + * Run "board-to-uboot.py e2220-1170". + */ + +#ifndef _PINMUX_CONFIG_E2220_1170_H_ +#define _PINMUX_CONFIG_E2220_1170_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config e2220_1170_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A5, IN), + GPIO_INIT(A6, IN), + GPIO_INIT(B4, IN), + GPIO_INIT(E6, IN), + GPIO_INIT(G2, OUT0), + GPIO_INIT(G3, OUT0), + GPIO_INIT(H0, OUT0), + GPIO_INIT(H1, OUT0), + GPIO_INIT(H2, IN), + GPIO_INIT(H3, OUT0), + GPIO_INIT(H4, OUT0), + GPIO_INIT(H5, IN), + GPIO_INIT(H6, OUT0), + GPIO_INIT(H7, OUT0), + GPIO_INIT(I0, OUT0), + GPIO_INIT(I1, IN), + GPIO_INIT(I2, OUT0), + GPIO_INIT(I3, OUT0), + GPIO_INIT(K0, IN), + GPIO_INIT(K1, OUT0), + GPIO_INIT(K2, OUT0), + GPIO_INIT(K3, OUT0), + GPIO_INIT(K4, IN), + GPIO_INIT(K5, OUT0), + GPIO_INIT(K6, IN), + GPIO_INIT(K7, OUT0), + GPIO_INIT(L0, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S5, OUT0), + GPIO_INIT(S6, OUT0), + GPIO_INIT(S7, OUT0), + GPIO_INIT(T0, OUT0), + GPIO_INIT(T1, OUT0), + GPIO_INIT(V1, OUT0), + GPIO_INIT(V2, OUT0), + GPIO_INIT(V3, IN), + GPIO_INIT(V5, OUT0), + GPIO_INIT(V6, OUT0), + GPIO_INIT(X0, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X2, IN), + GPIO_INIT(X3, IN), + GPIO_INIT(X4, IN), + GPIO_INIT(X5, IN), + GPIO_INIT(X6, IN), + GPIO_INIT(X7, IN), + GPIO_INIT(Y0, IN), + GPIO_INIT(Y1, IN), + GPIO_INIT(Z0, IN), + GPIO_INIT(Z4, OUT0), + GPIO_INIT(BB2, OUT0), + GPIO_INIT(BB3, OUT0), + GPIO_INIT(BB4, IN), + GPIO_INIT(CC1, IN), + GPIO_INIT(CC5, OUT0), + GPIO_INIT(CC6, IN), + GPIO_INIT(CC7, OUT0), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + } + +static const struct pmux_pingrp_config e2220_1170_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ + PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MOSI_PB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MOSI_PC0, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MISO_PC1, SPI1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_SCK_PC2, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS0_PC3, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS1_PC4, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_CTS_PD4, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_DAT_PE1, DMIC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_DAT_PE3, DMIC2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_DAT_PE5, DMIC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(UART2_TX_PG0, UART, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_RX_PG1, UART, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART2_RTS_PG2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO1_PV3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X3_AUD_PBB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SPDIF_OUT_PCC2, SPDIF, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPDIF_IN_PCC3, SPDIF, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(USB_VBUS_EN1_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_E2220_1170_H */ diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig new file mode 100644 index 000000000000..455e7892b5cb --- /dev/null +++ b/configs/e2220-1170_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA210=y +CONFIG_TARGET_E2220_1170=y +CONFIG_DEFAULT_DEVICE_TREE="tegra210-e2220-1170" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPL_DM=y +CONFIG_TEGRA114_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h new file mode 100644 index 000000000000..dff3f2a35733 --- /dev/null +++ b/include/configs/e2220-1170.h @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _E2220_1170_H +#define _E2220_1170_H + +#include <linux/sizes.h> + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra210 (E2220-1170) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA E2220-1170" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB2.0 Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#define COUNTER_FREQUENCY 38400000 + +#endif /* _E2220_1170_H */ -- 1.9.1

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