August 2015 - U-Boot

[U-Boot] [PATCH v6 2/5] nand: lpc32xx: add hardware ECC support
by slemieux.tyco＠gmail.com 11 Aug '15

11 Aug '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP. The code taken from the legacy patch is: - lpc32xx SLC NAND driver (hardware ECC support) - lpc3250 header file missing SLC NAND registers definition The legacy driver code was updated to integrate with the existing NAND SLC driver. Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- Changes from v5 to v6: * Addressed Vladimir's comments on LPC32xx NAND SLC driver: - move DMAC registers definitions from NAND SLC to "dma.h". - update NAND SLC to use the new DMA channel API. - generate the fatal BUG on the client side when attempting a transfer on an unallocated DMA channel. - kept the original order for read/write byte/buf functions. * Following feedback on maillist from Vladimir, the following update were done: - the ECC size / ECC bytes are fix to 256 & 3 in the driver. - add comments regarding the ECC correction done by page when using the DMA controller scatter/gather mode through linked list (i.e. ECC correction process). - definition used for managing small vs. large page were updated inside the driver to make them more clear. - definition used for the ECC process when the DMA is enable were updated to avoid any confusion with basic definition. - possible to select small page NAND using a single define. - use define instead of value for internal process logic. Changes from v4 to v5: * Addressed Marek's comments on LPC32xx NAND SLC driver: - Move macro use by the DMA client to write the next DMA linked list item address to NAND SLC driver. * Updated multiline comments style. * Use "uxx" instead of "uintxx_t" (new code), note: keep uintxx_t for API; to match initial patch. Changes from v3 to v4: * No changes. Changes from v2 to v3: * As per feedback on mailing list from Vladimir, - add warning when DMA and SPL build option are selected. - add another DMA specific read and write buffer functions. * Addressed Marek's comments on LPC32xx NAND SLC driver removed typecast and update variable type, when possible. * As per discussion on mailing list with Vladimir & Marek, updated conditional compile option (DMA only) to build the original NAND SLC code using software ECC. * Re-organized the conditional compile code inside "board_nand_init()" - DMA vs. non-DMA initialization. * Added original source code credit (copyright & author). Changes from v1 to v2: * Moved the NAND SLC patch as the second patch of the series. * As per discussion on mailing list with Vladimir, incorporate NAND SLC hardware ECC support into the following NAND SLC patch: https://patchwork.ozlabs.org/patch/497308/ * As per discussion on mailing list with Vladimir & Albert, add conditional compile option to build the original NAND SLC code using software ECC for SPL build. * Removed ECC layout for small page NAND from this patch. Update to the legacy code to integrate with the NAND SLC patch: 1) Fixed checkpatch script output in legacy code. 2) Use u-boot API for register access to remove the volatile in register definition taken from "lpc3250.h" header file. 3) Use register definition from the NAND SLC patch. The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2) was downloaded from the LPCLinux Web site. drivers/mtd/nand/lpc32xx_nand_slc.c | 382 +++++++++++++++++++++++++++++++++++- 1 file changed, 378 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c index 719a74d..2a32264 100644 --- a/drivers/mtd/nand/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/lpc32xx_nand_slc.c @@ -3,15 +3,48 @@ * * (C) Copyright 2015 Vladimir Zapolskiy <vz(a)mleia.com> * + * Hardware ECC support original source code + * Copyright (C) 2008 by NXP Semiconductors + * Author: Kevin Wells + * + * Copyright (c) 2015 Tyco Fire Protection Products. + * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <nand.h> +#include <linux/mtd/nand_ecc.h> #include <asm/errno.h> #include <asm/io.h> #include <asm/arch/clk.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/dma.h> +#include <asm/arch/cpu.h> + +#if defined(CONFIG_DMA_LPC32XX) && defined(CONFIG_SPL_BUILD) +#warning "DMA support in SPL image is not tested" +#endif + +/* Provide default for page size (large page), if target did not. */ +#if !defined(CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#endif + +#define NAND_LARGE_BLOCK_PAGE_SIZE 2048 +#define NAND_SMALL_BLOCK_PAGE_SIZE 512 + +/* Verify if a valid page size was define and configure OOB size. */ +#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 64 +#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 16 +#else +#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" +#endif + +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSIZE 256 struct lpc32xx_nand_slc_regs { u32 data; @@ -33,11 +66,18 @@ struct lpc32xx_nand_slc_regs { /* CFG register */ #define CFG_CE_LOW (1 << 5) +#define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */ +#define CFG_ECC_EN (1 << 3) /* ECC enable bit */ +#define CFG_DMA_BURST (1 << 2) /* DMA burst bit */ +#define CFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */ /* CTRL register */ #define CTRL_SW_RESET (1 << 2) +#define CTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */ +#define CTRL_DMA_START (1 << 0) /* Start DMA channel bit */ /* STAT register */ +#define STAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */ #define STAT_NAND_READY (1 << 0) /* INT_STAT register */ @@ -54,6 +94,33 @@ struct lpc32xx_nand_slc_regs { #define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4) #define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0) +#if defined(CONFIG_DMA_LPC32XX) +/* Total ECC bytes and size; refer to board_nand_init() for details. */ +#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) +#define TOTAL_ECCBYTES (CONFIG_SYS_NAND_ECCBYTES * ECCSTEPS) +#define TOTAL_ECCSIZE (CONFIG_SYS_NAND_ECCSIZE * ECCSTEPS) + +/* + * DMA Descriptors + * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area) + * For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area) + */ +static struct lpc32xx_dmac_ll dmalist[ECCSTEPS * 2 + 1]; +static u32 ecc_buffer[8]; /* MAX ECC size */ +static unsigned int dmachan = (unsigned int)-1; /* Invalid channel */ + +/* + * Helper macro for the DMA client (i.e. NAND SLC): + * - to write the next DMA linked list item address + * (see arch/include/asm/arch-lpc32xx/dma.h). + * - to assign the DMA data register to DMA source or destination address. + * - to assign the ECC register to DMA source or destination address. + */ +#define lpc32xx_dmac_next_lli(x) ((u32)x) +#define lpc32xx_dmac_set_dma_data() ((u32)&lpc32xx_nand_slc_regs->dma_data) +#define lpc32xx_dmac_set_ecc() ((u32)&lpc32xx_nand_slc_regs->ecc) +#endif + static struct lpc32xx_nand_slc_regs __iomem *lpc32xx_nand_slc_regs = (struct lpc32xx_nand_slc_regs __iomem *)SLC_NAND_BASE; @@ -108,22 +175,278 @@ static int lpc32xx_nand_dev_ready(struct mtd_info *mtd) return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY; } +#if defined(CONFIG_DMA_LPC32XX) +/* + * Prepares DMA descriptors for NAND RD/WR operations + * If the size is < 256 Bytes then it is assumed to be + * an OOB transfer + */ +static void lpc32xx_nand_dma_configure(struct nand_chip *chip, + const u8 *buffer, int size, + int read) +{ + u32 i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst; + struct lpc32xx_dmac_ll *dmalist_cur; + struct lpc32xx_dmac_ll *dmalist_cur_ecc; + + /* + * CTRL descriptor entry for reading ECC + * Copy Multiple times to sync DMA with Flash Controller + */ + ecc_ctrl = 0x5 | + DMAC_CHAN_SRC_BURST_1 | + DMAC_CHAN_DEST_BURST_1 | + DMAC_CHAN_SRC_WIDTH_32 | + DMAC_CHAN_DEST_WIDTH_32 | + DMAC_CHAN_DEST_AHB1; + + /* CTRL descriptor entry for reading/writing Data */ + ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) | + DMAC_CHAN_SRC_BURST_4 | + DMAC_CHAN_DEST_BURST_4 | + DMAC_CHAN_SRC_WIDTH_32 | + DMAC_CHAN_DEST_WIDTH_32 | + DMAC_CHAN_DEST_AHB1; + + /* CTRL descriptor entry for reading/writing Spare Area */ + oob_ctrl = (CONFIG_SYS_NAND_OOBSIZE / 4) | + DMAC_CHAN_SRC_BURST_4 | + DMAC_CHAN_DEST_BURST_4 | + DMAC_CHAN_SRC_WIDTH_32 | + DMAC_CHAN_DEST_WIDTH_32 | + DMAC_CHAN_DEST_AHB1; + + if (read) { + dmasrc = lpc32xx_dmac_set_dma_data(); + dmadst = (u32)buffer; + ctrl |= DMAC_CHAN_DEST_AUTOINC; + } else { + dmadst = lpc32xx_dmac_set_dma_data(); + dmasrc = (u32)buffer; + ctrl |= DMAC_CHAN_SRC_AUTOINC; + } + + /* + * Write Operation Sequence for Small Block NAND + * ---------------------------------------------------------- + * 1. X'fer 256 bytes of data from Memory to Flash. + * 2. Copy generated ECC data from Register to Spare Area + * 3. X'fer next 256 bytes of data from Memory to Flash. + * 4. Copy generated ECC data from Register to Spare Area. + * 5. X'fer 16 byets of Spare area from Memory to Flash. + * Read Operation Sequence for Small Block NAND + * ---------------------------------------------------------- + * 1. X'fer 256 bytes of data from Flash to Memory. + * 2. Copy generated ECC data from Register to ECC calc Buffer. + * 3. X'fer next 256 bytes of data from Flash to Memory. + * 4. Copy generated ECC data from Register to ECC calc Buffer. + * 5. X'fer 16 bytes of Spare area from Flash to Memory. + * Write Operation Sequence for Large Block NAND + * ---------------------------------------------------------- + * 1. Steps(1-4) of Write Operations repeate for four times + * which generates 16 DMA descriptors to X'fer 2048 bytes of + * data & 32 bytes of ECC data. + * 2. X'fer 64 bytes of Spare area from Memory to Flash. + * Read Operation Sequence for Large Block NAND + * ---------------------------------------------------------- + * 1. Steps(1-4) of Read Operations repeate for four times + * which generates 16 DMA descriptors to X'fer 2048 bytes of + * data & 32 bytes of ECC data. + * 2. X'fer 64 bytes of Spare area from Flash to Memory. + */ + + for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) { + dmalist_cur = &dmalist[i * 2]; + dmalist_cur_ecc = &dmalist[(i * 2) + 1]; + + dmalist_cur->dma_src = (read ? (dmasrc) : (dmasrc + (i*256))); + dmalist_cur->dma_dest = (read ? (dmadst + (i*256)) : dmadst); + dmalist_cur->next_lli = lpc32xx_dmac_next_lli(dmalist_cur_ecc); + dmalist_cur->next_ctrl = ctrl; + + dmalist_cur_ecc->dma_src = lpc32xx_dmac_set_ecc(); + dmalist_cur_ecc->dma_dest = (u32)&ecc_buffer[i]; + dmalist_cur_ecc->next_lli = + lpc32xx_dmac_next_lli(&dmalist[(i * 2) + 2]); + dmalist_cur_ecc->next_ctrl = ecc_ctrl; + } + + if (i) { /* Data only transfer */ + dmalist_cur_ecc = &dmalist[(i * 2) - 1]; + dmalist_cur_ecc->next_lli = 0; + dmalist_cur_ecc->next_ctrl |= DMAC_CHAN_INT_TC_EN; + return; + } + + /* OOB only transfer */ + if (read) { + dmasrc = lpc32xx_dmac_set_dma_data(); + dmadst = (u32)buffer; + oob_ctrl |= DMAC_CHAN_DEST_AUTOINC; + } else { + dmadst = lpc32xx_dmac_set_dma_data(); + dmasrc = (u32)buffer; + oob_ctrl |= DMAC_CHAN_SRC_AUTOINC; + } + + /* Read/ Write Spare Area Data To/From Flash */ + dmalist_cur = &dmalist[i * 2]; + dmalist_cur->dma_src = dmasrc; + dmalist_cur->dma_dest = dmadst; + dmalist_cur->next_lli = 0; + dmalist_cur->next_ctrl = (oob_ctrl | DMAC_CHAN_INT_TC_EN); +} + +static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf, + int len, int read) +{ + struct nand_chip *chip = mtd->priv; + u32 config; + int ret; + + /* DMA Channel Configuration */ + config = (read ? DMAC_CHAN_FLOW_D_P2M : DMAC_CHAN_FLOW_D_M2P) | + (read ? DMAC_DEST_PERIP(0) : DMAC_DEST_PERIP(DMA_PERID_NAND1)) | + (read ? DMAC_SRC_PERIP(DMA_PERID_NAND1) : DMAC_SRC_PERIP(0)) | + DMAC_CHAN_ENABLE; + + /* Prepare DMA descriptors */ + lpc32xx_nand_dma_configure(chip, buf, len, read); + + /* Setup SLC controller and start transfer */ + if (read) + setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR); + else /* NAND_ECC_WRITE */ + clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR); + setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_BURST); + + /* Write length for new transfers */ + if (!((readl(&lpc32xx_nand_slc_regs->stat) & STAT_DMA_FIFO) | + readl(&lpc32xx_nand_slc_regs->tc))) { + int tmp = (len != mtd->oobsize) ? mtd->oobsize : 0; + writel(len + tmp, &lpc32xx_nand_slc_regs->tc); + } + + setbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START); + + /* Start DMA transfers */ + ret = lpc32xx_dma_start_xfer(dmachan, dmalist, config); + if (unlikely(ret < 0)) + BUG(); + + + /* Wait for NAND to be ready */ + while (!lpc32xx_nand_dev_ready(mtd)) + ; + + /* Wait till DMA transfer is DONE */ + if (lpc32xx_dma_wait_status(dmachan)) + pr_err("NAND DMA transfer error!\r\n"); + + /* Stop DMA & HW ECC */ + clrbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START); + clrbits_le32(&lpc32xx_nand_slc_regs->cfg, + CFG_DMA_DIR | CFG_DMA_BURST | CFG_ECC_EN | CFG_DMA_ECC); +} + +static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count) +{ + int i; + for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES); + i += CONFIG_SYS_NAND_ECCBYTES) { + u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES]; + ce = ~(ce << 2) & 0xFFFFFF; + spare[i+2] = (u8)(ce & 0xFF); ce >>= 8; + spare[i+1] = (u8)(ce & 0xFF); ce >>= 8; + spare[i] = (u8)(ce & 0xFF); + } + return 0; +} + +static int lpc32xx_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc_code) +{ + return slc_ecc_copy_to_buffer(ecc_code, ecc_buffer, ECCSTEPS); +} + +/* + * Enables and prepares SLC NAND controller + * for doing data transfers with H/W ECC enabled. + */ +static void lpc32xx_hwecc_enable(struct mtd_info *mtd, int mode) +{ + /* Clear ECC */ + writel(CTRL_ECC_CLEAR, &lpc32xx_nand_slc_regs->ctrl); + + /* Setup SLC controller for H/W ECC operations */ + setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_ECC_EN | CFG_DMA_ECC); +} + +/* + * lpc32xx_correct_data - [NAND Interface] Detect and correct bit error(s) + * mtd: MTD block structure + * dat: raw data read from the chip + * read_ecc: ECC from the chip + * calc_ecc: the ECC calculated from raw data + * + * Detect and correct a 1 bit error for 256 byte block + */ +int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + unsigned int i; + int ret1, ret2 = 0; + u_char *r = read_ecc; + u_char *c = calc_ecc; + u16 data_offset = 0; + + for (i = 0 ; i < ECCSTEPS ; i++) { + r += CONFIG_SYS_NAND_ECCBYTES; + c += CONFIG_SYS_NAND_ECCBYTES; + data_offset += CONFIG_SYS_NAND_ECCSIZE; + + ret1 = nand_correct_data(mtd, dat + data_offset, r, c); + if (ret1 < 0) + return -EBADMSG; + else + ret2 += ret1; + } + + return ret2; +} +#endif + +#if defined(CONFIG_DMA_LPC32XX) +static void lpc32xx_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + lpc32xx_nand_xfer(mtd, buf, len, 1); +} +#else static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { while (len-- > 0) *buf++ = readl(&lpc32xx_nand_slc_regs->data); } +#endif static uint8_t lpc32xx_read_byte(struct mtd_info *mtd) { return readl(&lpc32xx_nand_slc_regs->data); } +#if defined(CONFIG_DMA_LPC32XX) +static void lpc32xx_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf, + int len) +{ + lpc32xx_nand_xfer(mtd, buf, len, 0); +} +#else static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { while (len-- > 0) writel(*buf++, &lpc32xx_nand_slc_regs->data); } +#endif static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte) { @@ -137,10 +460,61 @@ static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte) */ int board_nand_init(struct nand_chip *lpc32xx_chip) { +#if defined(CONFIG_DMA_LPC32XX) + int ret; + + /* Acquire a channel for our use */ + ret = lpc32xx_dma_get_channel(); + if (unlikely(ret < 0)) { + pr_info("Unable to get free DMA channel for NAND transfers\n"); + return -1; + } + dmachan = (unsigned int)ret; +#endif + lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl; lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready; /* + * The implementation of these functions is quite common, but + * they MUST be defined, because access to data register + * is strictly 32-bit aligned. + */ + lpc32xx_chip->read_byte = lpc32xx_read_byte; + lpc32xx_chip->write_byte = lpc32xx_write_byte; + +#if defined(CONFIG_DMA_LPC32XX) + /* + * Hardware ECC calculation is supported when + * DMA driver is selected. + */ + lpc32xx_chip->ecc.mode = NAND_ECC_HW; + + lpc32xx_chip->read_buf = lpc32xx_dma_read_buf; + lpc32xx_chip->write_buf = lpc32xx_dma_write_buf; + + lpc32xx_chip->ecc.calculate = lpc32xx_ecc_calculate; + lpc32xx_chip->ecc.correct = lpc32xx_correct_data; + lpc32xx_chip->ecc.hwctl = lpc32xx_hwecc_enable; + lpc32xx_chip->chip_delay = 2000; + + /* + * ECC correction is done by page when using the DMA controller + * scatter/gather mode through linked list; + * refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3 + * section 9.7 and tables 173 notes for details. + * + * The error correction is done on each page and process in multiple + * steps of 256 bytes inside the driver. + * + * The total ECC size and bytes for a page are used; + * NAND base code (HW ECC) will call the read / write buffer functions + * using the total ECC size and bytes for a page as a single step. + */ + lpc32xx_chip->ecc.size = TOTAL_ECCSIZE; + lpc32xx_chip->ecc.bytes = TOTAL_ECCBYTES; +#else + /* * Hardware ECC calculation is not supported by the driver, * because it requires DMA support, see LPC32x0 User Manual, * note after SLC_ECC register description (UM10326, p.198) @@ -153,16 +527,16 @@ int board_nand_init(struct nand_chip *lpc32xx_chip) * is strictly 32-bit aligned. */ lpc32xx_chip->read_buf = lpc32xx_read_buf; - lpc32xx_chip->read_byte = lpc32xx_read_byte; lpc32xx_chip->write_buf = lpc32xx_write_buf; - lpc32xx_chip->write_byte = lpc32xx_write_byte; /* * Use default ECC layout, but these values are predefined * for both small and large page NAND flash devices. */ - lpc32xx_chip->ecc.size = 256; - lpc32xx_chip->ecc.bytes = 3; + lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE; + lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; +#endif + lpc32xx_chip->ecc.strength = 1; #if defined(CONFIG_SYS_NAND_USE_FLASH_BBT) -- 1.8.3.1

3 3

[U-Boot] u-boot FIT image support
by York Sun 10 Aug '15

10 Aug '15

Simon, I was doing an experiment to put the load address and entry address of Linux to higher than 32-bit address. I found it is broken to process more than 32-bit addresses. When I attempted to fix it, I was troubled by those code used for both host and target, like common/image-fit.c. For example, to process 64-bit address, the function int fit_image_get_load(const void *fit, int noffset, ulong *load) should be converted to int fit_image_get_load(const void *fit, int noffset, uint64_t *load) ulong is 64-bit for 64-bit target such as ARMv8, but it can be 32-bit on host. If I use uint64_t, all related code in bootm and others need to change. Before I go too far, I'd like to check if anyone has tried to enable this in FIT image. #address-cells = <2>; I can try to use uint64_t in place of ulong for all related code if that's right. That will be a lot of change. York

2 4

[U-Boot] [PATCH v2 0/9] dfu: tftp: update: Support for DFU upgrades via ETH (TFTP)
by Lukasz Majewski 10 Aug '15

10 Aug '15

This commit series enables DFU subsystem to use ETH and TFTP protocol as a medium for downloading data, which should bring substantial speedup for writing large files (like rootfs). Please read provided ./doc/README.dfutftp documentation entry for more information. Those patches should be applied on the u-boot-dfu tree: SHA1: 09e46b733a9b02d10d3d29001c316dc937fe6b44 Lukasz Majewski (9): doc: dfu: tftp: README entry for TFTP extension of DFU net: tftp: Move tftp.h file from ./net to ./include/net tftp: update: Allow some parts of the code to be reused when CONFIG_SYS_NO_FLASH is set dfu: tftp: update: Provide tftp support for the DFU subsystem dfu: tftp: update: Add dfu_write_from_mem_addr() function update: tftp: dfu: Extend update_tftp() function to support DFU dfu: command: Extend "dfu" command to handle receiving data via TFTP config: bbb: Configs necessary for running update via TFTP on Beagle Bone Black dfu:tests: Modify dfu_gadget_test.sh to accept USB device major:minor number common/Makefile | 1 + common/cmd_dfu.c | 25 ++++++++++ common/cmd_fitupd.c | 2 +- common/main.c | 2 +- common/update.c | 51 +++++++++++++------ doc/README.dfutftp | 113 +++++++++++++++++++++++++++++++++++++++++++ drivers/dfu/Makefile | 1 + drivers/dfu/dfu.c | 48 ++++++++++++++++++ drivers/dfu/dfu_tftp.c | 65 +++++++++++++++++++++++++ include/configs/am335x_evm.h | 8 +++ include/dfu.h | 14 ++++++ include/net.h | 2 +- include/net/tftp.h | 30 ++++++++++++ net/bootp.c | 2 +- net/net.c | 2 +- net/rarp.c | 2 +- net/tftp.c | 2 +- net/tftp.h | 30 ------------ test/dfu/README | 9 +++- test/dfu/dfu_gadget_test.sh | 18 ++++--- 20 files changed, 366 insertions(+), 61 deletions(-) create mode 100644 doc/README.dfutftp create mode 100644 drivers/dfu/dfu_tftp.c create mode 100644 include/net/tftp.h delete mode 100644 net/tftp.h -- 2.1.4

4 31

[U-Boot] [PATCH 0/5] x86: Move x86 to use board_init_f_mem() instead of assembler
by Simon Glass 10 Aug '15

10 Aug '15

Much of the early-init assembler on x86 can be removed if we use the new board_init_f_mem() function. At present only PowerPC uses it, but we should try to move more archs over. This has been contemplated for a while but it is time to take the plunge. Simon Glass (5): x86: Remove init_gd() function Align global_data to a 16-byte boundary Allow arch-specific setting of global_data in board_init_f_mem() x86: Move the GDT into global_data x86: Switch to using generic global_data setup arch/x86/cpu/cpu.c | 11 +++-- arch/x86/cpu/start.S | 86 +++++--------------------------------- arch/x86/include/asm/global_data.h | 4 +- arch/x86/include/asm/u-boot-x86.h | 1 - common/board_f.c | 19 ++++++--- include/asm-generic/global_data.h | 2 +- include/common.h | 40 ++++++++++++++++++ 7 files changed, 75 insertions(+), 88 deletions(-) -- 2.5.0.rc2.392.g76e840b

3 13

[U-Boot] [PATCH 1/2] gpio: Add DW APB GPIO driver
by Marek Vasut 10 Aug '15

10 Aug '15

Add driver for the DesignWare APB GPIO IP block. This driver is DM capable and probes from DT. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> --- drivers/gpio/Makefile | 1 + drivers/gpio/dwapb_gpio.c | 167 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 168 insertions(+) create mode 100644 drivers/gpio/dwapb_gpio.c diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 67c6374..603c96b 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -6,6 +6,7 @@ # ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o obj-$(CONFIG_AXP_GPIO) += axp_gpio.o endif obj-$(CONFIG_DM_GPIO) += gpio-uclass.o diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c new file mode 100644 index 0000000..cdb6e78 --- /dev/null +++ b/drivers/gpio/dwapb_gpio.c @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2015 Marek Vasut <marex(a)denx.de> + * + * DesignWare APB GPIO driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/root.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO_SWPORTA_DR 0x00 +#define GPIO_SWPORTA_DDR 0x04 +#define GPIO_INTEN 0x30 +#define GPIO_INTMASK 0x34 +#define GPIO_INTTYPE_LEVEL 0x38 +#define GPIO_INT_POLARITY 0x3c +#define GPIO_INTSTATUS 0x40 +#define GPIO_PORTA_DEBOUNCE 0x48 +#define GPIO_PORTA_EOI 0x4c +#define GPIO_EXT_PORTA 0x50 + +struct gpio_dwapb_platdata { + char name[24]; + int bank; + int pins; + fdt_addr_t base; +}; + +static int dwapb_gpio_direction_input(struct udevice *dev, unsigned pin) +{ + struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); + clrbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin); + return 0; +} + +static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin, + int val) +{ + struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); + + setbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin); + + if (val) + setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + else + clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + + return 0; +} + +static int dwapb_gpio_get_value(struct udevice *dev, unsigned pin) +{ + struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); + return !!(readl(plat->base + GPIO_EXT_PORTA) & (1 << pin)); +} + + +static int dwapb_gpio_set_value(struct udevice *dev, unsigned pin, int val) +{ + struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); + + if (val) + setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + else + clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + + return 0; +} + +static const struct dm_gpio_ops gpio_dwapb_ops = { + .direction_input = dwapb_gpio_direction_input, + .direction_output = dwapb_gpio_direction_output, + .get_value = dwapb_gpio_get_value, + .set_value = dwapb_gpio_set_value, +}; + +static int gpio_dwapb_probe(struct udevice *dev) +{ + struct gpio_dev_priv *priv = dev_get_uclass_priv(dev); + struct gpio_dwapb_platdata *plat = dev->platdata; + + if (!plat) + return 0; + + priv->gpio_count = plat->pins; + priv->bank_name = plat->name; + + return 0; +} + +static int gpio_dwapb_bind(struct udevice *dev) +{ + struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); + const void *blob = gd->fdt_blob; + struct udevice *subdev; + fdt_addr_t base; + int node, bank = 0; + const char *name; + + /* If this is a child device, there is nothing to do here */ + if (plat) + return 0; + + base = fdtdec_get_addr(blob, dev->of_offset, "reg"); + if (base == FDT_ADDR_T_NONE) { + debug("Can't get the GPIO register base address\n"); + return -ENXIO; + } + + name = fdt_get_name(blob, dev->of_offset, NULL); + + for (node = fdt_first_subnode(blob, dev->of_offset); + node > 0; + node = fdt_next_subnode(blob, node)) { + int ret; + + if (!fdtdec_get_bool(blob, node, "gpio-controller")) + continue; + + plat = NULL; + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + + plat->base = base; + plat->bank = bank; + plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0); + snprintf(plat->name, sizeof(plat->name) - 1, "%s-bank%i-", + name, bank); + + ret = device_bind(dev, dev->driver, plat->name, + plat, -1, &subdev); + if (ret) + return ret; + + subdev->of_offset = node; + bank++; + } + + + return 0; +} + +static const struct udevice_id gpio_dwapb_ids[] = { + { .compatible = "snps,dw-apb-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_dwapb) = { + .name = "gpio-dwapb", + .id = UCLASS_GPIO, + .of_match = gpio_dwapb_ids, + .ops = &gpio_dwapb_ops, + .bind = gpio_dwapb_bind, + .probe = gpio_dwapb_probe, +}; -- 2.1.4

2 14

[U-Boot] [RFC v2 PATCH 0/3] add pinctrl driver framework
by Masahiro Yamada 10 Aug '15

10 Aug '15

Sorry for delay. This is RFC v2. README.pinctrl is missing in this version (I will do it in the next version), but the code itself is almost ready for the review. This series depends on "Add macros to ease our life with independent CONFIGs between U-Boot and SPL", consists of 15 patches. Masahiro Yamada (3): pinctrl: add pin control uclass support pinctrl: add simple pinctrl implementation pinctrl: sandbox: add sandbox pinctrl driver arch/sandbox/dts/sandbox.dts | 19 +++ configs/sandbox_defconfig | 5 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/core/device.c | 4 + drivers/pinctrl/Kconfig | 53 ++++++ drivers/pinctrl/Makefile | 4 + drivers/pinctrl/pinctrl-generic.c | 351 ++++++++++++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl-sandbox.c | 157 +++++++++++++++++ drivers/pinctrl/pinctrl-uclass.c | 180 +++++++++++++++++++ include/dm/pinctrl.h | 220 ++++++++++++++++++++++++ include/dm/uclass-id.h | 2 + 12 files changed, 998 insertions(+) create mode 100644 drivers/pinctrl/Kconfig create mode 100644 drivers/pinctrl/Makefile create mode 100644 drivers/pinctrl/pinctrl-generic.c create mode 100644 drivers/pinctrl/pinctrl-sandbox.c create mode 100644 drivers/pinctrl/pinctrl-uclass.c create mode 100644 include/dm/pinctrl.h -- 1.9.1

1 3

[U-Boot] [PATCH v2] dm: serial: Add a REQUIRE_SERIAL_CONSOLE option for boards with no serial port
by Hans de Goede 10 Aug '15

10 Aug '15

Currently the serial code assumes that there is always at least one serial port (and panics / crashes due to null pointer dereferences when there is none). This makes it impossible to use u-boot on boards where there is no (debug) serial port, because e.g. all uart pins are muxed to another function. This commit adds a CONFIG_REQUIRE_SERIAL_CONSOLE Kconfig option, which defaults to y (preserving existing behavior), which can be set to n on such boards to make them work. This commit only implements this for CONFIG_DM_SERIAL=y configs, as allowing running without a serial port for CONFIG_DM_SERIAL=n configs is non trivial, and is not necessary at this moment. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- Changes in v2: -Fix some typos in the Kconfig description / help-text. --- drivers/serial/Kconfig | 11 +++++++++++ drivers/serial/serial-uclass.c | 20 +++++++++++++++++--- 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index fd126a8..a880eac 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -1,3 +1,14 @@ +config REQUIRE_SERIAL_CONSOLE + bool "Require a serial port for console" + # Running without a serial console is not supported by the + # non-dm serial code + depends on DM_SERIAL + default y + help + Require a serial port for the console, and panic if none is found + during serial port initialization (default y). Set this to n on + boards which have no debug serial port whatsoever. + config DM_SERIAL bool "Enable Driver Model for serial drivers" depends on DM diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index bbc366b..2a49697 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -78,7 +78,9 @@ static void serial_find_console_or_panic(void) #undef INDEX } +#ifdef CONFIG_REQUIRE_SERIAL_CONSOLE panic_str("No serial driver found"); +#endif } /* Called prior to relocation */ @@ -140,28 +142,40 @@ static int _serial_tstc(struct udevice *dev) void serial_putc(char ch) { - _serial_putc(gd->cur_serial_dev, ch); + if (gd->cur_serial_dev) + _serial_putc(gd->cur_serial_dev, ch); } void serial_puts(const char *str) { - _serial_puts(gd->cur_serial_dev, str); + if (gd->cur_serial_dev) + _serial_puts(gd->cur_serial_dev, str); } int serial_getc(void) { + if (!gd->cur_serial_dev) + return 0; + return _serial_getc(gd->cur_serial_dev); } int serial_tstc(void) { + if (!gd->cur_serial_dev) + return 0; + return _serial_tstc(gd->cur_serial_dev); } void serial_setbrg(void) { - struct dm_serial_ops *ops = serial_get_ops(gd->cur_serial_dev); + struct dm_serial_ops *ops; + + if (!gd->cur_serial_dev) + return; + ops = serial_get_ops(gd->cur_serial_dev); if (ops->setbrg) ops->setbrg(gd->cur_serial_dev, gd->baudrate); } -- 2.4.3

2 2

[U-Boot] [PATCH][v2] driver: misc: debug server: Update Error message
by Prabhakar Kushwaha 10 Aug '15

10 Aug '15

Append "debug server image" in error message to make more informative. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> Reviewed-by: Bhupesh Sharma <bhupesh.sharma(a)freescale.com> --- Changes for v2: Incorporated Bhuesh's review comments drivers/misc/fsl_debug_server.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/misc/fsl_debug_server.c b/drivers/misc/fsl_debug_server.c index 44cd9b9..a592891 100644 --- a/drivers/misc/fsl_debug_server.c +++ b/drivers/misc/fsl_debug_server.c @@ -60,29 +60,29 @@ int debug_server_parse_firmware_fit_image(const void **raw_image_addr, /* Check if Image is in FIT format */ format = genimg_get_format(fit_hdr); if (format != IMAGE_FORMAT_FIT) { - printf("Error! Not a FIT image\n"); + printf("Debug Server FW: Not a FIT image\n"); goto out_error; } if (!fit_check_format(fit_hdr)) { - printf("Error! Bad FIT image format\n"); + printf("Debug Server FW: Bad FIT image format\n"); goto out_error; } node_offset = fit_image_get_node(fit_hdr, uname); if (node_offset < 0) { - printf("Error! Can not find %s subimage\n", uname); + printf("Debug Server FW:Can not find %s subimage\n", uname); goto out_error; } /* Verify Debug Server firmware image */ if (!fit_image_verify(fit_hdr, node_offset)) { - printf("Error! Bad Debug Server firmware hash"); + printf("Debug Server FW: Bad Debug Server firmware hash"); goto out_error; } if (fit_get_desc(fit_hdr, node_offset, &desc) < 0) { - printf("Error! Failed to get Debug Server fw description"); + printf("Debug Server FW: Failed to get FW description"); goto out_error; } -- 1.9.1

1 0

[U-Boot] [PATCH 1/2] Tegra: clocks: Add 38.4MHz OSC support for T210 use
by Tom Warren 10 Aug '15

10 Aug '15

Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs to be measured - should be close to 700MHz (1.4G/2). Note that some freqs aren't in the PLLU table in T210 TRM (13, 26MHz), so I used the 12MHz table entry for them. They shouldn't be selected since they're not viable T210 OSC freqs. Since there are now 2 new OSC defines, all tables (pll_x_table, PLLU) had to increase by two entries, but since 38.4/48MHz are not viable osc freqs on T20/30/114, etc, they're just set to 0. Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- arch/arm/include/asm/arch-tegra/clock.h | 2 ++ arch/arm/mach-tegra/clock.c | 13 +++++++++---- arch/arm/mach-tegra/cpu.c | 12 ++++++++++++ arch/arm/mach-tegra/tegra210/clock.c | 8 ++++++-- drivers/usb/host/ehci-tegra.c | 18 +++++++++++++----- 5 files changed, 42 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index f9dd3c8..2274b14 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -16,6 +16,8 @@ enum clock_osc_freq { CLOCK_OSC_FREQ_19_2, CLOCK_OSC_FREQ_12_0, CLOCK_OSC_FREQ_26_0, + CLOCK_OSC_FREQ_38_4, + CLOCK_OSC_FREQ_48_0, CLOCK_OSC_FREQ_COUNT, }; diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 5d968d8..d0eebd2 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -44,6 +44,8 @@ static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = { 19200000, 12000000, 26000000, + 38400000, + 48000000, }; /* return 1 if a peripheral ID is in range */ @@ -620,17 +622,20 @@ int clock_verify(void) void clock_init(void) { + pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); - pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); + pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB); pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY); - pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); - pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); + pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; + pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); + debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]); + debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]); debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); - debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); + debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]); debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]); debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); } diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c index f7d45e8..b9391d6 100644 --- a/arch/arm/mach-tegra/cpu.c +++ b/arch/arm/mach-tegra/cpu.c @@ -67,6 +67,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ }, /* * T25: 1.2 GHz @@ -83,6 +85,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ }, /* * T30: 600 MHz @@ -99,6 +103,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */ }, /* * T114: 700 MHz @@ -114,6 +120,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ }, /* @@ -130,6 +138,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */ + { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */ }, /* @@ -146,6 +156,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/ { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/ + { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */ + { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */ }, }; diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 4e7d793..7ac2a06 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -649,8 +649,8 @@ enum clock_osc_freq clock_get_osc_freq(void) */ if (reg == 5) { debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg); - /* Map it to 19.2MHz for now. 38.4MHz OSC support TBD */ - return 1; + /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */ + return 4; } /* @@ -930,6 +930,10 @@ void clock_early_init(void) clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0); clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12); break; + case CLOCK_OSC_FREQ_38_4: + clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0); + clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0); + break; default: /* * These are not supported. It is too early to print a diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 0edd557..4a4f559 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -131,7 +131,9 @@ static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, - { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } + { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } }; static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { @@ -139,7 +141,9 @@ static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, - { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } + { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } }; static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { @@ -147,16 +151,20 @@ static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, - { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB } + { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 11 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } }; /* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */ static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */ - { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 32500, 5 }, { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 }, { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, - { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 }, + { 0x019, 0x02, 0x01, 0x0, 0, 0x05, 0x96, 0x18, 0x177, 96000, 15 }, + { 0x028, 0x04, 0x01, 0x0, 0, 0x04, 0x66, 0x09, 0xFE, 120000, 20 } }; /* UTMIP Idle Wait Delay */ -- 1.8.2.1.610.g562af5b

5 6

[U-Boot] [PATCH v6 3/5] nand: lpc32xx: add ECC layout for small page NAND
by slemieux.tyco＠gmail.com 10 Aug '15

10 Aug '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP. The code taken from the legacy patch is: - lpc32xx SLC NAND driver (ECC layout for small page) This layout is matching the lpc32xx NAND SLC Kernel driver: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/d… Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- Changes from v5 to v6: * Updated comment regarding default OOB layout. Changes from v4 to v5: * No changes; patch context updated. Changes from v3 to v4: * No changes. Changes from v2 to v3: * No changes; patch context updated. Changes from v1 to v2: * Move ECC layout for small page NAND into a separate patch. The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2) was downloaded from the LPCLinux Web site. drivers/mtd/nand/lpc32xx_nand_slc.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c index 2a32264..088818f 100644 --- a/drivers/mtd/nand/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/lpc32xx_nand_slc.c @@ -94,6 +94,19 @@ struct lpc32xx_nand_slc_regs { #define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4) #define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0) +/* NAND ECC Layout for small page NAND devices + * Note: For large page devices, the default layouts are used. */ +static struct nand_ecclayout lpc32xx_nand_oob_16 = { + .eccbytes = 6, + .eccpos = {10, 11, 12, 13, 14, 15}, + .oobfree = { + {.offset = 0, + . length = 4}, + {.offset = 6, + . length = 4} + } +}; + #if defined(CONFIG_DMA_LPC32XX) /* Total ECC bytes and size; refer to board_nand_init() for details. */ #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) @@ -530,7 +543,7 @@ int board_nand_init(struct nand_chip *lpc32xx_chip) lpc32xx_chip->write_buf = lpc32xx_write_buf; /* - * Use default ECC layout, but these values are predefined + * These values are predefined * for both small and large page NAND flash devices. */ lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE; @@ -539,6 +552,9 @@ int board_nand_init(struct nand_chip *lpc32xx_chip) lpc32xx_chip->ecc.strength = 1; + if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE) + lpc32xx_chip->ecc.layout = &lpc32xx_nand_oob_16; + #if defined(CONFIG_SYS_NAND_USE_FLASH_BBT) lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH; #endif -- 1.8.3.1

1 0