August 2015 - U-Boot

[U-Boot] [PATCH] dm: serial: Add a REQUIRE_SERIAL_CONSOLE option for boards with no serial port
by Hans de Goede 06 Aug '15

06 Aug '15

Currently the serial code assumes that there is always at least one serial port (and panics / crashes due to null pointer dereferences when there is none). This makes it impossible to use u-boot on boards where there is no (debug) serial port, because e.g. all uart pins are muxed to another function. This commit adds a CONFIG_REQUIRE_SERIAL_CONSOLE Kconfig option, which defaults to y (preserving existing behavior), which can be set to n on such boards to make them work. This commit only implements this for CONFIG_DM_SERIAL=y configs, as allowing running without a serial port for CONFIG_DM_SERIAL=n configs is non trivial, and is not necessary at this moment. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- drivers/serial/Kconfig | 11 +++++++++++ drivers/serial/serial-uclass.c | 20 +++++++++++++++++--- 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 4829284..89d01d5 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -1,3 +1,14 @@ +config REQUIRE_SERIAL_CONSOLE + bool "Require a serial port for console" + # Running without a serial console is not supported by the + # non dm serial code + depends on DM_SERIAL + default y + help + Require a serial port for the console, and panic of none is found + during serial port initialization (default y). Set this to n on + boards which have no debug serial port what so ever. + config DM_SERIAL bool "Enable Driver Model for serial drivers" depends on DM diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 815fec3..df0f183 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -78,7 +78,9 @@ static void serial_find_console_or_panic(void) #undef INDEX } +#ifdef CONFIG_REQUIRE_SERIAL_CONSOLE panic_str("No serial driver found"); +#endif } /* Called prior to relocation */ @@ -140,28 +142,40 @@ static int _serial_tstc(struct udevice *dev) void serial_putc(char ch) { - _serial_putc(gd->cur_serial_dev, ch); + if (gd->cur_serial_dev) + _serial_putc(gd->cur_serial_dev, ch); } void serial_puts(const char *str) { - _serial_puts(gd->cur_serial_dev, str); + if (gd->cur_serial_dev) + _serial_puts(gd->cur_serial_dev, str); } int serial_getc(void) { + if (!gd->cur_serial_dev) + return 0; + return _serial_getc(gd->cur_serial_dev); } int serial_tstc(void) { + if (!gd->cur_serial_dev) + return 0; + return _serial_tstc(gd->cur_serial_dev); } void serial_setbrg(void) { - struct dm_serial_ops *ops = serial_get_ops(gd->cur_serial_dev); + struct dm_serial_ops *ops; + + if (!gd->cur_serial_dev) + return; + ops = serial_get_ops(gd->cur_serial_dev); if (ops->setbrg) ops->setbrg(gd->cur_serial_dev, gd->baudrate); } -- 2.4.3

2 3

[U-Boot] [PATCH v5 5/5] usb: lpc32xx: add host USB driver
by slemieux.tyco＠gmail.com 06 Aug '15

06 Aug '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Incorporate USB driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx USB driver - lpc3250 header file USB registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- Changes from v4 to v5: * Addressed Marek's comments on LPC32xx USB driver: - update "wait_for_bit()" implementation to use "get_timer()". - use return value of "wait_for_bit()" instead of returning -1. * Updated multiline comments style. Changes from v3 to v4: * Addressed Marek's comments on LPC32xx USB driver: - use same "wait_for_bit()" implementation as drivers/usb/host/dwc2.c - use a const variable to define a mask to make the code more clear to read. * Fixed legacy USB driver; use "otg_clk_sts" register to verify clock status instead of control register. Changes from v2 to v3: * Addressed Marek's comments on LPC32xx USB driver: - use "get_timer()" to handle timeout (usbpll_setup). - submit i2c driver update into a separate patch. - use "u32" for 4 bytes registers definition. - Move pin mux code to setup file (i.e. "device.c"). * Updated ISP1301 register definition (set & clear) instead of using an extra mask for the clear address. Changes from v1 to v2: * Addressed Marek's comments on LPC32xx USB driver: - use "get_timer()" to handle timeout. - Split USB and I2C driver. * Updated LPC32xx I2C driver to support the I2C that is part of the USB module. * Removed ISP1301 USB transceiver I2C registers definition that are not used. * Use "cpu" initialization & stop functions API instead of the "board" API. Update to the legacy driver to integrate with the latest u-boot: 1) Fixed checkpatch script output in legacy code. 2) Use LPC32xx definition from "cpu.h" and "clk.h". 3) Incorporate USB specific register definition from "lpc3250.h" header file from legacy BSP patch from LPCLinux. 4) Use u-boot API for register access to remove the volatile in register definition taken from "lpc3250.h" header file. 5) Update driver for latest u-boot USB API. 6) Use the peripheral clock to compute the I2C divider. The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2) was downloaded from the LPCLinux Web site. arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 + arch/arm/include/asm/arch-lpc32xx/clk.h | 12 ++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ohci-lpc32xx.c | 250 ++++++++++++++++++++++++++ 5 files changed, 270 insertions(+) create mode 100644 drivers/usb/host/ohci-lpc32xx.c diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index 0d2ef7a..3da0952 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -82,6 +82,12 @@ void lpc32xx_i2c_init(unsigned int devnum) writel(ctrl, &clk->i2cclk_ctrl); } +void lpc32xx_usb_init(void) +{ + /* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */ + clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE); +} + U_BOOT_DEVICE(lpc32xx_gpios) = { .name = "gpio_lpc32xx" }; diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 663f6bc..d21310e 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -167,6 +167,18 @@ struct clk_pm_regs { /* SDRAMCLK register bits */ #define CLK_SDRAM_DDR_SEL (1 << 1) +/* USB control register definitions */ +#define CLK_USBCTRL_PLL_STS (1 << 0) +#define CLK_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1) +#define CLK_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11) +#define CLK_USBCTRL_PLL_PWRUP (1 << 16) +#define CLK_USBCTRL_CLK_EN1 (1 << 17) +#define CLK_USBCTRL_CLK_EN2 (1 << 18) +#define CLK_USBCTRL_BUS_KEEPER (0x1 << 19) +#define CLK_USBCTRL_USBHSTND_EN (1 << 21) +#define CLK_USBCTRL_USBDVND_EN (1 << 22) +#define CLK_USBCTRL_HCLK_EN (1 << 24) + unsigned int get_sys_clk_rate(void); unsigned int get_hclk_pll_rate(void); unsigned int get_hclk_clk_div(void); diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index 7f997d9..ca7790a 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -14,6 +14,7 @@ void lpc32xx_mac_init(void); void lpc32xx_mlc_nand_init(void); void lpc32xx_slc_nand_init(void); void lpc32xx_dma_init(void); +void lpc32xx_usb_init(void); void lpc32xx_i2c_init(unsigned int devnum); void lpc32xx_ssp_init(void); #if defined(CONFIG_SPL_BUILD) diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 4d35d3e..9dfdc94 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o obj-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o +obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o # echi obj-$(CONFIG_USB_EHCI) += ehci-hcd.o diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c new file mode 100644 index 0000000..4ef1867 --- /dev/null +++ b/drivers/usb/host/ohci-lpc32xx.c @@ -0,0 +1,250 @@ +/* + * Copyright (C) 2008-2015 by NXP Semiconductors + * All rights reserved. + * + * @Author: Based on code by Kevin Wells + * @Descr: USB driver - Embedded Artists LPC3250 OEM Board support functions + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <usb.h> +#include <i2c.h> + +/* + * Notes: + * + * Only bitfield masks/values which are actually used by the driver + * are defined. + */ + +/* OTG I2C controller module register structures */ +struct otgi2c_regs { + u32 otg_i2c_txrx; /* OTG I2C Tx/Rx Data FIFO */ + u32 otg_i2c_stat; /* OTG I2C Status Register */ + u32 otg_i2c_ctrl; /* OTG I2C Control Register */ + u32 otg_i2c_clk_hi; /* OTG I2C Clock Divider high */ + u32 otg_i2c_clk_lo; /* OTG I2C Clock Divider low */ +}; + +/* OTG controller module register structures */ +struct otg_regs { + u32 reserved1[64]; + u32 otg_int_sts; /* OTG int status register */ + u32 otg_int_enab; /* OTG int enable register */ + u32 otg_int_set; /* OTG int set register */ + u32 otg_int_clr; /* OTG int clear register */ + u32 otg_sts_ctrl; /* OTG status/control register */ + u32 otg_timer; /* OTG timer register */ + u32 reserved2[122]; + struct otgi2c_regs otg_i2c; + u32 reserved3[824]; + u32 otg_clk_ctrl; /* OTG clock control reg */ + u32 otg_clk_sts; /* OTG clock status reg */ +}; + +/* otg_sts_ctrl register definitions */ +#define OTG_HOST_EN (1 << 0) /* Enable host mode */ + +/* otg_clk_ctrl and otg_clk_sts register definitions */ +#define OTG_CLK_AHB_EN (1 << 4) /* Enable AHB clock */ +#define OTG_CLK_OTG_EN (1 << 3) /* Enable OTG clock */ +#define OTG_CLK_I2C_EN (1 << 2) /* Enable I2C clock */ +#define OTG_CLK_HOST_EN (1 << 0) /* Enable host clock */ + +/* ISP1301 USB transceiver I2C registers */ +#define MC1_SPEED_REG (1 << 0) +#define MC1_DAT_SE0 (1 << 2) +#define MC1_UART_EN (1 << 6) + +#define MC2_SPD_SUSP_CTRL (1 << 1) +#define MC2_BI_DI (1 << 2) +#define MC2_PSW_EN (1 << 6) + +#define OTG1_DP_PULLUP (1 << 0) +#define OTG1_DM_PULLUP (1 << 1) +#define OTG1_DP_PULLDOWN (1 << 2) +#define OTG1_DM_PULLDOWN (1 << 3) +#define OTG1_VBUS_DRV (1 << 5) + +#define ISP1301_I2C_ADDR CONFIG_USB_ISP1301_I2C_ADDR + +#define ISP1301_I2C_MODE_CONTROL_1_SET 0x04 +#define ISP1301_I2C_MODE_CONTROL_1_CLR 0x05 +#define ISP1301_I2C_MODE_CONTROL_2_SET 0x12 +#define ISP1301_I2C_MODE_CONTROL_2_CLR 0x13 +#define ISP1301_I2C_OTG_CONTROL_1_SET 0x06 +#define ISP1301_I2C_OTG_CONTROL_1_CLR 0x07 +#define ISP1301_I2C_INTERRUPT_LATCH_CLR 0x0B +#define ISP1301_I2C_INTERRUPT_FALLING_CLR 0x0D +#define ISP1301_I2C_INTERRUPT_RISING_CLR 0x0F + +static struct otg_regs *otg = (struct otg_regs *)USB_BASE; +static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE; + +static int wait_for_bit(void *reg, const u32 mask, bool set) +{ + u32 val; + unsigned long start = get_timer(0); + + while (1) { + val = readl(reg); + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + if (get_timer(start) > 1000) + break; + + udelay(1); + } + + debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", + __func__, reg, mask, set); + + return -ETIMEDOUT; +} + +static int isp1301_set_value(int reg, u8 value) +{ + return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1); +} + +static void isp1301_configure(void) +{ + i2c_set_bus_num(I2C_2); + + /* + * LPC32XX only supports DAT_SE0 USB mode + * This sequence is important + */ + + /* Disable transparent UART mode first */ + isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN); + + isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG); + isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG); + isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_CLR, ~0); + isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_SET, + MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL); + + isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR, ~0); + isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0); + isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, + OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN); + isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR, + OTG1_DM_PULLUP | OTG1_DP_PULLUP); + isp1301_set_value(ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0); + isp1301_set_value(ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0); + isp1301_set_value(ISP1301_I2C_INTERRUPT_RISING_CLR, ~0); + + /* Enable usb_need_clk clock after transceiver is initialized */ + setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN); +} + +static int usbpll_setup(void) +{ + u32 ret; + + /* make sure clocks are disabled */ + clrbits_le32(&clk_pwr->usb_ctrl, + CLK_USBCTRL_CLK_EN1 | CLK_USBCTRL_CLK_EN2); + + /* start PLL clock input */ + setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN1); + + /* Setup PLL. */ + setbits_le32(&clk_pwr->usb_ctrl, + CLK_USBCTRL_FDBK_PLUS1(192 - 1)); + setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01)); + setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP); + + ret = wait_for_bit(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS, 1); + if (ret) + return ret; + + /* enable PLL output */ + setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN2); + + return 0; +} + +int usb_cpu_init(void) +{ + unsigned long start; + u32 ret; + + /* + * USB pins routing setup is done by "lpc32xx_usb_init()" and should + * be call by board "board_init()" or "misc_init_r()" functions. + */ + + /* enable AHB slave USB clock */ + setbits_le32(&clk_pwr->usb_ctrl, + CLK_USBCTRL_HCLK_EN | CLK_USBCTRL_BUS_KEEPER); + + /* enable I2C clock in OTG block if it isn't */ + if ((readl(&otg->otg_clk_sts) & OTG_CLK_I2C_EN) != OTG_CLK_I2C_EN) { + writel(OTG_CLK_I2C_EN, &otg->otg_clk_ctrl); + + start = get_timer(0); + while (1) { + if (readl(&otg->otg_clk_sts) == OTG_CLK_I2C_EN) + break; + + if (get_timer(start) > 100) + return -1; + + udelay(1); + } + } + + /* Configure ISP1301 */ + isp1301_configure(); + + /* setup USB clocks and PLL */ + ret = usbpll_setup(); + if (ret) + return ret; + + /* enable usb_host_need_clk */ + setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBHSTND_EN); + + /* enable all needed USB clocks */ + const u32 mask = OTG_CLK_AHB_EN | OTG_CLK_OTG_EN | + OTG_CLK_I2C_EN | OTG_CLK_HOST_EN; + writel(mask, &otg->otg_clk_ctrl); + + ret = wait_for_bit(&otg->otg_clk_sts, mask, 1); + if (ret) + return ret; + + setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); + isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV); + + return 0; +} + +int usb_cpu_stop(void) +{ + /* vbus off */ + isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV); + + clrbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); + + clrbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_HCLK_EN); + + return 0; +} + +int usb_cpu_init_fail(void) +{ + return usb_cpu_stop(); +} -- 1.8.3.1

4 5

[U-Boot] [PATCH] ti_armv7_common: enable setexpr
by Nishanth Menon 06 Aug '15

06 Aug '15

This allows us to do basic math in hush shell. For example: U-Boot# r1=10 U-Boot# r2=20 U-Boot# setexpr.l r3 $r1 + $r2 U-Boot# echo $r3 30 Reported-by: Vitaly Andrianov <vitalya(a)ti.com> Suggested-by: Tom Rini <trini(a)ti.com> Signed-off-by: Nishanth Menon <nm(a)ti.com> --- include/configs/ti_armv7_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 5a4fd2d5552f..d9cd90002ca7 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -115,6 +115,7 @@ #define CONFIG_SYS_MALLOC_LEN (16 << 20) #endif #define CONFIG_SYS_HUSH_PARSER +#define CONFIG_CMD_SETEXPR #define CONFIG_SYS_PROMPT "U-Boot# " #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_BAUDRATE 115200 -- 2.1.4

3 4

[U-Boot] [PATCH 0/2] ARM: tegra: enable GPU DT node
by Alexandre Courbot 06 Aug '15

06 Aug '15

Tegra124 requires the bootloader to perform VPR initialization, otherwise the GPU cannot be used by the system. Since using the GPU without that initialization results in a hang, the GPU DT node is left disabled, and it is the task of the bootloader to enable it after ensuring it is safe to use the GPU. VPR init is already performed since patch df3443dfa449, but the device tree was left untouched. This patch series performs this last step and prepares the GPU intialization code to receive more code for newer chips. Patch 1 of this series moves the GPU initialization code to a more generic place, since newer chips like T210 require extra steps to initialize the GPU (e.g. WPR setup). It also performs VPR initialization at a later time of the bootloader life, so that we can check the status variable right before booting the kernel and patch the DT accordingly. Patch 2 performs the DT patching using the ft_board_setup() hook. Alexandre Courbot (2): ARM: tegra: move VPR configuration to a later stage ARM: tegra: enable GPU DT node when appropriate arch/arm/include/asm/arch-tegra/ap.h | 9 ----- arch/arm/include/asm/arch-tegra/gpu.h | 43 +++++++++++++++++++++++ arch/arm/mach-tegra/Makefile | 2 +- arch/arm/mach-tegra/ap.c | 3 -- arch/arm/mach-tegra/board2.c | 3 ++ arch/arm/mach-tegra/gpu.c | 66 +++++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/vpr.c | 35 ------------------- board/nvidia/jetson-tk1/jetson-tk1.c | 8 +++++ board/nvidia/venice2/venice2.c | 8 +++++ include/configs/jetson-tk1.h | 2 ++ include/configs/tegra124-common.h | 3 ++ include/configs/venice2.h | 2 ++ 12 files changed, 136 insertions(+), 48 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra/gpu.h create mode 100644 arch/arm/mach-tegra/gpu.c delete mode 100644 arch/arm/mach-tegra/vpr.c -- 2.4.4

5 12

[U-Boot] [PATCH] x86: WIP: Enable D0 stepping microcode for MinnowMax
by Bin Meng 06 Aug '15

06 Aug '15

This is a temparory hacking for testing U-Boot on a newer version MinnowMax board. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/dts/minnowmax.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 7103bc5..9e1fcfc 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -101,7 +101,7 @@ microcode { update@0 { -#include "microcode/m0130673322.dtsi" +#include "microcode/m0130679901.dtsi" }; }; -- 1.8.2.1

3 12

[U-Boot] [PATCH v1] arm: omap5: Add AMP boot support for OMAP5
by Bharat Gohil 06 Aug '15

06 Aug '15

This command uses AMP boot mode to boot the omap5 device. it is used to run two different software on each dedicated core without using hypervisor. A typical example is: Core0 uses Linux or Android and Core1 uses QNX or baremetal app. It is also used for benchmarking the hypervisor performance where hypervisor is run in the SMP mode and runs two different operating systems or baremetal app on top of it. Signed-off-by: Bharat Gohil <ghl.bhrt(a)gmail.com> Cc: Tom Rini <trini(a)ti.com> --- arch/arm/include/asm/arch-omap5/hardware.h | 5 +++ common/Kconfig | 6 +++ common/Makefile | 1 + common/cmd_omap5_ampboot.c | 59 ++++++++++++++++++++++++++++++ configs/dra7xx_evm_defconfig | 3 ++ 5 files changed, 74 insertions(+) create mode 100644 common/cmd_omap5_ampboot.c diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h index f7011b4..540d9c3 100644 --- a/arch/arm/include/asm/arch-omap5/hardware.h +++ b/arch/arm/include/asm/arch-omap5/hardware.h @@ -23,4 +23,9 @@ /* GPMC Base address */ #define GPMC_BASE 0x50000000 +/* Secondary core control registers */ +#define AUXCORE_BOOT1 0x48281804 +#define AUXCORE_BOOT0 0x48281800 + + #endif diff --git a/common/Kconfig b/common/Kconfig index 40cd69e..fbb0353 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -474,6 +474,12 @@ config CMD_SOUND sound init - set up sound system sound play - play a sound +config CMD_OMAP5_AMPBOOT + bool "omap5 ampboot" + depends on OMAP54XX + help + This command start secondary core1 from dual CoretexA15 omap5. + endmenu menu "Boot timing" diff --git a/common/Makefile b/common/Makefile index d6c1d48..0734dd9 100644 --- a/common/Makefile +++ b/common/Makefile @@ -264,6 +264,7 @@ obj-$(CONFIG_FIT_SIGNATURE) += image-sig.o obj-$(CONFIG_IO_TRACE) += iotrace.o obj-y += memsize.o obj-y += stdio.o +obj-$(CONFIG_CMD_OMAP5_AMPBOOT) += cmd_omap5_ampboot.o # This option is not just y/n - it can have a numeric value ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV diff --git a/common/cmd_omap5_ampboot.c b/common/cmd_omap5_ampboot.c new file mode 100644 index 0000000..212a815 --- /dev/null +++ b/common/cmd_omap5_ampboot.c @@ -0,0 +1,59 @@ +/* + * cmd_omap5_ampboot.c + * + * Copyright (c) 2015 Bharat Gohil (ghl.bhrt(a)gmail.com). + * + * Licensed under the GPL-2 or later. + */ + +/* This command uses AMP boot mode to boot the omap5 device. it is used to run +* two different software on each dedicated core without using hypervisor. +* A typical example is: Core0 uses Linux or Android and Core1 uses QNX or + baremetal app. +* It is also used for benchmarking the hypervisor performance where +* hypervisor is run in the SMP mode and runs two different operating systems +* or baremetal app on top of it. +*/ + +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include <asm/hardware.h> + +static inline void dsb_sev(void) +{ + __asm__ __volatile__("dsb\n" + "sev\n" + "nop"); +} + +int ampboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + unsigned long addr; + char *endp; + + if (argc < 2) + return -1; + + addr = simple_strtoul(argv[1], &endp, 16); + if (*argv[1] == 0 || *endp != 0) + return -1; + + /* 'addr' is starting address of core1 in the dual ARM A15 sub-system */ + writel(addr, AUXCORE_BOOT1); + + /* 'AUXCORE_BOOT0' is a status register for core1. Writing a non-zero value + * to this register indicates that, AUXCORE_BOOT1 register has valid start + * address for core1 + */ + writel(0x20, AUXCORE_BOOT0); + + /* Kick secondary core1 */ + dsb_sev(); + + return 0; +} + +U_BOOT_CMD(ampboot, 2, 1, ampboot, + "ampboot <image address>", + "Start Core1 at specified address where binary image is stored"); + diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 463a7e2..af6f69d 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -7,5 +7,8 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set +CONFIG_CMD_MISC=y +# CONFIG_CMD_TIMER is not set +CONFIG_CMD_OMAP5_AMPBOOT=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -- 1.9.1

1 0

[U-Boot] [PATCH 01/13][v4] power: pmic: add pfuze3000 support
by Adrian Alonso 06 Aug '15

06 Aug '15

* Add pmic pfuze3000 support, implement power_pfuze3000_init to be used in power_init_board callback function. Signed-off-by: Adrian Alonso <aalonso(a)freescale.com> Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- Changes for V2: - Correct pfuze device name to pfuze3000; Freescale documentation uses Pfuze 3000 as product name for the pmic, align driver name with the actual product name. Changes for V3: Resend Changes for V4: Resend drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_pfuze3000.c | 32 +++++++++++++++ include/power/pfuze3000_pmic.h | 78 +++++++++++++++++++++++++++++++++++++ 3 files changed, 111 insertions(+) create mode 100644 drivers/power/pmic/pmic_pfuze3000.c create mode 100644 include/power/pfuze3000_pmic.h diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index ae86f04..b271acb 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o +obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o diff --git a/drivers/power/pmic/pmic_pfuze3000.c b/drivers/power/pmic/pmic_pfuze3000.c new file mode 100644 index 0000000..ac807a8 --- /dev/null +++ b/drivers/power/pmic/pmic_pfuze3000.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Peng Fan <Peng.Fan(a)freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> + +int power_pfuze3000_init(unsigned char bus) +{ + static const char name[] = "PFUZE3000"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = PMIC_NUM_OF_REGS; + p->hw.i2c.addr = CONFIG_POWER_PFUZE3000_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/include/power/pfuze3000_pmic.h b/include/power/pfuze3000_pmic.h new file mode 100644 index 0000000..e8b892b --- /dev/null +++ b/include/power/pfuze3000_pmic.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc + * Peng Fan <Peng.Fan(a)freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __PFUZE3000_PMIC_H_ +#define __PFUZE3000_PMIC_H_ + +/* PFUZE3000 registers */ +enum { + PFUZE3000_DEVICEID = 0x00, + + PFUZE3000_REVID = 0x03, + PFUZE3000_FABID = 0x04, + PFUZE3000_INTSTAT0 = 0x05, + PFUZE3000_INTMASK0 = 0x06, + PFUZE3000_INTSENSE0 = 0x07, + PFUZE3000_INTSTAT1 = 0x08, + PFUZE3000_INTMASK1 = 0x09, + PFUZE3000_INTSENSE1 = 0x0A, + + PFUZE3000_INTSTAT3 = 0x0E, + PFUZE3000_INTMASK3 = 0x0F, + PFUZE3000_INTSENSE3 = 0x10, + PFUZE3000_INTSTAT4 = 0x11, + PFUZE3000_INTMASK4 = 0x12, + PFUZE3000_INTSENSE4 = 0x13, + + PFUZE3000_COINCTL = 0x1A, + PFUZE3000_PWRCTL = 0x1B, + PFUZE3000_MEMA = 0x1C, + PFUZE3000_MEMB = 0x1D, + PFUZE3000_MEMC = 0x1E, + PFUZE3000_MEMD = 0x1F, + + PFUZE3000_SW1AVOLT = 0x20, + PFUZE3000_SW1ASTBY = 0x21, + PFUZE3000_SW1AOFF = 0x22, + PFUZE3000_SW1AMODE = 0x23, + PFUZE3000_SW1ACONF = 0x24, + + PFUZE3000_SW1BVOLT = 0x2E, + PFUZE3000_SW1BSTBY = 0x2F, + PFUZE3000_SW1BOFF = 0x30, + PFUZE3000_SW1BMODE = 0x31, + PFUZE3000_SW1BCONF = 0x32, + + PFUZE3000_SW2VOLT = 0x35, + PFUZE3000_SW2STBY = 0x36, + PFUZE3000_SW2OFF = 0x37, + PFUZE3000_SW2MODE = 0x38, + PFUZE3000_SW2CONF = 0x39, + + PFUZE3000_SW3VOLT = 0x3C, + PFUZE3000_SW3STBY = 0x3D, + PFUZE3000_SW3OFF = 0x3E, + PFUZE3000_SW3MODE = 0x3F, + PFUZE3000_SW3CONF = 0x40, + + PFUZE3000_SWBSTCTL = 0x66, + + PFUZE3000_LDOGCTL = 0x69, + PFUZE3000_VREFDDRCTL = 0x6A, + PFUZE3000_VSNVSCTL = 0x6B, + PFUZE3000_VLDO1CTL = 0x6C, + PFUZE3000_VLDO2CTL = 0x6D, + PFUZE3000_VCC_SDCTL = 0x6E, + PFUZE3000_V33CTL = 0x6F, + PFUZE3000_VLDO3CTL = 0x70, + PFUZE3000_VLD4CTL = 0x71, + + PMIC_NUM_OF_REGS = 0x7F, +}; + +int power_pfuze3000_init(unsigned char bus); + +#endif -- 2.1.4

7 22

[U-Boot] [PATCH] board: Xilinx: zynqmp: Define checkboard() function
by Siva Durga Prasad Paladugu 06 Aug '15

06 Aug '15

Define checkboard() function for zynqMP Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- board/xilinx/zynqmp/zynqmp.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 0c9a814..70d9c2c 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -130,3 +130,10 @@ int board_late_init(void) return 0; } + +int checkboard(void) +{ + puts("Board:\tXilinx ZynqMP\n"); + return 0; +} + -- 1.7.1

2 1

[U-Boot] [PATCH v2 1/3] common: Display >=4GiB memory bank size
by Bin Meng 06 Aug '15

06 Aug '15

bd->bi_dram[] has both start address and size defined as 32-bit, which is not the case on some platforms where >=4GiB memory bank is used. Change them to support such memory banks. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - Drop patches which are already applied - Change start to phys_addr_t - Change debug output to either %016llx or %08lx common/board_f.c | 9 ++++++++- include/asm-generic/u-boot.h | 4 ++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/common/board_f.c b/common/board_f.c index 6d922b8..eb24f6c 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -206,7 +206,14 @@ static int show_dram_config(void) debug("\nRAM Configuration:\n"); for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { size += gd->bd->bi_dram[i].size; - debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); + + if (gd->bd->bi_dram[i].start >= 0x100000000ULL) { + debug("Bank #%d: %016llx ", i, + (unsigned long long)(gd->bd->bi_dram[i].start)); + } else { + debug("Bank #%d: %08lx ", i, + (unsigned long)(gd->bd->bi_dram[i].start)); + } #ifdef DEBUG print_size(gd->bd->bi_dram[i].size, "\n"); #endif diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index c918049..9f3351d 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -130,8 +130,8 @@ typedef struct bd_info { ulong bi_boot_params; /* where this board expects params */ #ifdef CONFIG_NR_DRAM_BANKS struct { /* RAM configuration */ - ulong start; - ulong size; + phys_addr_t start; + phys_size_t size; } bi_dram[CONFIG_NR_DRAM_BANKS]; #endif /* CONFIG_NR_DRAM_BANKS */ } bd_t; -- 1.8.2.1

1 1

[U-Boot] [PATCH] arm: mvebu/armada100: dram.c: Remove CONFIG_SYS_BOARD_DRAM_INIT
by Stefan Roese 06 Aug '15

06 Aug '15

CONFIG_SYS_BOARD_DRAM_INIT is not defined anywhere. So lets get rid of all references here. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- arch/arm/cpu/arm926ejs/armada100/dram.c | 2 -- arch/arm/mach-mvebu/dram.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c index 8d7c71f..f3b9a66 100644 --- a/arch/arm/cpu/arm926ejs/armada100/dram.c +++ b/arch/arm/cpu/arm926ejs/armada100/dram.c @@ -72,7 +72,6 @@ u32 armd1_sdram_size(int chip_sel) } } -#ifndef CONFIG_SYS_BOARD_DRAM_INIT int dram_init(void) { int i; @@ -113,4 +112,3 @@ void dram_init_banksize(void) { dram_init(); } -#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index db18791..7a5840c 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -93,7 +93,6 @@ void mvebu_sdram_size_adjust(enum memory_bank bank) mvebu_sdram_bs_set(bank, size); } -#ifndef CONFIG_SYS_BOARD_DRAM_INIT int dram_init(void) { int i; @@ -141,4 +140,3 @@ void dram_init_banksize(void) { dram_init(); } -#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ -- 2.4.8

1 0