August 2015 - U-Boot

[U-Boot] [PATCH v3 04/16] drivers/net/vsc9953: Fix missing reserved register
by Codrin Ciubotariu 19 Aug '15

19 Aug '15

The VSC9953 DS reserves a register between vlan_mask and anag_efil registers. Signed-off-by: Johnson Leung <johnson.leung(a)freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu(a)freescale.com> --- Changes for v2: - removed Change-id field; Changes for v3: - added signature; include/vsc9953.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/vsc9953.h b/include/vsc9953.h index 6ae5fec..8ff02c1 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -143,6 +143,7 @@ struct vsc9953_ana_ana_tables { struct vsc9953_ana_ana { u32 adv_learn; u32 vlan_mask; + u32 reserved; u32 anag_efil; u32 an_events; u32 storm_limit_burst; -- 1.9.3

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[U-Boot] [PATCH v2 0/5] ti: usb (dwc3) peripheral mode fixes
by Kishon Vijay Abraham I 19 Aug '15

19 Aug '15

Patch series enables the 2nd PHY present in DRA7 SoC so that the 2nd instance of USB DWC3 can be used in peripheral mode. It also contains minor fixes and cleanups. Changes from v1: Added reviewed-by and acked-by I got for the previous version This patch series is split from [1] to contain only fixes specific to TI platforms. [1] -> http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/229188 Kishon Vijay Abraham I (5): usb: dwc3: dwc3-omap: Use the clear register inorder to clear the interrupts ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2 TI PHY: Add support to control 2nd USB PHY in DRA7xx/AM57xx board: ti: remove duplicate initialization of vbus_id_status include: configs: am43xx_evm: add 'usb stop' in usbboot env arch/arm/cpu/armv7/omap5/hw_data.c | 16 +++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 2 ++ arch/arm/include/asm/arch-omap5/clock.h | 3 ++ arch/arm/include/asm/omap_common.h | 2 ++ board/ti/am43xx/board.c | 2 -- board/ti/dra7xx/evm.c | 2 -- drivers/usb/dwc3/dwc3-omap.c | 46 +++++++++++++++++++------------ drivers/usb/dwc3/ti_usb_phy.c | 15 +++++++--- include/configs/am43xx_evm.h | 2 ++ 9 files changed, 64 insertions(+), 26 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH 1/3] arm: socfpga: Fix SD/MMC boot on ArriaV SoCDK
by Marek Vasut 19 Aug '15

19 Aug '15

Add the missing DT nodes, so that ArriaV SoCDK can boot from SD card. The SD card must be in slot J5 and BSEL must be 0x5. Signed-off-by: Marek Vasut <marex(a)denx.de> --- arch/arm/dts/socfpga_arria5_socdk.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index f2b5963..7d1836e 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -33,6 +33,10 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + soc { + u-boot,dm-pre-reloc; + }; }; &gmac1 { @@ -67,6 +71,8 @@ &mmc0 { vmmc-supply = <&regulator_3_3v>; vqmmc-supply = <&regulator_3_3v>; + bus-width = <4>; + u-boot,dm-pre-reloc; }; &usb1 { -- 2.1.4

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[U-Boot] [PATCH 1/3] zynqmp: usb: Add usb dwc3 driver support for zynqmp
by Siva Durga Prasad Paladugu 19 Aug '15

19 Aug '15

Added usb dwc3 driver support for zynqmp this also supports the DFU and LTHOR to download the linux images on to RAM and cen be booted from those linux images. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- arch/arm/cpu/armv8/zynqmp/Kconfig | 3 ++ arch/arm/include/asm/arch-zynqmp/hardware.h | 3 ++ board/xilinx/zynqmp/zynqmp.c | 27 +++++++++++++++++ configs/xilinx_zynqmp_ep_defconfig | 1 + include/configs/xilinx_zynqmp.h | 41 +++++++++++++++++++++++++- 5 files changed, 73 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index c8fcfb6..9a19dfa 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -20,4 +20,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP +config ZYNQMP_USB + bool "Configure ZynqMP USB" + endif diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 7640eab..8c041c0 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -27,6 +27,9 @@ #define ZYNQMP_SATA_BASEADDR 0xFD0C0000 +#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 +#define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000 + #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 70d9c2c..d105bb4 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -12,6 +12,8 @@ #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <usb.h> +#include <dwc3-uboot.h> DECLARE_GLOBAL_DATA_PTR; @@ -137,3 +139,28 @@ int checkboard(void) return 0; } +#ifdef CONFIG_USB_DWC3 +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_HIGH, + .base = ZYNQMP_USB0_XHCI_BASEADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, +}; + +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + return dwc3_uboot_init(&dwc3_device_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + dwc3_uboot_exit(index); + return 0; +} +#endif diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index fda44ea..efc1bbe 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -16,3 +16,4 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep" CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_ZYNQMP_USB=y diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 68853b6..927c917 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -49,7 +49,7 @@ #define COUNTER_FREQUENCY 4000000 /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x400000) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x2000000) /* Serial setup */ #if defined(CONFIG_ZYNQMP_DCC) @@ -108,13 +108,50 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR 0x8000000 +#if defined(CONFIG_ZYNQMP_USB) +#define CONFIG_USB_DWC3 +#define CONFIG_USB_DWC3_GADGET + +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000 +#define DFU_DEFAULT_POLL_TIMEOUT 300 +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_RAM +#define CONFIG_G_DNL_VENDOR_NUM 0x03FD +#define CONFIG_G_DNL_PRODUCT_NUM 0x0300 +#define CONFIG_G_DNL_MANUFACTURER "Xilinx" +#define CONFIG_USB_CABLE_CHECK +#define CONFIG_CMD_DFU +#define CONFIG_CMD_THOR_DOWNLOAD +#define CONFIG_THOR_FUNCTION +#define CONFIG_THOR_RESET_OFF +#define DFU_ALT_INFO_RAM \ + "dfu_ram_info=" \ + "set dfu_alt_info " \ + "Image ram 0x200000 0x1800000\\\\;" \ + "system.dtb ram 0x7000000 0x40000\0" \ + "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ + "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" + +#define DFU_ALT_INFO \ + DFU_ALT_INFO_RAM +#endif + +#if !defined(DFU_ALT_INFO) +# define DFU_ALT_INFO +#endif + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "kernel_addr=0x80000\0" \ "fdt_addr=0x7000000\0" \ "fdt_high=0x10000000\0" \ "sdboot=mmcinfo && load mmc 0:0 $fdt_addr system.dtb && " \ - "load mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0" + "load mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0" \ + DFU_ALT_INFO #define CONFIG_BOOTARGS "setenv bootargs console=ttyPS0,${baudrate} " \ "earlycon=cdns,mmio,0xff000000,${baudrate}n8" -- 1.7.1

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[U-Boot] [PATCH V2 00/10] Replace the FAT filesystem code
by Stephen Warren 19 Aug '15

19 Aug '15

The existing FAT filesystem implementation in U-Boot has some bugs that are tricky to fix cleanly without significant rework of the code. For example, see: http://lists.denx.de/pipermail/u-boot/2015-July/221054.html [PATCH] fat: handle paths that include ../ This series replaces U-Boot's FAT filesystem implementation with the "ff" project; http://elm-chan.org/fsw/ff/00index_e.html. This project appears to be actively maintained, does not have at least the bug referenced in the patch link above, and is quite easy to integrate into U-Boot. An earlier version is also used in Barebox, so presumably it's had some level of testing/exposure there. Note that this series is based on u-boot/master without the patch linked above applied. I wonder if it's a little risky to apply this series after -rc1; perhaps the patch above should be applied to v2015.10, and this series immediately after the release? v2: * buildman passes for everything it can build: * Implemented FAT functions used only by SPL code. * Fixed a warning in ff.c. * Fixed types in integer.h so that >64KiB files are loaded correctly. * ./test/fs/fs-test.sh passes. * Tested on a Raspberry Pi as well as sandbox. * Use a define for a hard-coded array size in ff-uboot.c. Binary size changes due to this series: * Text size increases around 1-6KiB depending on target. * Data size sometimes goes up, sometimes down, depending on target. * Nearly 200KiB of BSS is saved. Stephen Warren (10): disk: support host devices in dev_print() fat: move to a different directory fat: add ff.c implementation fat: apply upstream bugfix to ff.c fat: ff: add ifdef to avoid unused function warning fat: ffconf.h changes for U-Boot port fat: port integer.h to U-Boot types fat: add U-Boot to ff.c API conversion wrapper fat: switch to new FAT implementation fat: remove old implementation disk/part.c | 3 + fs/fat/Makefile | 8 +- fs/fat/diskio.h | 80 + fs/fat/fat.c | 1323 --------------- fs/fat/fat_write.c | 1115 ------------- fs/fat/ff-uboot.c | 403 +++++ fs/fat/ff.c | 4634 ++++++++++++++++++++++++++++++++++++++++++++++++++++ fs/fat/ff.h | 350 ++++ fs/fat/ffconf.h | 277 ++++ fs/fat/file.c | 183 --- fs/fat/integer.h | 35 + 11 files changed, 5784 insertions(+), 2627 deletions(-) create mode 100644 fs/fat/diskio.h delete mode 100644 fs/fat/fat.c delete mode 100644 fs/fat/fat_write.c create mode 100644 fs/fat/ff-uboot.c create mode 100644 fs/fat/ff.c create mode 100644 fs/fat/ff.h create mode 100644 fs/fat/ffconf.h delete mode 100644 fs/fat/file.c create mode 100644 fs/fat/integer.h -- 1.9.1

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[U-Boot] Question regarding CONFIG_DM_USB
by Suriyan Ramasami 19 Aug '15

19 Aug '15

Hi folks and Simon, After moving to the driver model for USB, I see that the call to board_usb_init() is not done anymore. This has the board specific initialisation sequence. It used to be called before the driver model existed by usb_lowlevel_init(). Without it, usb fails to work. I see that this call to board_usb_init() or something similar is missing (say in ehci-exynos.c or dwc2.c etc). My question is, where is the right place to plug this call in ? should it be part of the .probe ? Thanks - Suriyan

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[U-Boot] USB keyboard does not work on DWC2 controller (on Raspberry Pi B)
by Guillaume Gardet 19 Aug '15

19 Aug '15

Hi Stephen, I want to add USB keyboard support to raspberry pi but I get the following error when I do 'usb start' with a keyboard plugged-in: unable to get device descriptor (error=-22) Ethernet chip and mass storage devices are found. I found this thread from February: http://lists.denx.de/pipermail/u-boot/2015-February/206593.html which says: ********** This error is because the keyboard driver uses interrupt transfers, and these aren't implemented in DWC2 ********** But in April, you added a patch series including "usb: dwc2: implement interrupt transfers". But there is also a note: ********** With all these commits applied, both my USB keyboards (one LS Lenovo and one FS Dell) work correctly when there is no USB hub between the SoC and the keyboard; We still need split transactions to be implemented for hubs to work. ********** So, I guess this is expected that USB keyboard does not work on DWC2 / RPi B since it uses a USB hub (SMSC LAN9512)? Guillaume

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[U-Boot] [PATCH] ARM: atmel: switch to usb ehci for sama5d3 boards
by Josh Wu 19 Aug '15

19 Aug '15

From: Bo Shen <voice.shen(a)atmel.com> As the cache coherence issue in OHCI HCD, when enable I/D cache for sama5d3 SoC, the OHCI can not work properly. So, switch to EHCI, then the USB can work well. Signed-off-by: Bo Shen <voice.shen(a)atmel.com> [rebase to mainline] Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- include/configs/sama5d3_xplained.h | 21 +++------------------ include/configs/sama5d3xek.h | 21 +++------------------ 2 files changed, 6 insertions(+), 36 deletions(-) diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index bfd8aa7..0dab15d 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -20,17 +20,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_DBGU -/* - * This needs to be defined for the OHCI code to work but it is defined as - * ATMEL_ID_UHPHS in the CPU specific header files. - */ -#define ATMEL_ID_UHP ATMEL_ID_UHPHS - -/* - * Specify the clock enable bit in the PMC_SCER register. - */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS @@ -95,13 +84,9 @@ #define CONFIG_CMD_USB #ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index d933a9e..d3ab6e4 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -24,17 +24,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_DBGU -/* - * This needs to be defined for the OHCI code to work but it is defined as - * ATMEL_ID_UHPHS in the CPU specific header files. - */ -#define ATMEL_ID_UHP ATMEL_ID_UHPHS - -/* - * Specify the clock enable bit in the PMC_SCER register. - */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - /* LCD */ #define CONFIG_LCD #define LCD_BPP LCD_COLOR16 @@ -128,13 +117,9 @@ #define CONFIG_CMD_USB #ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #endif -- 1.9.1

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[U-Boot] [PATCH 1/2] ddr: altera: Replace float multiplication with integer one
by Marek Vasut 19 Aug '15

19 Aug '15

This gem is really really rare, there was an actual float used in the Altera DDR init code, which pulled in floating point ops from the libgcc, just wow. Since we don't support floating point operations the same way Linux does not support them, replace this with an integer multiplication and division combo. This removes some 2kiB of size from the SPL as the floating point ops are no longer pulled in from libgcc. This was detected by enabling CONFIG_USE_PRIVATE_LIBGCC=y , which does not contain the floating point bits. Signed-off-by: Marek Vasut <marex(a)denx.de> --- drivers/ddr/altera/sequencer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 2bd0109..f3621cf 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3247,7 +3247,7 @@ static void mem_skip_calibrate(void) * (1.25 * iocfg->dll_chain_length - 2) */ scc_mgr_set_dqdqs_output_phase(i, - 1.25 * iocfg->dll_chain_length - 2); + ((125 * iocfg->dll_chain_length) / 100) - 2); } writel(0xff, &sdr_scc_mgr->dqs_ena); writel(0xff, &sdr_scc_mgr->dqs_io_ena); -- 2.1.4

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[U-Boot] [PATCH] arm: socfpga: Fix delay in freeze controller
by Marek Vasut 19 Aug '15

19 Aug '15

Based on observation, this udelay(20) was apparently too high and caused subsequent failure to calibrate DDR when U-Boot was compiled with certain toolchains. Lowering this delay fixed the problem. Instead of permanently lowering the delay, calculate the correct delay based on the original comment, that is, obtain EOSC1 frequency and use it to calculate the precise delay. Signed-off-by: Marek Vasut <marex(a)denx.de> --- arch/arm/mach-socfpga/freeze_controller.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 0be643c..2b16795 100644 --- a/arch/arm/mach-socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c @@ -7,8 +7,8 @@ #include <common.h> #include <asm/io.h> +#include <asm/arch/clock_manager.h> #include <asm/arch/freeze_controller.h> -#include <asm/arch/timer.h> #include <asm/errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -112,6 +112,7 @@ void sys_mgr_frzctrl_thaw_req(void) u32 reg_cfg_mask; u32 reg_value; u32 channel_id; + unsigned long eosc1_freq; /* select software FSM */ writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); @@ -162,12 +163,9 @@ void sys_mgr_frzctrl_thaw_req(void) setbits_le32(&freeze_controller_base->hioctrl, SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK); - /* - * Delay 1000 intosc. intosc is based on eosc1 - * Use worst case which is fatest eosc1=50MHz, delay required - * is 1/50MHz * 1000 = 20us - */ - udelay(20); + /* Delay 1000 intosc cycles. The intosc is based on eosc1. */ + eosc1_freq = cm_get_osc_clk_hz(1) / 1000; /* kHz */ + udelay(DIV_ROUND_UP(1000000, eosc1_freq)); /* * de-assert active low bhniotri signals, -- 2.1.4

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