August 2015 - U-Boot

[U-Boot] [PATCH v2 0/3] usb: host/gadget: Miscellaneous fixes
by Kishon Vijay Abraham I 20 Aug '15

20 Aug '15

Changes from v1: Added reviewed-by. This patch series is split from [1] to contain only the usb host/gadget fixes. [1] -> http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/229188 Kishon Vijay Abraham I (3): usb: gadget: ether: Perform board initialization from ethernet gadget driver usb: host: xhci-omap: invoke board_usb_cleanup in xhci_hcd_stop usb: gadget: ether: populate _reset_ callback drivers/usb/gadget/ether.c | 5 +++++ drivers/usb/host/xhci-omap.c | 1 + 2 files changed, 6 insertions(+) -- 1.7.9.5

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[U-Boot] ext4load and ls
by Glen Cook 20 Aug '15

20 Aug '15

Hi, Can anyone tell me if there is any work going on for further ext4 support in u-boot. In particular ext4load mmc and ls. This is notoriously slow for a large number of files. Cheers Glen

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[U-Boot] [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
by Yuantian.Tang＠freescale.com 20 Aug '15

20 Aug '15

From: Tang Yuantian <Yuantian.Tang(a)freescale.com> Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- v2: - rebase to latest git tree - use micro SATA_ECC_REG_ADDR instead of hard coding arch/arm/include/asm/arch-ls102xa/config.h | 15 ++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 24 +++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 61 +++++++++++++++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 61 +++++++++++++++++++++++ 4 files changed, 161 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index c55cdef..a4a5d84 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -79,6 +79,21 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ CONFIG_SYS_PCIE2_VIRT_ADDR) +/* SATA */ +#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_FSL_ERRATUM_A008407 + #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index d34044a..211fe1d 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -397,4 +397,28 @@ struct ccsr_cci400 { u8 res_e004[0x10000 - 0xe004]; }; +/* AHCI (sata) register map */ +struct ccsr_ahci { + u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ + u32 pcfg; /* port config */ + u32 ppcfg; /* port phy1 config */ + u32 pp2c; /* port phy2 config */ + u32 pp3c; /* port phy3 config */ + u32 pp4c; /* port phy4 config */ + u32 pp5c; /* port phy5 config */ + u32 paxic; /* port AXI config */ + u32 axicc; /* AXI cache control */ + u32 axipc; /* AXI PROT control */ + u32 ptc; /* port Trans Config */ + u32 pts; /* port Trans Status */ + u32 plc; /* port link config */ + u32 plc1; /* port link config1 */ + u32 plc2; /* port link config2 */ + u32 pls; /* port link status */ + u32 pls1; /* port link status1 */ + u32 pcmdc; /* port CMD config */ + u32 ppcs; /* port phy control status */ + u32 pberr; /* port 0/1 BIST error */ + u32 cmds; /* port 0/1 CMD status error */ +}; #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d6ef6ba..1b26ed3 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -18,6 +18,8 @@ #include <fsl_ifc.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #include "../common/qixis.h" @@ -54,6 +56,52 @@ enum { GE1_CLK125, }; +static void ls1021a_sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 + unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR; +#endif + + out_le32(&ccsr_ahci->ppcfg, 0xa003fffe); + out_le32(&ccsr_ahci->pp2c, 0x28183411); + out_le32(&ccsr_ahci->pp3c, 0x0e081004); + out_le32(&ccsr_ahci->pp4c, 0x00480811); + out_le32(&ccsr_ahci->pp5c, 0x192c96a4); + out_le32(&ccsr_ahci->ptc, 0x08000025); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 + out_le32(ecc_reg, 0x00020000); +#endif +} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start(void) +{ + struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 cfg; + int rc = -1; + + cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; + + if (cfg != 0x30 && cfg != 0x70) { + printf("SATA disabled: serdes protocol doesn't support\n"); + return rc; + } + + rc = ahci_init((void __iomem *)AHCI_BASE_ADDR); + if (rc) + return rc; + + scsi_scan(0); + + return 0; +} +#endif + #ifdef CONFIG_LS102XA_NS_ACCESS static struct csu_ns_dev ns_dev[] = { { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, @@ -327,6 +375,8 @@ int board_early_init_f(void) fsl_dp_disable_console(); #endif + ls1021a_sata_init(); + return 0; } @@ -388,6 +438,17 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_start(); +#endif + + return 0; +} +#endif + void config_etseccm_source(int etsec_gtx_125_mux) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b7458a9..6a964c3 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -22,6 +22,8 @@ #include <tsec.h> #include <fsl_sec.h> #include <spl.h> +#include <ahci.h> +#include <scsi.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" @@ -173,6 +175,52 @@ struct cpld_data { u8 rev2; /* Reserved */ }; +static void ls1021a_sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 +#define SATA_ECC_REG_ADDR 0x20220520 + unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR; +#endif + + out_le32(&ccsr_ahci->ppcfg, 0xa003fffe); + out_le32(&ccsr_ahci->pp2c, 0x28183411); + out_le32(&ccsr_ahci->pp3c, 0x0e081004); + out_le32(&ccsr_ahci->pp4c, 0x00480811); + out_le32(&ccsr_ahci->pp5c, 0x192c96a4); + out_le32(&ccsr_ahci->ptc, 0x08000025); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 + out_le32(ecc_reg, 0x00020000); +#endif +} + +#ifdef CONFIG_SCSI_AHCI_PLAT +static int ls1021a_sata_start(void) +{ + struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 cfg; + int rc = -1; + + cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; + + if (cfg != 0x10 && cfg != 0x30 && cfg != 0x70) { + printf("SATA disabled: serdes protocol doesn't support\n"); + return rc; + } + + rc = ahci_init((void __iomem *)AHCI_BASE_ADDR); + if (rc) + return rc; + + scsi_scan(0); + + return 0; +} +#endif + #ifndef CONFIG_QSPI_BOOT static void convert_serdes_mux(int type, int need_reset); @@ -522,9 +570,22 @@ int board_early_init_f(void) fsl_dp_disable_console(); #endif + ls1021a_sata_init(); + return 0; } +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_start(); +#endif + + return 0; +} +#endif + #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) { -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] ARM: tegra: fix PLLP frequency calc on T210
by Stephen Warren 20 Aug '15

20 Aug '15

From: Stephen Warren <swarren(a)nvidia.com> AFAIK, for all PLLs on all Tegra SoCs, the primary PLL output frequency is (input * m) / (n * p). However, PLLP's primary output (pllP_out0) on T210 is the VCO output, and divp is not applied. pllP_out2 does have divp applied. All other pllP_outN are divided down from pllP_out0. We only support pllP_out0 in U-Boot at the time of writing. Fix clock_get_rate() to handle this special case. This corrects the returned rate for PLLP to be 408MHz rather than 204MHz. In turn, this causes high enough dividers to be calculated for the various peripheral clocks that feed off of PLLP. Without this, some peripherals failed to operate correctly. For instance, one of my SD cards worked perfectly but an older (presumably slower) card could not be read. Note that prior to commit 722e000ccd72 "Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.", the calculated PLL frequency was 816MHz since the wrong values were being extracted from the PLLP divider register. This caused overly large peripheral dividers to be calculated, which while wrong, didn't cause any correctness issues; things simply ran slower than they could. Reported-by: Thierry Reding <treding(a)nvidia.com> Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/mach-tegra/clock.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index f9dfcd04115a..b85f63848f2c 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -483,7 +483,16 @@ unsigned clock_get_rate(enum clock_id clkid) * PLLU uses p_mask/p_shift for VCO on all but T210, * T210 uses normal DIVP. Handled in pllinfo table. */ - divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; +#ifdef CONFIG_TEGRA210 + /* + * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is + * not applied. pllP_out2 does have divp applied. All other pllP_outN + * are divided down from pllP_out0. We only support pllP_out0 in + * U-Boot at the time of writing this comment. + */ + if (clkid != CLOCK_ID_PERIPH) +#endif + divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; do_div(rate, divm); return rate; } -- 1.9.1

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[U-Boot] [PATCH 0/3] nand: Sync with Linux v4.1
by Scott Wood 19 Aug '15

19 Aug '15

As requested, these patches can be found in the sync-4.1 branch of u-boot-nand-flash.git. Ezequiel Garcia (1): mtd: Introduce mtd_block_isreserved() Scott Wood (2): nand: Remove __UBOOT__ ifdefs nand: Sync with Linux v4.1 drivers/mtd/mtdcore.c | 14 +- drivers/mtd/mtdpart.c | 9 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/atmel_nand_ecc.h | 3 + drivers/mtd/nand/denali.c | 209 +++++++------ drivers/mtd/nand/denali.h | 8 +- drivers/mtd/nand/docg4.c | 6 +- drivers/mtd/nand/fsl_elbc_nand.c | 14 + drivers/mtd/nand/fsl_ifc_nand.c | 33 +- drivers/mtd/nand/nand_base.c | 615 ++++++++++---------------------------- drivers/mtd/nand/nand_bbt.c | 75 ++--- drivers/mtd/nand/nand_ids.c | 10 +- drivers/mtd/nand/nand_timings.c | 252 ++++++++++++++++ include/fsl_ifc.h | 2 + include/linux/mtd/mtd.h | 2 + include/linux/mtd/nand.h | 122 +++++--- 16 files changed, 715 insertions(+), 660 deletions(-) create mode 100644 drivers/mtd/nand/nand_timings.c -- 2.1.4

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[U-Boot] [PATCH] ARM: tegra: fix COUNTER_FREQUENCY for T210
by Stephen Warren 19 Aug '15

19 Aug '15

From: Stephen Warren <swarren(a)nvidia.com> While T210 boards all have 38.4MHz crystals, per the TRM, the only supported configuration is to divide the crystal frequency by 2 to generate clk_m, which is what feeds the ARM generic timers amongst other things. Fix the value of COUNTER_FREQUENCY to reflect this divide-by-2. When I queried the 19.2 value in Tom's original T210 patches, I wasn't aware of this extra divide-by-2, and didn't notice any effect from the incorrect value, since its only used if U-Boot is booted in EL3, whereas I'm booting it in EL2. Reported-by: Thierry Reding <treding(a)nvidia.com> Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- include/configs/e2220-1170.h | 3 ++- include/configs/p2371-0000.h | 3 ++- include/configs/p2371-2180.h | 3 ++- include/configs/p2571.h | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h index dff3f2a35733..3bc60637edc1 100644 --- a/include/configs/e2220-1170.h +++ b/include/configs/e2220-1170.h @@ -60,6 +60,7 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define COUNTER_FREQUENCY 38400000 +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 #endif /* _E2220_1170_H */ diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index 9d7b650d98ca..397a0ef8ae7b 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -60,6 +60,7 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define COUNTER_FREQUENCY 38400000 +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 #endif /* _P2371_0000_H */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 378d5a905e93..f311ae9e7d03 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -60,6 +60,7 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define COUNTER_FREQUENCY 38400000 +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 #endif /* _P2371_2180_H */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 356c941a773f..3bf98884723d 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -61,7 +61,8 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define COUNTER_FREQUENCY 38400000 +/* Crystal is 38.4MHz. clk_m runs at half that rate */ +#define COUNTER_FREQUENCY 19200000 #define CONFIG_OF_BOARD_SETUP #endif /* _P2571_H */ -- 1.9.1

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[U-Boot] [PATCH 1/2] usb: dwc2: Add original Synopsys compat string
by Marek Vasut 19 Aug '15

19 Aug '15

Add the Synopsys compatible string. This is used in SoCFPGA DT files. Signed-off-by: Marek Vasut <marex(a)denx.de> --- drivers/usb/host/dwc2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 09f91f1..7b29134 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -1113,6 +1113,7 @@ struct dm_usb_ops dwc2_usb_ops = { static const struct udevice_id dwc2_usb_ids[] = { { .compatible = "brcm,bcm2835-usb" }, + { .compatible = "snps,dwc2" }, { } }; -- 2.1.4

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[U-Boot] [PATCH 0/8] arm: socfpga: Board cleanup
by Marek Vasut 19 Aug '15

19 Aug '15

This series cleans up the QTS-generated header files and cleans up the SoCDK support such that they fit into the framework just like any other SoCFPGA boards. Marek Vasut (8): arm: socfpga: Move wrappers into platform directory arm: socfpga: Unbind CPU type from board type arm: socfpga: Split Altera socfpga into AV and CV SoCDK arm: socfpga: Remove CV-specific parts from AV-SoCDK arm: socfpga: Remove AV-specific parts from CV-SoCDK arm: socfpga: Add qts-filter.sh script arm: socfpga: Switch to filtered QTS files arm: socfpga: Make the pinmux table const u8 arch/arm/mach-socfpga/Kconfig | 26 +- arch/arm/mach-socfpga/Makefile | 9 + .../arm/mach-socfpga/include/mach/system_manager.h | 3 +- arch/arm/mach-socfpga/qts-filter.sh | 205 +++ arch/arm/mach-socfpga/system_manager.c | 2 +- .../arm/mach-socfpga}/wrap_iocsr_config.c | 7 +- arch/arm/mach-socfpga/wrap_pinmux_config.c | 17 + .../arm/mach-socfpga}/wrap_pll_config.c | 2 +- .../arm/mach-socfpga}/wrap_sdram_config.c | 8 +- board/altera/{socfpga => arria5-socdk}/MAINTAINERS | 0 board/altera/{socfpga => arria5-socdk}/Makefile | 4 +- board/altera/arria5-socdk/qts/iocsr_config.h | 696 ++++++++++ board/altera/arria5-socdk/qts/pinmux_config.h | 219 ++++ board/altera/arria5-socdk/qts/pll_config.h | 85 ++ board/altera/arria5-socdk/qts/sdram_config.h | 340 +++++ board/altera/{socfpga => arria5-socdk}/socfpga.c | 0 .../altera/{socfpga => cyclone5-socdk}/MAINTAINERS | 0 board/altera/{socfpga => cyclone5-socdk}/Makefile | 4 +- board/altera/cyclone5-socdk/qts/iocsr_config.h | 660 ++++++++++ board/altera/cyclone5-socdk/qts/pinmux_config.h | 219 ++++ board/altera/cyclone5-socdk/qts/pll_config.h | 85 ++ board/altera/cyclone5-socdk/qts/sdram_config.h | 342 +++++ board/altera/{socfpga => cyclone5-socdk}/socfpga.c | 0 board/altera/socfpga/qts/iocsr_config.c | 1345 -------------------- board/altera/socfpga/qts/iocsr_config.h | 26 - board/altera/socfpga/qts/pinmux_config.c | 429 ------- board/altera/socfpga/qts/pinmux_config.h | 54 - board/altera/socfpga/qts/pll_config.h | 109 -- board/altera/socfpga/qts/sdram_config.h | 100 -- board/altera/socfpga/qts/sequencer_auto.h | 128 -- board/altera/socfpga/qts/sequencer_auto_ac_init.h | 84 -- .../altera/socfpga/qts/sequencer_auto_inst_init.h | 268 ---- board/altera/socfpga/qts/sequencer_defines.h | 122 -- board/altera/socfpga/wrap_pinmux_config.c | 35 - configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + 37 files changed, 2908 insertions(+), 2728 deletions(-) create mode 100755 arch/arm/mach-socfpga/qts-filter.sh rename {board/altera/socfpga => arch/arm/mach-socfpga}/wrap_iocsr_config.c (87%) create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config.c rename {board/altera/socfpga => arch/arm/mach-socfpga}/wrap_pll_config.c (99%) rename {board/altera/socfpga => arch/arm/mach-socfpga}/wrap_sdram_config.c (98%) copy board/altera/{socfpga => arria5-socdk}/MAINTAINERS (100%) copy board/altera/{socfpga => arria5-socdk}/Makefile (57%) create mode 100644 board/altera/arria5-socdk/qts/iocsr_config.h create mode 100644 board/altera/arria5-socdk/qts/pinmux_config.h create mode 100644 board/altera/arria5-socdk/qts/pll_config.h create mode 100644 board/altera/arria5-socdk/qts/sdram_config.h copy board/altera/{socfpga => arria5-socdk}/socfpga.c (100%) rename board/altera/{socfpga => cyclone5-socdk}/MAINTAINERS (100%) rename board/altera/{socfpga => cyclone5-socdk}/Makefile (57%) create mode 100644 board/altera/cyclone5-socdk/qts/iocsr_config.h create mode 100644 board/altera/cyclone5-socdk/qts/pinmux_config.h create mode 100644 board/altera/cyclone5-socdk/qts/pll_config.h create mode 100644 board/altera/cyclone5-socdk/qts/sdram_config.h rename board/altera/{socfpga => cyclone5-socdk}/socfpga.c (100%) delete mode 100644 board/altera/socfpga/qts/iocsr_config.c delete mode 100644 board/altera/socfpga/qts/iocsr_config.h delete mode 100644 board/altera/socfpga/qts/pinmux_config.c delete mode 100644 board/altera/socfpga/qts/pinmux_config.h delete mode 100644 board/altera/socfpga/qts/pll_config.h delete mode 100644 board/altera/socfpga/qts/sdram_config.h delete mode 100644 board/altera/socfpga/qts/sequencer_auto.h delete mode 100644 board/altera/socfpga/qts/sequencer_auto_ac_init.h delete mode 100644 board/altera/socfpga/qts/sequencer_auto_inst_init.h delete mode 100644 board/altera/socfpga/qts/sequencer_defines.h delete mode 100644 board/altera/socfpga/wrap_pinmux_config.c -- 2.1.4

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[U-Boot] [PATCH v2 0/7] BAR/wait_ready logic updates
by Jagan Teki 19 Aug '15

19 Aug '15

BAR and spi_flash_cmd_wait_ready are updated to make more module to add new status checks. Changes for v2: - Update bank_sel for non-bar case. - split the spi_flash_cmd_wait_ready logic into SR and FSR patches. Clone spi-nor branch u-boot-spi.git repo for changes http://git.denx.de/?p=u-boot/u-boot-spi.git;a=tree;h=refs/heads/spi-nor;hb=… Jagan Teki (7): spi: zynq_spi: Remove unneeded headers sf: Return proper bank_sel, if flash->bank_curr == bank_sel sf: Make BAR discovery, as spi_flash_read_bar sf: Optimize BAR write code sf: Make flash->flags use for generic usage sf: Update status reg check in spi_flash_cmd_wait_ready sf: Add FSR support to spi_flash_cmd_wait_ready drivers/mtd/spi/sf_internal.h | 5 ++ drivers/mtd/spi/sf_ops.c | 151 +++++++++++++++++++++--------------------- drivers/mtd/spi/sf_probe.c | 64 ++++++++++-------- drivers/spi/zynq_spi.c | 6 +- include/spi_flash.h | 6 +- 5 files changed, 121 insertions(+), 111 deletions(-) -- 1.9.1

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[U-Boot] [PATCH 01/11] arm: pxa: clean-up include file order
by Marcel Ziswiler 19 Aug '15

19 Aug '15

Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel(a)ziswiler.com> --- arch/arm/cpu/pxa/pxa2xx.c | 4 ++-- arch/arm/cpu/pxa/timer.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index 7e861e2..2f12fb9 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -10,11 +10,11 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> +#include <asm/arch/pxa-regs.h> #include <asm/io.h> #include <asm/system.h> #include <command.h> -#include <common.h> -#include <asm/arch/pxa-regs.h> /* Flush I/D-cache */ static void cache_flush(void) diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c index 11fefd5..7c25e67 100644 --- a/arch/arm/cpu/pxa/timer.c +++ b/arch/arm/cpu/pxa/timer.c @@ -6,8 +6,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <asm/io.h> #include <common.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; -- 2.4.3

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