August 2015 - U-Boot

[U-Boot] [v3 0/4] spi: cadence_qspi: optimize & fix indirect rd-writes
by Vikas Manocha 21 Aug '15

21 Aug '15

This patchset: - fixes trigger base & transfer start address register programming. This fix superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb trigger address setting". - adds support to get fifo width from device tree Changes in v3: - removed two patches which were bypassing the sram level check. - format string in patch corrected 3/4 - added commit message in patch 1/4 Changes in v2: - rebased to master. - removed patch "spi: cadence_qspi: read can be independent of fifo width", it was implemented in other patchset, in mainline now. Vikas Manocha (4): spi: cadence_qspi: move trigger base configuration in init spi: cadence_qspi: fix indirect read/write start address spi: cadence_qspi: fix base trigger address & transfer start address spi: cadence_qspi: get fifo width from device tree arch/arm/dts/socfpga.dtsi | 4 +++- arch/arm/dts/stv0991.dts | 4 +++- drivers/spi/cadence_qspi.c | 15 +++++++------- drivers/spi/cadence_qspi.h | 6 ++++-- drivers/spi/cadence_qspi_apb.c | 42 ++++++++++++++++------------------------ 5 files changed, 35 insertions(+), 36 deletions(-) -- 1.7.9.5

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 21 Aug '15

21 Aug '15

The following changes since commit 0f9258228e2b2070368ffccf5c243218128770a8: of: clean up OF_CONTROL ifdef conditionals (2015-08-18 13:46:05 -0400) are available in the git repository at: git://git.denx.de/u-boot-usb.git HEAD for you to fetch changes up to 7a1386f96bca550240670fa3461d3a0dc060aa01: usb: dwc2: Rename to dwc2_usb (2015-08-19 22:31:39 +0200) ---------------------------------------------------------------- Adrian Alonso (4): imx: usb: ehci-mx6: reg accessor cleanups imx: usb: ehci-mx6: document board specific functions imx: usb: ehci-mx6: add usb support for imx7d soc imx: usb: ehci-mx6: wait_for_bit to check reg status Kishon Vijay Abraham I (3): usb: gadget: ether: Perform board initialization from ethernet gadget driver usb: host: xhci-omap: invoke board_usb_cleanup in xhci_hcd_stop usb: gadget: ether: populate _reset_ callback Marek Vasut (2): usb: dwc2: Add original Synopsys compat string usb: dwc2: Rename to dwc2_usb Sergey Temerkhanov (1): usb: xhci: Fix a potential NULL pointer dereference Stefan Roese (1): usb: spear: Add support for both SPEAr600 EHCI controllers arch/arm/cpu/arm926ejs/spear/cpu.c | 4 ++ arch/arm/include/asm/arch-spear/hardware.h | 2 + drivers/usb/gadget/ether.c | 5 +++ drivers/usb/host/Makefile | 1 + drivers/usb/host/dwc2.c | 3 +- drivers/usb/host/ehci-mx6.c | 211 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------ drivers/usb/host/ehci-spear.c | 38 +++++++++++++++-- drivers/usb/host/xhci-omap.c | 1 + drivers/usb/host/xhci.c | 19 ++++++--- 9 files changed, 223 insertions(+), 61 deletions(-)

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[U-Boot] [PATCH 00/25] dm: Convert TPM drivers to driver model
by Simon Glass 20 Aug '15

20 Aug '15

This series adds driver model support for Trusted Platform Modules (TPMs). These have a very simple interface and are configured via the device tree. Two bus types are supported at present: I2C and LPC (Intel Low-Pin-Count). Most drivers and users are converted over to driver model. The exception is the Atmel TPM and its users. The I2C driver has been cleaned up and simplified. It was ported from Linux and was pretty hard to follow. This series includes patches to unify the code, remove duplicated data structures and drop unnecessary indirection. Also this series enables the TPM on all Chromebooks (snow, spring, nyan-big, pit, pi, link) since some did not have it fully enabled. As before, the 'tpm' command can be used to implement TPM functionality. Simon Glass (25): tpm: Remove old pre-driver-model I2C code tpm: Drop two unused options tpm: Add Kconfig options for TPMs tpm: Convert board config TPM options to Kconfig tpm: Convert drivers to use SPDX tpm: Move the I2C TPM code into one file tpm: tpm_tis_i2c: Drop unnecessary methods tpm: tpm_tis_i2c: Drop struct tpm_vendor_specific tpm: tpm_tis_i2c: Merge struct tpm_dev into tpm_chip tpm: tpm_tis_i2c: Merge struct tpm into tpm_chip tpm: tpm_tis_i2c: Move definitions into the header file tpm: tpm_tis_i2c: Simplify init code tpm: tpm_tis_i2c: Use a consistent tpm_tis_i2c_ prefix tpm: tpm_tis_i2c: Tidy up delays dm: tpm: Add a uclass for Trusted Platform Modules dm: tpm: Convert the TPM command and library to driver model dm: i2c: Add a command to adjust the offset length tpm: Report tpm errors on the command line dm: tpm: sandbox: Convert TPM driver to driver model tpm: Check that parse_byte_string() has data to parse exynos: x86: dts: Add tpm nodes to the device tree for Chrome OS devices dm: tpm: Convert I2C driver to driver model dm: tpm: Convert LPC driver to driver model tpm: Add a 'tpm info' command tegra: nyan: Enable TPM command and driver README | 6 - arch/arm/dts/exynos5250-snow.dts | 9 + arch/arm/dts/exynos5250-spring.dts | 8 + arch/arm/dts/exynos5420-peach-pit.dts | 6 +- arch/arm/dts/exynos5800-peach-pi.dts | 6 +- arch/sandbox/dts/sandbox.dts | 4 + arch/x86/dts/chromebook_link.dts | 5 + common/Kconfig | 12 + common/cmd_i2c.c | 33 + common/cmd_tpm.c | 100 ++- configs/chromebook_link_defconfig | 4 + configs/chromebox_panther_defconfig | 4 + .../controlcenterd_36BIT_SDCARD_DEVELOP_defconfig | 4 + configs/controlcenterd_36BIT_SDCARD_defconfig | 4 + .../controlcenterd_TRAILBLAZER_DEVELOP_defconfig | 4 + configs/controlcenterd_TRAILBLAZER_defconfig | 4 + configs/coreboot-x86_defconfig | 4 + configs/nyan-big_defconfig | 4 + configs/peach-pi_defconfig | 4 + configs/peach-pit_defconfig | 4 + configs/sandbox_defconfig | 3 + configs/snow_defconfig | 4 + configs/spring_defconfig | 4 + drivers/tpm/Kconfig | 61 ++ drivers/tpm/Makefile | 4 +- drivers/tpm/tpm-uclass.c | 57 ++ drivers/tpm/tpm.c | 694 --------------------- drivers/tpm/tpm_atmel_twi.c | 15 +- drivers/tpm/tpm_private.h | 140 ----- drivers/tpm/tpm_tis_i2c.c | 594 ++++++++++-------- drivers/tpm/tpm_tis_i2c.h | 446 +++++++++++++ drivers/tpm/tpm_tis_lpc.c | 291 +++++---- drivers/tpm/tpm_tis_sandbox.c | 48 +- include/configs/controlcenterd.h | 7 - include/configs/efi-x86.h | 2 - include/configs/exynos5-common.h | 7 - include/configs/x86-common.h | 2 - include/dm/uclass-id.h | 1 + include/fdtdec.h | 2 - include/tis.h | 97 +++ include/tpm.h | 2 +- lib/Kconfig | 10 + lib/fdtdec.c | 2 - lib/tpm.c | 29 +- 44 files changed, 1404 insertions(+), 1347 deletions(-) create mode 100644 drivers/tpm/tpm-uclass.c delete mode 100644 drivers/tpm/tpm.c delete mode 100644 drivers/tpm/tpm_private.h create mode 100644 drivers/tpm/tpm_tis_i2c.h -- 2.5.0.rc2.392.g76e840b

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[U-Boot] [PATCH 0/3] arm: tegra20/colibri_t20: early pmic rail configuration
by Marcel Ziswiler 20 Aug '15

20 Aug '15

Implement early TPS6586X PMIC rail configuration setting SM0 being VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts. While those are PMIC power-up defaults the SoC might have been reset separately with certain rails being left at lower DVFS states which is e.g. the case upon watchdog reset while otherwise nearly idling. This fixes an issue of the Colibri T20 being stuck in U-Boot's SPL upon watchdog reset (e.g. running downstream L4T Linux kernel as there exists no mainline Tegra20 watchdog driver as of yet). The last patch in this series is not really related but just gets rid of a spurious MAX_I2C_RETRY define in the Colibri T20's board file. Marcel Ziswiler (3): arm: tegra20: implement early pmic rail configuration colibri_t20: enable early pmic rail configuration colibri_t20: get rid of spurious MAX_I2C_RETRY define arch/arm/mach-tegra/tegra20/cpu.c | 76 ++++++++++++++++++++++++++++++++- board/toradex/colibri_t20/colibri_t20.c | 1 - include/configs/colibri_t20.h | 2 + 3 files changed, 77 insertions(+), 2 deletions(-) -- 2.4.3

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[U-Boot] [PATCH] ARM: cpu: Add ARMv7 barrier operations support
by Vladimir Barinov 20 Aug '15

20 Aug '15

From: Valentine Barshak <valentine.barshak(a)cogentembedded.com> This enables ARMv7 barrier operations support when march=armv7-a is enabled. Using CP15 barriers causes U-Boot bootm command crash when transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU. Using ARMv7 barrier operations instead of the deprecated CP15 barriers helps to avoid these issues. Signed-off-by: Valentine Barshak <valentine.barshak+renesas(a)cogentembedded.com> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas(a)cogentembedded.com> Reviewed-by: Tom Rini <trini(a)konsulko.com> --- arch/arm/cpu/armv7/cache_v7.c | 14 +++++++------- arch/arm/include/asm/armv7.h | 10 ++++++++++ 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 0f9d837..e8ee875 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, } } /* DSB to make sure the operation is complete */ - CP15DSB; + DSB; } static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, @@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, } } /* DSB to make sure the operation is complete */ - CP15DSB; + DSB; } static void v7_maint_dcache_level_setway(u32 level, u32 operation) @@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* DSB to make sure the operation is complete */ - CP15DSB; + DSB; } /* Invalidate TLB */ @@ -228,9 +228,9 @@ static void v7_inval_tlb(void) /* Invalidate entire instruction TLB */ asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; + DSB; /* Full system ISB - make sure the instruction stream sees it */ - CP15ISB; + ISB; } void invalidate_dcache_all(void) @@ -343,10 +343,10 @@ void invalidate_icache_all(void) asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; + DSB; /* ISB - make sure the instruction stream sees it */ - CP15ISB; + ISB; } #else void invalidate_icache_all(void) diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a13da23..189f3f0 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -70,6 +70,16 @@ #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) +#ifdef __ARM_ARCH_7A__ +#define ISB asm volatile ("isb" : : : "memory") +#define DSB asm volatile ("dsb" : : : "memory") +#define DMB asm volatile ("dmb" : : : "memory") +#else +#define ISB CP15ISB +#define DSB CP15DSB +#define DMB CP15DMB +#endif + /* * Workaround for ARM errata # 798870 * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been -- 1.9.3

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[U-Boot] [PATCH v2] ARM: davinci: remove support for cam_enc_4xx
by Masahiro Yamada 20 Aug '15

20 Aug '15

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> Acked-by: Heiko Schocher <hs(a)denx.de> Acked-by: Marek Vasut <marex(a)denx.de> --- Changes in v2: - Use lower cases for the board name arch/arm/mach-davinci/Kconfig | 5 - board/ait/cam_enc_4xx/Kconfig | 12 - board/ait/cam_enc_4xx/MAINTAINERS | 6 - board/ait/cam_enc_4xx/Makefile | 10 - board/ait/cam_enc_4xx/cam_enc_4xx.c | 1106 ---------------------------------- board/ait/cam_enc_4xx/config.mk | 20 - board/ait/cam_enc_4xx/u-boot-spl.lds | 57 -- board/ait/cam_enc_4xx/ublimage.cfg | 31 - configs/cam_enc_4xx_defconfig | 10 - doc/README.scrapyard | 1 + include/configs/cam_enc_4xx.h | 504 ---------------- 11 files changed, 1 insertion(+), 1761 deletions(-) delete mode 100644 board/ait/cam_enc_4xx/Kconfig delete mode 100644 board/ait/cam_enc_4xx/MAINTAINERS delete mode 100644 board/ait/cam_enc_4xx/Makefile delete mode 100644 board/ait/cam_enc_4xx/cam_enc_4xx.c delete mode 100644 board/ait/cam_enc_4xx/config.mk delete mode 100644 board/ait/cam_enc_4xx/u-boot-spl.lds delete mode 100644 board/ait/cam_enc_4xx/ublimage.cfg delete mode 100644 configs/cam_enc_4xx_defconfig delete mode 100644 include/configs/cam_enc_4xx.h diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index e6cb390..681270d 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -18,10 +18,6 @@ config TARGET_DA850EVM bool "DA850 EVM board" select SUPPORT_SPL -config TARGET_CAM_ENC_4XX - bool "CAM ENC 4xx board" - select SUPPORT_SPL - config TARGET_OMAPL138_LCDK bool "OMAPL138 LCDK" select SUPPORT_SPL @@ -62,7 +58,6 @@ config SYS_SOC default "davinci" source "board/enbw/enbw_cmc/Kconfig" -source "board/ait/cam_enc_4xx/Kconfig" source "board/Barix/ipam390/Kconfig" source "board/davinci/da8xxevm/Kconfig" source "board/davinci/dm355evm/Kconfig" diff --git a/board/ait/cam_enc_4xx/Kconfig b/board/ait/cam_enc_4xx/Kconfig deleted file mode 100644 index 64e18f4..0000000 diff --git a/board/ait/cam_enc_4xx/MAINTAINERS b/board/ait/cam_enc_4xx/MAINTAINERS deleted file mode 100644 index d6477c6..0000000 diff --git a/board/ait/cam_enc_4xx/Makefile b/board/ait/cam_enc_4xx/Makefile deleted file mode 100644 index 0d03ce0..0000000 diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c deleted file mode 100644 index c5687ba..0000000 diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk deleted file mode 100644 index 2022151..0000000 diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds deleted file mode 100644 index f5c19df..0000000 diff --git a/board/ait/cam_enc_4xx/ublimage.cfg b/board/ait/cam_enc_4xx/ublimage.cfg deleted file mode 100644 index d4fe705..0000000 diff --git a/configs/cam_enc_4xx_defconfig b/configs/cam_enc_4xx_defconfig deleted file mode 100644 index a67bf0e..0000000 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index f029a0f..fb1ed42 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +cam_enc_4xx arm arm926ejs - - Heiko Schocher <hs(a)denx.de> atstk1003 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> atstk1004 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> atstk1006 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h deleted file mode 100644 index 578c4ab..0000000 -- 1.9.1

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[U-Boot] [GIT PULL] Zynq changes
by Michal Simek 20 Aug '15

20 Aug '15

Hi Tom, please pull these changes to your tree. There are 3 warnings. One zynq_zc70x which will be removed in the next release. The second is gem for 64bit warnings. And the third one by DCW3 the same as GEM. Thanks, Michal The following changes since commit 0f9258228e2b2070368ffccf5c243218128770a8: of: clean up OF_CONTROL ifdef conditionals (2015-08-18 13:46:05 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git zynq for you to fetch changes up to d1221462fece27ad163dcd0c181a456c73fe2011: zynqmp: enable CONFIG_NET_RANDOM_ETHADDR (2015-08-19 11:28:21 +0200) ---------------------------------------------------------------- Masahiro Yamada (2): ARM: zynq: drop "optional" from board select in favor of ZC702 zynq: enable CONFIG_NET_RANDOM_ETHADDR Michal Simek (7): zynqmp: Enable U-Boot run in EL3 ARM: zynqmp: Add platform specific arch_get_page_table ARM: zynqmp_ep: Enable ethernet for EP configs: zynqmp: Enable networking by default for EP108 zynq: Make CONFIG_OF_EMBED default case ARM: dts: Rename memory@0 to memory zynqmp: enable CONFIG_NET_RANDOM_ETHADDR Siva Durga Prasad Paladugu (2): board: Xilinx: zynqmp: Define checkboard() function zynqmp: usb: Add usb dwc3 driver support for zynqmp arch/arm/cpu/armv8/zynqmp/Kconfig | 7 +++++++ arch/arm/cpu/armv8/zynqmp/cpu.c | 5 +++++ arch/arm/dts/zynq-zc770-xm010.dts | 2 +- arch/arm/dts/zynq-zc770-xm011.dts | 2 +- arch/arm/dts/zynq-zc770-xm012.dts | 2 +- arch/arm/dts/zynq-zc770-xm013.dts | 2 +- arch/arm/include/asm/arch-zynqmp/hardware.h | 7 +++++++ arch/arm/mach-zynq/Kconfig | 2 +- board/xilinx/zynqmp/zynqmp.c | 34 ++++++++++++++++++++++++++++++++++ configs/xilinx_zynqmp_ep_defconfig | 12 ++++++++---- configs/zynq_microzed_defconfig | 2 ++ configs/zynq_picozed_defconfig | 2 ++ configs/zynq_zc702_defconfig | 3 ++- configs/zynq_zc706_defconfig | 2 ++ configs/zynq_zc70x_defconfig | 2 ++ configs/zynq_zc770_xm010_defconfig | 2 ++ configs/zynq_zc770_xm011_defconfig | 2 ++ configs/zynq_zc770_xm012_defconfig | 2 ++ configs/zynq_zc770_xm013_defconfig | 2 ++ configs/zynq_zed_defconfig | 2 ++ configs/zynq_zybo_defconfig | 2 ++ include/configs/xilinx_zynqmp.h | 42 ++++++++++++++++++++++++++++++++++++++++-- include/configs/xilinx_zynqmp_ep.h | 3 +++ include/configs/zynq-common.h | 2 +- 24 files changed, 132 insertions(+), 13 deletions(-) -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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[U-Boot] [PATCH 0/2] MIPS: add support to support usb stack for mips and minor cleanup
by Govindraj Raja 20 Aug '15

20 Aug '15

Patch prepares to support usb stack compiled for mips platform. Also fix fdt usage api's from bootm. Govindraj Raja (2): MIPS: add clrbits and setbits and add phy_to_bus support. MIPS: fix syntax for fdt_chosen/initrd. arch/mips/include/asm/io.h | 71 +++++++++++++++++++++++++++++++++++++++++++++- arch/mips/lib/bootm.c | 4 +-- 2 files changed, 72 insertions(+), 3 deletions(-) -- 1.9.1

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[U-Boot] [PATCH V2 1/2] ARM: tegra: Add e2220-1170 board
by Stephen Warren 20 Aug '15

20 Aug '15

From: Stephen Warren <swarren(a)nvidia.com> Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- v2: Use named constants for PMIC I2C and register addresses. --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra210-e2220-1170.dts | 58 +++++ arch/arm/mach-tegra/tegra210/Kconfig | 6 + board/nvidia/e2220-1170/Kconfig | 12 + board/nvidia/e2220-1170/MAINTAINERS | 6 + board/nvidia/e2220-1170/Makefile | 8 + board/nvidia/e2220-1170/e2220-1170.c | 51 ++++ board/nvidia/e2220-1170/pinmux-config-e2220-1170.h | 269 +++++++++++++++++++++ configs/e2220-1170_defconfig | 16 ++ include/configs/e2220-1170.h | 72 ++++++ 10 files changed, 499 insertions(+) create mode 100644 arch/arm/dts/tegra210-e2220-1170.dts create mode 100644 board/nvidia/e2220-1170/Kconfig create mode 100644 board/nvidia/e2220-1170/MAINTAINERS create mode 100644 board/nvidia/e2220-1170/Makefile create mode 100644 board/nvidia/e2220-1170/e2220-1170.c create mode 100644 board/nvidia/e2220-1170/pinmux-config-e2220-1170.h create mode 100644 configs/e2220-1170_defconfig create mode 100644 include/configs/e2220-1170.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ba6355379cba..d8e1841eb4d8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ tegra124-venice2.dtb \ + tegra210-e2220-1170.dtb \ tegra210-p2571.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-sld3-ref.dtb \ diff --git a/arch/arm/dts/tegra210-e2220-1170.dts b/arch/arm/dts/tegra210-e2220-1170.dts new file mode 100644 index 000000000000..75efbba1061e --- /dev/null +++ b/arch/arm/dts/tegra210-e2220-1170.dts @@ -0,0 +1,58 @@ +/dts-v1/; + +#include "tegra210.dtsi" + +/ { + model = "NVIDIA E2220-1170"; + compatible = "nvidia,e2220-1170", "nvidia,tegra210"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = "/i2c@0,7000d000"; + sdhci0 = "/sdhci@0,700b0600"; + sdhci1 = "/sdhci@0,700b0000"; + usb0 = "/usb@0,7d000000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0xc0000000>; + }; + + sdhci@0,700b0000 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@0,700b0600 { + status = "okay"; + bus-width = <8>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + }; + + usb@0,7d000000 { + status = "okay"; + dr_mode = "peripheral"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig index 147e6a83d722..9633ba8c629e 100644 --- a/arch/arm/mach-tegra/tegra210/Kconfig +++ b/arch/arm/mach-tegra/tegra210/Kconfig @@ -3,6 +3,11 @@ if TEGRA210 choice prompt "Tegra210 board select" +config TARGET_E2220_1170 + bool "NVIDIA Tegra210 E2220-1170 base board" + help + E2220-1170 ERS + config TARGET_P2571 bool "NVIDIA Tegra210 P2571 base board" help @@ -13,6 +18,7 @@ endchoice config SYS_SOC default "tegra210" +source "board/nvidia/e2220-1170/Kconfig" source "board/nvidia/p2571/Kconfig" endif diff --git a/board/nvidia/e2220-1170/Kconfig b/board/nvidia/e2220-1170/Kconfig new file mode 100644 index 000000000000..0a30f4936223 --- /dev/null +++ b/board/nvidia/e2220-1170/Kconfig @@ -0,0 +1,12 @@ +if TARGET_E2220_1170 + +config SYS_BOARD + default "e2220-1170" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "e2220-1170" + +endif diff --git a/board/nvidia/e2220-1170/MAINTAINERS b/board/nvidia/e2220-1170/MAINTAINERS new file mode 100644 index 000000000000..0abb37884018 --- /dev/null +++ b/board/nvidia/e2220-1170/MAINTAINERS @@ -0,0 +1,6 @@ +E2220-1170 BOARD +M: Tom Warren <twarren(a)nvidia.com> +S: Maintained +F: board/nvidia/e2220-1170/ +F: include/configs/e2220-1170.h +F: configs/e2220-1170_defconfig diff --git a/board/nvidia/e2220-1170/Makefile b/board/nvidia/e2220-1170/Makefile new file mode 100644 index 000000000000..c956b1972deb --- /dev/null +++ b/board/nvidia/e2220-1170/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2013-2015 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += e2220-1170.o diff --git a/board/nvidia/e2220-1170/e2220-1170.c b/board/nvidia/e2220-1170/e2220-1170.c new file mode 100644 index 000000000000..d66a72e5204c --- /dev/null +++ b/board/nvidia/e2220-1170/e2220-1170.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include "../p2571/max77620_init.h" +#include "pinmux-config-e2220-1170.h" + +void pin_mux_mmc(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO2 to 3.3V for SD card power */ + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); +} + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_clear_tristate_input_clamping(); + + gpio_config_table(e2220_1170_gpio_inits, + ARRAY_SIZE(e2220_1170_gpio_inits)); + + pinmux_config_pingrp_table(e2220_1170_pingrps, + ARRAY_SIZE(e2220_1170_pingrps)); + + pinmux_config_drvgrp_table(e2220_1170_drvgrps, + ARRAY_SIZE(e2220_1170_drvgrps)); +} diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h new file mode 100644 index 000000000000..397dc7f44b11 --- /dev/null +++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_E2220_1170_H_ +#define _PINMUX_CONFIG_E2220_1170_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config e2220_1170_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A5, IN), + GPIO_INIT(A6, IN), + GPIO_INIT(B4, IN), + GPIO_INIT(E6, IN), + GPIO_INIT(G2, OUT0), + GPIO_INIT(G3, OUT0), + GPIO_INIT(H0, OUT0), + GPIO_INIT(H1, OUT0), + GPIO_INIT(H2, IN), + GPIO_INIT(H3, OUT0), + GPIO_INIT(H4, OUT0), + GPIO_INIT(H5, IN), + GPIO_INIT(H6, OUT0), + GPIO_INIT(H7, OUT0), + GPIO_INIT(I0, OUT0), + GPIO_INIT(I1, IN), + GPIO_INIT(I2, OUT0), + GPIO_INIT(I3, OUT0), + GPIO_INIT(K0, IN), + GPIO_INIT(K1, OUT0), + GPIO_INIT(K2, OUT0), + GPIO_INIT(K3, OUT0), + GPIO_INIT(K4, IN), + GPIO_INIT(K5, OUT0), + GPIO_INIT(K6, IN), + GPIO_INIT(K7, OUT0), + GPIO_INIT(L0, OUT0), + GPIO_INIT(S4, OUT0), + GPIO_INIT(S5, OUT0), + GPIO_INIT(S6, OUT0), + GPIO_INIT(S7, OUT0), + GPIO_INIT(T0, OUT0), + GPIO_INIT(T1, OUT0), + GPIO_INIT(V1, OUT0), + GPIO_INIT(V2, OUT0), + GPIO_INIT(V3, IN), + GPIO_INIT(V5, OUT0), + GPIO_INIT(V6, OUT0), + GPIO_INIT(X0, IN), + GPIO_INIT(X1, IN), + GPIO_INIT(X2, IN), + GPIO_INIT(X3, IN), + GPIO_INIT(X4, IN), + GPIO_INIT(X5, IN), + GPIO_INIT(X6, IN), + GPIO_INIT(X7, IN), + GPIO_INIT(Y0, IN), + GPIO_INIT(Y1, IN), + GPIO_INIT(Z0, IN), + GPIO_INIT(Z4, OUT0), + GPIO_INIT(BB2, OUT0), + GPIO_INIT(BB3, OUT0), + GPIO_INIT(BB4, IN), + GPIO_INIT(CC1, IN), + GPIO_INIT(CC5, OUT0), + GPIO_INIT(CC6, IN), + GPIO_INIT(CC7, OUT0), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + } + +static const struct pmux_pingrp_config e2220_1170_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ + PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MOSI_PB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MOSI_PC0, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MISO_PC1, SPI1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SPI1_SCK_PC2, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS0_PC3, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS1_PC4, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_CTS_PD4, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_DAT_PE1, DMIC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_DAT_PE3, DMIC2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_DAT_PE5, DMIC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(UART2_TX_PG0, UART, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_RX_PG1, UART, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART2_RTS_PG2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO1_PV3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X3_AUD_PBB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SPDIF_OUT_PCC2, SPDIF, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPDIF_IN_PCC3, SPDIF, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(USB_VBUS_EN1_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL), + PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_E2220_1170_H */ diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig new file mode 100644 index 000000000000..a31f5fa78a05 --- /dev/null +++ b/configs/e2220-1170_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA210=y +CONFIG_TARGET_E2220_1170=y +CONFIG_DEFAULT_DEVICE_TREE="tegra210-e2220-1170" +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPL_DM=y +CONFIG_SPI_FLASH=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h new file mode 100644 index 000000000000..49eb55ae4b29 --- /dev/null +++ b/include/configs/e2220-1170.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _E2220_1170_H +#define _E2220_1170_H + +#include <linux/sizes.h> + +/* enable PMIC */ +#define CONFIG_MAX77620_POWER + +#include "tegra210-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Tegra210 (E2220-1170) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA E2220-1170" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB2.0 Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_DHCP + +#include "tegra-common-usb-gadget.h" +#include "tegra-common-post.h" + +#define COUNTER_FREQUENCY 38400000 + +#endif /* _E2220_1170_H */ -- 1.9.1

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[U-Boot] [PATCH 2/2] arm: socfpga: config: Remove hard-coded drvsel and smpsel
by Chin Liang See 20 Aug '15

20 Aug '15

Remove hard-coded SDMMC timing parameter drvsel and smplsel. This setting now will come from SDMMC calibration Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> --- include/configs/socfpga_common.h | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 5ca45a9..1ca795c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -155,8 +155,6 @@ #define CONFIG_DWMMC #define CONFIG_SOCFPGA_DWMMC #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 -#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 -#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 /* FIXME */ /* using smaller max blk cnt to avoid flooding the limited stack we have */ #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ -- 1.7.7.4

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