August 2015 - U-Boot

[U-Boot] [linux-sunxi] [PATCH] sunxi: Add support for the Olimex A20 EVB
by codekipper＠gmail.com 19 Aug '15

19 Aug '15

From: Marcus Cooper <codekipper(a)gmail.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun7i-a20-olinuxino-evb.dts | 233 +++++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 5 + configs/A20-OLinuXino-EVB_defconfig | 17 +++ 4 files changed, 256 insertions(+) create mode 100644 arch/arm/dts/sun7i-a20-olinuxino-evb.dts create mode 100644 configs/A20-OLinuXino-EVB_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d9a2f5f..dc9a500 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -120,6 +120,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-m3.dtb \ sun7i-a20-m5.dtb \ sun7i-a20-mk808c.dtb \ + sun7i-a20-olinuxino-evb.dtb \ sun7i-a20-olinuxino-lime.dtb \ sun7i-a20-olinuxino-lime2.dtb \ sun7i-a20-olinuxino-micro.dtb \ diff --git a/arch/arm/dts/sun7i-a20-olinuxino-evb.dts b/arch/arm/dts/sun7i-a20-olinuxino-evb.dts new file mode 100644 index 0000000..a0071fa --- /dev/null +++ b/arch/arm/dts/sun7i-a20-olinuxino-evb.dts @@ -0,0 +1,233 @@ +/* + * Copyright 2015 - Marcus Cooper <codekipper(a)gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Olimex A20-OLinuXino-EVB"; + compatible = "olimex,a20-olinuxino-evb", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinoevb>; + + green { + label = "a20-olinuxino-evb:green:usr"; + gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_axp_ipsout: axp_ipsout { + compatible = "regulator-fixed"; + regulator-name = "axp-ipsout"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&ahci { + target-supply = <&reg_ahci_5v>; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells = <1>; + + acin-supply = <&reg_axp_ipsout>; + vin2-supply = <&reg_axp_ipsout>; + vin3-supply = <&reg_axp_ipsout>; + ldo24in-supply = <&reg_axp_ipsout>; + ldo3in-supply = <&reg_axp_ipsout>; + + regulators { + vdd_rtc: ldo1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + avcc: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_csi0: ldo3 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + + vcc_csi1: ldo4 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_cpu: dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <2275000>; + regulator-always-on; + }; + + vdd_int: dcdc3 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + ahci_pwr_pin_olinuxinoevb: ahci_pwr_pin@1 { + allwinner,pins = "PC3"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + led_pins_olinuxinoevb: led_pins@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_20_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&reg_ahci_5v { + pinctrl-0 = <&ahci_pwr_pin_olinuxinoevb>; + gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&reg_usb1_vbus { + status = "okay"; +}; + +&reg_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <&reg_usb1_vbus>; + usb2_vbus-supply = <&reg_usb2_vbus>; + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 1b44ce8..6dd55a2 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -45,6 +45,11 @@ F: configs/Ippo_q8h_v1_2_a33_1024x600_defconfig F: include/configs/sun9i.h F: configs/Merrii_A80_Optimus_defconfig +A20-OLINUXINO-EVB BOARD +M: Marcus Cooper <codekipper(a)gmail.com> +S: Maintained +F: configs/A20-OLinuXino-EVB_defconfig + A20-OLINUXINO-LIME BOARD M: FUKAUMI Naoki <naobsd(a)gmail.com> S: Maintained diff --git a/configs/A20-OLinuXino-EVB_defconfig b/configs/A20-OLinuXino-EVB_defconfig new file mode 100644 index 0000000..a4d0978 --- /dev/null +++ b/configs/A20-OLinuXino-EVB_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN7I=y +CONFIG_DRAM_CLK=480 +CONFIG_MMC0_CD_PIN="PH1" +CONFIG_USB0_VBUS_PIN="PB9" +CONFIG_USB0_VBUS_DET="PH5" +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-evb" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_ETH_DESIGNWARE=y +CONFIG_USB_EHCI_HCD=y + -- 2.5.0

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[U-Boot] Building Uboot for Nios2 - linker not found on Linux environment
by Dave Williams 19 Aug '15

19 Aug '15

I am trying to build Uboot for Nios2. I do the following on Linux bash. > git clone git://git.denx.de/u-boot-nios.git > cd u-boot-nios/ > make menuconfig These proceeding steps complete with no visible errors or warnings. > make all This step fails with the following error LD arch/nios2/cpu/built-in.o /bin/sh: nios2-elf-ld.bfd: command not found scripts/Makefile.build:354: recipe for target 'arch/nios2/cpu/built-in.o' failed make[1]: *** [arch/nios2/cpu/built-in.o] Error 127 Makefile:1037: recipe for target 'arch/nios2/cpu' failed make: *** [arch/nios2/cpu] Error 2 I tested to confirm that both 'nios2-elf-gcc' and 'nios2-elf-ld' are in the path and are executable. It appears the compile completed but the nios2 linker is not found. The Nios2 binaries - nios2-elf-gcc and nios2-elf-ld are in same path location. I have been running Nios2 successfully on Linux. Anyone else seen this error or found a workaround? Dave USA

2 2

[U-Boot] [PATCH v7 2/5] nand: lpc32xx: add hardware ECC support
by slemieux.tyco＠gmail.com 19 Aug '15

19 Aug '15

From: Sylvain Lemieux <slemieux(a)tycoint.com> Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP. The code taken from the legacy patch is: - lpc32xx SLC NAND driver (hardware ECC support) - lpc3250 header file missing SLC NAND registers definition The legacy driver was updated and clean-up as part of the integration with the existing NAND SLC driver. Signed-off-by: Sylvain Lemieux <slemieux(a)tycoint.com> --- Changes from v6 to v7: * Rebase the patch on: https://patchwork.ozlabs.org/patch/506182/ * Addressed Vladimir's comments on LPC32xx NAND SLC driver: - The ECC size / bytes are always define for a single step. * Provide a custom version of the hardware ECC "read_page()" and "write_page()" to be able to take advantage of the DMA controller scatter/gather mode through linked list. Changes from v5 to v6: * Addressed Vladimir's comments on LPC32xx NAND SLC driver: - move DMAC registers definitions from NAND SLC to "dma.h". - update NAND SLC to use the new DMA channel API. - generate the fatal BUG on the client side when attempting a transfer on an unallocated DMA channel. - kept the original order for read/write byte/buf functions. * Following feedback on maillist from Vladimir, the following update were done: - the ECC size / ECC bytes are fix to 256 & 3 in the driver. - add comments regarding the ECC correction done by page when using the DMA controller scatter/gather mode through linked list (i.e. ECC correction process). - definition used for managing small vs. large page were updated inside the driver to make them more clear. - definition used for the ECC process when the DMA is enable were updated to avoid any confusion with basic definition. - possible to select small page NAND using a single define. - use define instead of value for internal process logic. Changes from v4 to v5: * Addressed Marek's comments on LPC32xx NAND SLC driver: - Move macro use by the DMA client to write the next DMA linked list item address to NAND SLC driver. * Updated multiline comments style. * Use "uxx" instead of "uintxx_t" (new code), note: keep uintxx_t for API; to match initial patch. Changes from v3 to v4: * No changes. Changes from v2 to v3: * As per feedback on mailing list from Vladimir, - add warning when DMA and SPL build option are selected. - add another DMA specific read and write buffer functions. * Addressed Marek's comments on LPC32xx NAND SLC driver removed typecast and update variable type, when possible. * As per discussion on mailing list with Vladimir & Marek, updated conditional compile option (DMA only) to build the original NAND SLC code using software ECC. * Re-organized the conditional compile code inside "board_nand_init()" - DMA vs. non-DMA initialization. * Added original source code credit (copyright & author). Changes from v1 to v2: * Moved the NAND SLC patch as the second patch of the series. * As per discussion on mailing list with Vladimir, incorporate NAND SLC hardware ECC support into the following NAND SLC patch: https://patchwork.ozlabs.org/patch/497308/ * As per discussion on mailing list with Vladimir & Albert, add conditional compile option to build the original NAND SLC code using software ECC for SPL build. * Removed ECC layout for small page NAND from this patch. Update to the legacy code to integrate with the NAND SLC patch: 1) Fixed checkpatch script output in legacy code. 2) Use u-boot API for register access to remove the volatile in register definition taken from "lpc3250.h" header file. 3) Use register definition from the NAND SLC patch. The legacy BSP patch (u-boot-2009.03_lpc32x0-v1.07.patch.tar.bz2) was downloaded from the LPCLinux Web site. drivers/mtd/nand/lpc32xx_nand_slc.c | 413 +++++++++++++++++++++++++++++++++++- 1 file changed, 409 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c index 719a74d..dbb95d9 100644 --- a/drivers/mtd/nand/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/lpc32xx_nand_slc.c @@ -3,15 +3,29 @@ * * (C) Copyright 2015 Vladimir Zapolskiy <vz(a)mleia.com> * + * Hardware ECC support original source code + * Copyright (C) 2008 by NXP Semiconductors + * Author: Kevin Wells + * + * Copyright (c) 2015 Tyco Fire Protection Products. + * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <nand.h> +#include <linux/mtd/nand_ecc.h> #include <asm/errno.h> #include <asm/io.h> +#include <asm/arch/config.h> #include <asm/arch/clk.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/dma.h> +#include <asm/arch/cpu.h> + +#if defined(CONFIG_DMA_LPC32XX) && defined(CONFIG_SPL_BUILD) +#warning "DMA support in SPL image is not tested" +#endif struct lpc32xx_nand_slc_regs { u32 data; @@ -33,11 +47,18 @@ struct lpc32xx_nand_slc_regs { /* CFG register */ #define CFG_CE_LOW (1 << 5) +#define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */ +#define CFG_ECC_EN (1 << 3) /* ECC enable bit */ +#define CFG_DMA_BURST (1 << 2) /* DMA burst bit */ +#define CFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */ /* CTRL register */ #define CTRL_SW_RESET (1 << 2) +#define CTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */ +#define CTRL_DMA_START (1 << 0) /* Start DMA channel bit */ /* STAT register */ +#define STAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */ #define STAT_NAND_READY (1 << 0) /* INT_STAT register */ @@ -54,6 +75,30 @@ struct lpc32xx_nand_slc_regs { #define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4) #define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0) +#if defined(CONFIG_DMA_LPC32XX) +#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) + +/* + * DMA Descriptors + * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area) + * For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area) + */ +static struct lpc32xx_dmac_ll dmalist[ECCSTEPS * 2 + 1]; +static u32 ecc_buffer[8]; /* MAX ECC size */ +static unsigned int dmachan = (unsigned int)-1; /* Invalid channel */ + +/* + * Helper macro for the DMA client (i.e. NAND SLC): + * - to write the next DMA linked list item address + * (see arch/include/asm/arch-lpc32xx/dma.h). + * - to assign the DMA data register to DMA source or destination address. + * - to assign the ECC register to DMA source or destination address. + */ +#define lpc32xx_dmac_next_lli(x) ((u32)x) +#define lpc32xx_dmac_set_dma_data() ((u32)&lpc32xx_nand_slc_regs->dma_data) +#define lpc32xx_dmac_set_ecc() ((u32)&lpc32xx_nand_slc_regs->ecc) +#endif + static struct lpc32xx_nand_slc_regs __iomem *lpc32xx_nand_slc_regs = (struct lpc32xx_nand_slc_regs __iomem *)SLC_NAND_BASE; @@ -108,28 +153,353 @@ static int lpc32xx_nand_dev_ready(struct mtd_info *mtd) return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY; } +#if defined(CONFIG_DMA_LPC32XX) +/* + * Prepares DMA descriptors for NAND RD/WR operations + * If the size is < 256 Bytes then it is assumed to be + * an OOB transfer + */ +static void lpc32xx_nand_dma_configure(struct nand_chip *chip, + const u8 *buffer, int size, + int read) +{ + u32 i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst; + struct lpc32xx_dmac_ll *dmalist_cur; + struct lpc32xx_dmac_ll *dmalist_cur_ecc; + + /* + * CTRL descriptor entry for reading ECC + * Copy Multiple times to sync DMA with Flash Controller + */ + ecc_ctrl = 0x5 | + DMAC_CHAN_SRC_BURST_1 | + DMAC_CHAN_DEST_BURST_1 | + DMAC_CHAN_SRC_WIDTH_32 | + DMAC_CHAN_DEST_WIDTH_32 | + DMAC_CHAN_DEST_AHB1; + + /* CTRL descriptor entry for reading/writing Data */ + ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) | + DMAC_CHAN_SRC_BURST_4 | + DMAC_CHAN_DEST_BURST_4 | + DMAC_CHAN_SRC_WIDTH_32 | + DMAC_CHAN_DEST_WIDTH_32 | + DMAC_CHAN_DEST_AHB1; + + /* CTRL descriptor entry for reading/writing Spare Area */ + oob_ctrl = (CONFIG_SYS_NAND_OOBSIZE / 4) | + DMAC_CHAN_SRC_BURST_4 | + DMAC_CHAN_DEST_BURST_4 | + DMAC_CHAN_SRC_WIDTH_32 | + DMAC_CHAN_DEST_WIDTH_32 | + DMAC_CHAN_DEST_AHB1; + + if (read) { + dmasrc = lpc32xx_dmac_set_dma_data(); + dmadst = (u32)buffer; + ctrl |= DMAC_CHAN_DEST_AUTOINC; + } else { + dmadst = lpc32xx_dmac_set_dma_data(); + dmasrc = (u32)buffer; + ctrl |= DMAC_CHAN_SRC_AUTOINC; + } + + /* + * Write Operation Sequence for Small Block NAND + * ---------------------------------------------------------- + * 1. X'fer 256 bytes of data from Memory to Flash. + * 2. Copy generated ECC data from Register to Spare Area + * 3. X'fer next 256 bytes of data from Memory to Flash. + * 4. Copy generated ECC data from Register to Spare Area. + * 5. X'fer 16 byets of Spare area from Memory to Flash. + * Read Operation Sequence for Small Block NAND + * ---------------------------------------------------------- + * 1. X'fer 256 bytes of data from Flash to Memory. + * 2. Copy generated ECC data from Register to ECC calc Buffer. + * 3. X'fer next 256 bytes of data from Flash to Memory. + * 4. Copy generated ECC data from Register to ECC calc Buffer. + * 5. X'fer 16 bytes of Spare area from Flash to Memory. + * Write Operation Sequence for Large Block NAND + * ---------------------------------------------------------- + * 1. Steps(1-4) of Write Operations repeate for four times + * which generates 16 DMA descriptors to X'fer 2048 bytes of + * data & 32 bytes of ECC data. + * 2. X'fer 64 bytes of Spare area from Memory to Flash. + * Read Operation Sequence for Large Block NAND + * ---------------------------------------------------------- + * 1. Steps(1-4) of Read Operations repeate for four times + * which generates 16 DMA descriptors to X'fer 2048 bytes of + * data & 32 bytes of ECC data. + * 2. X'fer 64 bytes of Spare area from Flash to Memory. + */ + + for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) { + dmalist_cur = &dmalist[i * 2]; + dmalist_cur_ecc = &dmalist[(i * 2) + 1]; + + dmalist_cur->dma_src = (read ? (dmasrc) : (dmasrc + (i*256))); + dmalist_cur->dma_dest = (read ? (dmadst + (i*256)) : dmadst); + dmalist_cur->next_lli = lpc32xx_dmac_next_lli(dmalist_cur_ecc); + dmalist_cur->next_ctrl = ctrl; + + dmalist_cur_ecc->dma_src = lpc32xx_dmac_set_ecc(); + dmalist_cur_ecc->dma_dest = (u32)&ecc_buffer[i]; + dmalist_cur_ecc->next_lli = + lpc32xx_dmac_next_lli(&dmalist[(i * 2) + 2]); + dmalist_cur_ecc->next_ctrl = ecc_ctrl; + } + + if (i) { /* Data only transfer */ + dmalist_cur_ecc = &dmalist[(i * 2) - 1]; + dmalist_cur_ecc->next_lli = 0; + dmalist_cur_ecc->next_ctrl |= DMAC_CHAN_INT_TC_EN; + return; + } + + /* OOB only transfer */ + if (read) { + dmasrc = lpc32xx_dmac_set_dma_data(); + dmadst = (u32)buffer; + oob_ctrl |= DMAC_CHAN_DEST_AUTOINC; + } else { + dmadst = lpc32xx_dmac_set_dma_data(); + dmasrc = (u32)buffer; + oob_ctrl |= DMAC_CHAN_SRC_AUTOINC; + } + + /* Read/ Write Spare Area Data To/From Flash */ + dmalist_cur = &dmalist[i * 2]; + dmalist_cur->dma_src = dmasrc; + dmalist_cur->dma_dest = dmadst; + dmalist_cur->next_lli = 0; + dmalist_cur->next_ctrl = (oob_ctrl | DMAC_CHAN_INT_TC_EN); +} + +static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf, + int len, int read) +{ + struct nand_chip *chip = mtd->priv; + u32 config; + int ret; + + /* DMA Channel Configuration */ + config = (read ? DMAC_CHAN_FLOW_D_P2M : DMAC_CHAN_FLOW_D_M2P) | + (read ? DMAC_DEST_PERIP(0) : DMAC_DEST_PERIP(DMA_PERID_NAND1)) | + (read ? DMAC_SRC_PERIP(DMA_PERID_NAND1) : DMAC_SRC_PERIP(0)) | + DMAC_CHAN_ENABLE; + + /* Prepare DMA descriptors */ + lpc32xx_nand_dma_configure(chip, buf, len, read); + + /* Setup SLC controller and start transfer */ + if (read) + setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR); + else /* NAND_ECC_WRITE */ + clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR); + setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_BURST); + + /* Write length for new transfers */ + if (!((readl(&lpc32xx_nand_slc_regs->stat) & STAT_DMA_FIFO) | + readl(&lpc32xx_nand_slc_regs->tc))) { + int tmp = (len != mtd->oobsize) ? mtd->oobsize : 0; + writel(len + tmp, &lpc32xx_nand_slc_regs->tc); + } + + setbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START); + + /* Start DMA transfers */ + ret = lpc32xx_dma_start_xfer(dmachan, dmalist, config); + if (unlikely(ret < 0)) + BUG(); + + + /* Wait for NAND to be ready */ + while (!lpc32xx_nand_dev_ready(mtd)) + ; + + /* Wait till DMA transfer is DONE */ + if (lpc32xx_dma_wait_status(dmachan)) + pr_err("NAND DMA transfer error!\r\n"); + + /* Stop DMA & HW ECC */ + clrbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START); + clrbits_le32(&lpc32xx_nand_slc_regs->cfg, + CFG_DMA_DIR | CFG_DMA_BURST | CFG_ECC_EN | CFG_DMA_ECC); +} + +static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count) +{ + int i; + for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES); + i += CONFIG_SYS_NAND_ECCBYTES) { + u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES]; + ce = ~(ce << 2) & 0xFFFFFF; + spare[i+2] = (u8)(ce & 0xFF); ce >>= 8; + spare[i+1] = (u8)(ce & 0xFF); ce >>= 8; + spare[i] = (u8)(ce & 0xFF); + } + return 0; +} + +static int lpc32xx_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc_code) +{ + return slc_ecc_copy_to_buffer(ecc_code, ecc_buffer, ECCSTEPS); +} + +/* + * Enables and prepares SLC NAND controller + * for doing data transfers with H/W ECC enabled. + */ +static void lpc32xx_hwecc_enable(struct mtd_info *mtd, int mode) +{ + /* Clear ECC */ + writel(CTRL_ECC_CLEAR, &lpc32xx_nand_slc_regs->ctrl); + + /* Setup SLC controller for H/W ECC operations */ + setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_ECC_EN | CFG_DMA_ECC); +} + +/* + * lpc32xx_correct_data - [NAND Interface] Detect and correct bit error(s) + * mtd: MTD block structure + * dat: raw data read from the chip + * read_ecc: ECC from the chip + * calc_ecc: the ECC calculated from raw data + * + * Detect and correct a 1 bit error for 256 byte block + */ +int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + unsigned int i; + int ret1, ret2 = 0; + u_char *r = read_ecc; + u_char *c = calc_ecc; + u16 data_offset = 0; + + for (i = 0 ; i < ECCSTEPS ; i++) { + r += CONFIG_SYS_NAND_ECCBYTES; + c += CONFIG_SYS_NAND_ECCBYTES; + data_offset += CONFIG_SYS_NAND_ECCSIZE; + + ret1 = nand_correct_data(mtd, dat + data_offset, r, c); + if (ret1 < 0) + return -EBADMSG; + else + ret2 += ret1; + } + + return ret2; +} +#endif + +#if defined(CONFIG_DMA_LPC32XX) +static void lpc32xx_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + lpc32xx_nand_xfer(mtd, buf, len, 1); +} +#else static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { while (len-- > 0) *buf++ = readl(&lpc32xx_nand_slc_regs->data); } +#endif static uint8_t lpc32xx_read_byte(struct mtd_info *mtd) { return readl(&lpc32xx_nand_slc_regs->data); } +#if defined(CONFIG_DMA_LPC32XX) +static void lpc32xx_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf, + int len) +{ + lpc32xx_nand_xfer(mtd, buf, len, 0); +} +#else static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { while (len-- > 0) writel(*buf++, &lpc32xx_nand_slc_regs->data); } +#endif static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte) { writel(byte, &lpc32xx_nand_slc_regs->data); } +#if defined(CONFIG_DMA_LPC32XX) +/* Reuse the logic from "nand_read_page_hwecc()" */ +static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int oob_required, int page) +{ + int i; + int stat; + uint8_t *p = buf; + uint8_t *ecc_calc = chip->buffers->ecccalc; + uint8_t *ecc_code = chip->buffers->ecccode; + uint32_t *eccpos = chip->ecc.layout->eccpos; + unsigned int max_bitflips = 0; + + /* + * As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes + * and section 9.7, the NAND SLC & DMA allowed single DMA transaction + * of a page size using DMA controller scatter/gather mode through + * linked list; the ECC read is done without any software intervention. + */ + + lpc32xx_hwecc_enable(mtd, NAND_ECC_READ); + lpc32xx_dma_read_buf(mtd, p, chip->ecc.size * chip->ecc.steps); + lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]); + lpc32xx_dma_read_buf(mtd, chip->oob_poi, mtd->oobsize); + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = chip->oob_poi[eccpos[i]]; + + stat = chip->ecc.correct(mtd, p, &ecc_code[0], &ecc_calc[0]); + if (stat < 0) + mtd->ecc_stats.failed++; + else { + mtd->ecc_stats.corrected += stat; + max_bitflips = max_t(unsigned int, max_bitflips, stat); + } + + return max_bitflips; +} + +/* Reuse the logic from "nand_write_page_hwecc()" */ +static int lpc32xx_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf, int oob_required) +{ + int i; + uint8_t *ecc_calc = chip->buffers->ecccalc; + const uint8_t *p = buf; + uint32_t *eccpos = chip->ecc.layout->eccpos; + + /* + * As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes + * and section 9.7, the NAND SLC & DMA allowed single DMA transaction + * of a page size using DMA controller scatter/gather mode through + * linked list; the ECC read is done without any software intervention. + */ + + lpc32xx_hwecc_enable(mtd, NAND_ECC_WRITE); + lpc32xx_dma_write_buf(mtd, p, chip->ecc.size * chip->ecc.steps); + lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]); + + for (i = 0; i < chip->ecc.total; i++) + chip->oob_poi[eccpos[i]] = ecc_calc[i]; + + lpc32xx_dma_write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; +} +#endif + /* * LPC32xx has only one SLC NAND controller, don't utilize * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function @@ -137,10 +507,46 @@ static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte) */ int board_nand_init(struct nand_chip *lpc32xx_chip) { +#if defined(CONFIG_DMA_LPC32XX) + int ret; + + /* Acquire a channel for our use */ + ret = lpc32xx_dma_get_channel(); + if (unlikely(ret < 0)) { + pr_info("Unable to get free DMA channel for NAND transfers\n"); + return -1; + } + dmachan = (unsigned int)ret; +#endif + lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl; lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready; /* + * The implementation of these functions is quite common, but + * they MUST be defined, because access to data register + * is strictly 32-bit aligned. + */ + lpc32xx_chip->read_byte = lpc32xx_read_byte; + lpc32xx_chip->write_byte = lpc32xx_write_byte; + +#if defined(CONFIG_DMA_LPC32XX) + /* Hardware ECC calculation is supported when DMA driver is selected */ + lpc32xx_chip->ecc.mode = NAND_ECC_HW; + + lpc32xx_chip->read_buf = lpc32xx_dma_read_buf; + lpc32xx_chip->write_buf = lpc32xx_dma_write_buf; + + lpc32xx_chip->ecc.calculate = lpc32xx_ecc_calculate; + lpc32xx_chip->ecc.correct = lpc32xx_correct_data; + lpc32xx_chip->ecc.hwctl = lpc32xx_hwecc_enable; + lpc32xx_chip->chip_delay = 2000; + + lpc32xx_chip->ecc.read_page = lpc32xx_read_page_hwecc; + lpc32xx_chip->ecc.write_page = lpc32xx_write_page_hwecc; + lpc32xx_chip->options |= NAND_NO_SUBPAGE_WRITE; +#else + /* * Hardware ECC calculation is not supported by the driver, * because it requires DMA support, see LPC32x0 User Manual, * note after SLC_ECC register description (UM10326, p.198) @@ -153,16 +559,15 @@ int board_nand_init(struct nand_chip *lpc32xx_chip) * is strictly 32-bit aligned. */ lpc32xx_chip->read_buf = lpc32xx_read_buf; - lpc32xx_chip->read_byte = lpc32xx_read_byte; lpc32xx_chip->write_buf = lpc32xx_write_buf; - lpc32xx_chip->write_byte = lpc32xx_write_byte; +#endif /* * Use default ECC layout, but these values are predefined * for both small and large page NAND flash devices. */ - lpc32xx_chip->ecc.size = 256; - lpc32xx_chip->ecc.bytes = 3; + lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE; + lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; lpc32xx_chip->ecc.strength = 1; #if defined(CONFIG_SYS_NAND_USE_FLASH_BBT) -- 1.8.3.1

4 4

[U-Boot] [PATCH v6 4/6] net: e1000: Add Kconfig options
by Simon Glass 19 Aug '15

19 Aug '15

Add Kconfig options in preparation for moving boards to use Kconfig. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v6: - Drop CONFIG_E1000_FALLBACK_MAC option from README Changes in v5: None Changes in v4: None Changes in v3: - Drop CONFIG_E1000_FALLBACK_MAC option Changes in v2: - Move the Kconfig additions to a new patch README | 3 --- drivers/net/Kconfig | 32 ++++++++++++++++++++++++++++++++ drivers/net/e1000.c | 7 ------- 3 files changed, 32 insertions(+), 10 deletions(-) diff --git a/README b/README index 95f2d9d..a52ff46 100644 --- a/README +++ b/README @@ -1382,9 +1382,6 @@ The following options need to be configured: Management command for E1000 devices. When used on devices with SPI support you can reprogram the EEPROM from U-Boot. - CONFIG_E1000_FALLBACK_MAC - default MAC for empty EEPROM after production. - CONFIG_EEPRO100 Support for Intel 82557/82559/82559ER chips. Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index ce76a02..7367d9e 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -20,6 +20,38 @@ menuconfig NETDEVICES if NETDEVICES +config E1000 + bool "Intel PRO/1000 Gigabit Ethernet support" + help + This driver supports Intel(R) PRO/1000 gigabit ethernet family of + adapters. For more information on how to identify your adapter, go + to the Adapter & Driver ID Guide at: + + <http://support.intel.com/support/network/adapter/pro100/21397.htm> + +config E1000_SPI_GENERIC + bool "Allow access to the Intel 8257x SPI bus" + depends on E1000 + help + Allow generic access to the SPI bus on the Intel 8257x, for + example with the "sspi" command. + +config E1000_SPI + bool "Enable SPI bus utility code" + depends on E1000 + help + Utility code for direct access to the SPI bus on Intel 8257x. + This does not do anything useful unless you set at least one + of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC. + +config CMD_E1000 + bool "Enable the e1000 command" + depends on E1000 + help + This enables the 'e1000' management command for E1000 devices. When + used on devices with SPI support you can reprogram the EEPROM from + U-Boot. + config ETH_SANDBOX depends on DM_ETH && SANDBOX default y diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 3b4177a..fdda139 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -1221,13 +1221,6 @@ e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6]) if (e1000_is_second_port(hw)) enetaddr[5] ^= 1; -#ifdef CONFIG_E1000_FALLBACK_MAC - if (!is_valid_ethaddr(nic->enetaddr)) { - unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; - - memcpy(enetaddr, fb_mac, NODE_ADDRESS_SIZE); - } -#endif return 0; } #endif -- 2.5.0.276.gf5e568e

2 2

[U-Boot] [PATCH v3] ARM: tegra: Add Tegra20 SPI device nodes
by Mirza Krak 19 Aug '15

19 Aug '15

From: Mirza Krak <mirza.krak(a)hostmobility.com> Add the device tree node for the SPI controllers found on Tegra20 SOCs. Signed-off-by: Mirza Krak <mirza.krak(a)hostmobility.com> --- Changes in v2: * Dropped tegra30-slink compatible string, based on comment from Thierry Reding on v1 patch Changes in v3: * Copy/paste spi device nodes from Linux (4.1.6) Did an attempt of copying tegra20.dtsi from Linux but it broke USB and LCD from what I could see on my Colibri T20, and I dropped that as it was out of scope of my patch. arch/arm/dts/tegra20.dtsi | 57 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index b8c8a923017e..e68d7be4785f 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -320,6 +320,63 @@ clocks = <&tegra_car 47>, <&tegra_car 124>; }; + spi@7000d400 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d400 0x200>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC1>; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d600 0x200>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC2>; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d800 0x200>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC3>; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000da00 0x200>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC4>; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + kbc@7000e200 { compatible = "nvidia,tegra20-kbc"; reg = <0x7000e200 0x0078>; -- 2.1.0

1 0

[U-Boot] malloc_simple: Allow malloc_simple to be used with non stack RAM
by Hans de Goede 19 Aug '15

19 Aug '15

Hi Tom and Simon, Here is an old patch of mine, which at the time I send it got reviewed by Simon, but never got merged. I've just brushed this patch of, because it shrinks the SPL by about 3k, and with the spl nand support we've recently added we are going over the size limit with the SPL on some sunxi boards. So I would like to see this merged. Simon, does your ack still stand for this patch ? Tom, if so can you merge this please ? Note this patch has close to 0 chance of causing regressions as it is a nop unless the new CONFIG_SYS_MALLOC_F_BASE define is defined. Patch 2 / 3 are merely added as example / for Ian to review :) I will merge these through the sunxi tree once patch 1 is merged. Thanks & Regards, Hans

3 10

Re: [U-Boot] [v2] net/fman: Support both new and legacy FMan Compatibles
by Xing Lei 19 Aug '15

19 Aug '15

Verified 1G and 10G, the patch is working on all tested platforms: B4860QDS, P2041RDB, P3041DS, P4080DS, P5020DS, P5040DS, T1024RDB, T1040RDB, T2080RDB, T4240QDS. Tested-by: Xing Lei <xing.lei(a)freescale.com<mailto:xing.lei@freescale.com>>

1 0

[U-Boot] [PATCH 1/3] ARM: at91: sama5: move the sd/mmc env config to at91-sama5_common.h
by Josh Wu 19 Aug '15

19 Aug '15

As almost all sama5 sd/mmc env configurations are same, so move them to at91-sama5_common.h. Also we define a KERNEL_DTB_FILE_NAME as dtb file name for different board. Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- Hi, Those patches depends on the patch: http://patchwork.ozlabs.org/patch/485339/ Best Regards, Josh Wu include/configs/at91-sama5_common.h | 17 +++++++++++++++++ include/configs/sama5d3_xplained.h | 12 +++--------- include/configs/sama5d3xek.h | 10 +--------- include/configs/sama5d4_xplained.h | 20 +++----------------- include/configs/sama5d4ek.h | 18 +++--------------- 5 files changed, 27 insertions(+), 50 deletions(-) diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 9289964..99fa0b1 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -56,6 +56,23 @@ #define CONFIG_CMD_DHCP #ifdef CONFIG_SYS_USE_MMC +/* u-boot env in sd/mmc card */ +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_SIZE 0x4000 + +#ifdef KERNEL_DTB_FILE_NAME +#define CONFIG_BOOT_DTB_COMMAND "fatload mmc 0:1 0x21000000 " KERNEL_DTB_FILE_NAME "; " +#else +#define CONFIG_BOOT_DTB_COMMAND "fatload mmc 0:1 0x21000000 ${ek_name}.dtb; " +#endif + +#define CONFIG_BOOTCOMMAND CONFIG_BOOT_DTB_COMMAND \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk " \ "root=/dev/mmcblk0p2 rw rootwait" diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index c4141a0..e5de24b 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -13,6 +13,8 @@ /* No NOR flash, this definition should put before common header */ #define CONFIG_SYS_NO_FLASH +#define KERNEL_DTB_FILE_NAME "at91-sama5d3_xplained.dtb" + #include "at91-sama5_common.h" /* serial console */ @@ -124,15 +126,7 @@ "nand read 0x22000000 0x200000 0x600000;" \ "bootz 0x22000000 - 0x21000000" #elif CONFIG_SYS_USE_MMC -/* bootstrap + u-boot + env in sd card */ -#define CONFIG_ENV_IS_IN_FAT -#define FAT_ENV_INTERFACE "mmc" -#define FAT_ENV_FILE "uboot.env" -#define FAT_ENV_DEVICE_AND_PART "0" -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for sd/mmc env */ #else #define CONFIG_ENV_IS_NOWHERE #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 344ae9c..71441a4 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -176,15 +176,7 @@ "nand read 0x22000000 0x200000 0x600000;" \ "bootm 0x22000000 - 0x21000000" #elif CONFIG_SYS_USE_MMC -/* bootstrap + u-boot + env in sd card */ -#define CONFIG_ENV_IS_IN_FAT -#define FAT_ENV_INTERFACE "mmc" -#define FAT_ENV_FILE "uboot.env" -#define FAT_ENV_DEVICE_AND_PART "0" -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 ${ek_name}.dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootm 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for sd/mmc env */ #else #define CONFIG_ENV_IS_NOWHERE #endif diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 5fb621e..a7d9e78 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -13,6 +13,8 @@ /* No NOR flash, this definition should put before common header */ #define CONFIG_SYS_NO_FLASH +#define KERNEL_DTB_FILE_NAME "at91-sama5d4_xplained.dtb" + #include "at91-sama5_common.h" /* serial console */ @@ -139,25 +141,9 @@ "nand read 0x22000000 0x200000 0x600000;" \ "bootz 0x22000000 - 0x21000000" #elif CONFIG_SYS_USE_MMC -/* bootstrap + u-boot + env in sd card */ -#define CONFIG_ENV_IS_IN_FAT -#define CONFIG_FAT_WRITE -#define FAT_ENV_INTERFACE "mmc" -/* - * We don't specify the part number, if device 0 has partition table, it means - * the first partition; it no partition table, then take whole device as a - * FAT file system. - */ -#define FAT_ENV_DEVICE_AND_PART "0" -#define FAT_ENV_FILE "uboot.env" -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d4_xplained.dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for sd/mmc env */ #endif - - /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x200000 diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 546d7a3..8ecb6d3 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -13,6 +13,8 @@ /* No NOR flash, this definition should put before common header */ #define CONFIG_SYS_NO_FLASH +#define KERNEL_DTB_FILE_NAME "sama5d4ek.dtb" + #include "at91-sama5_common.h" /* serial console */ @@ -137,21 +139,7 @@ "nand read 0x22000000 0x200000 0x600000;" \ "bootz 0x22000000 - 0x21000000" #elif CONFIG_SYS_USE_MMC -/* bootstrap + u-boot + env in sd card */ -#define CONFIG_ENV_IS_IN_FAT -#define CONFIG_FAT_WRITE -#define FAT_ENV_INTERFACE "mmc" -/* - * We don't specify the part number, if device 0 has partition table, it means - * the first partition; it no partition table, then take whole device as a - * FAT file system. - */ -#define FAT_ENV_DEVICE_AND_PART "0" -#define FAT_ENV_FILE "uboot.env" -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 sama5d4ek.dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for sd/mmc env */ #endif /* SPL */ -- 1.9.1

3 6

[U-Boot] [PATCH 1/3] arm: Add SYS_L2CACHE_OFF Kconfig entry
by Peng Fan 19 Aug '15

19 Aug '15

To i.MX6UL, SYS_L2CACHE_OFF is selected, but there is no Kconfig entry for SYS_L2CACHE_OFF. Then "select SYS_L2CACHE_OFF" does not effect for i.MX6UL, which is not expected. Since SYS_L2CACHE_OFF is mainly used by ARM architecture, add it to arch/arm/Kconfig. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Tom Rini <trini(a)konsulko.com> Cc: Stefano Babic <sbabic(a)denx.de> --- Hi, I worked this patch based on imx tree, since mainly for i.MX6UL. Then can this patch go through imx tree to avoid break i.MX6UL? This option does not impact others which defined CONFIG_SYS_L2CACHE_OFF in board header file. arch/arm/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9a01c5c..ad8f796 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -62,6 +62,12 @@ config SEMIHOSTING the hosted environment to call out to the emulator to retrieve files from the host machine. +config SYS_L2CACHE_OFF + bool "L2cache off" + help + If SoC does not support L2CACHE or one do not want to enable + L2CACHE, choose this option. + choice prompt "Target select" optional -- 1.8.4

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[U-Boot] [PATCH] ARM: at91: sama5d3xek: initialized a variable:ek_name in U-Boot
by Josh Wu 19 Aug '15

19 Aug '15

Then we can use this ek_name variable to load corresponding dtb file in mmc boot. Also we change the mmc boot command to load zImage as this format is prefered. Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- board/atmel/sama5d3xek/sama5d3xek.c | 21 +++++++++++++++++++++ include/configs/sama5d3xek.h | 7 +++++-- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index cf6ed8b..8408b2b 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -15,6 +15,7 @@ #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <lcd.h> +#include <linux/ctype.h> #include <atmel_hlcdc.h> #include <atmel_mci.h> #include <phy.h> @@ -369,6 +370,26 @@ void spi_cs_deactivate(struct spi_slave *slave) } #endif /* CONFIG_ATMEL_SPI */ +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + const char *BOARD_EK_NAME = "ek_name"; + const int MAX_STR_LEN = 32; + char name[MAX_STR_LEN], *p; + int i; + + strncpy(name, get_cpu_name(), MAX_STR_LEN); + for (i = 0, p = name; *p != '\0' || i < MAX_STR_LEN; i++, p++) + *p = tolower(*p); + + strcat(name, "ek"); + setenv(BOARD_EK_NAME, name); +#endif + return 0; +} +#endif + /* SPL */ #ifdef CONFIG_SPL_BUILD void spl_board_init(void) diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index d933a9e..344ae9c 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -19,6 +19,9 @@ */ #include "at91-sama5_common.h" +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + /* serial console */ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU @@ -179,8 +182,8 @@ #define FAT_ENV_FILE "uboot.env" #define FAT_ENV_DEVICE_AND_PART "0" #define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \ - "fatload mmc 0:1 0x22000000 uImage; " \ +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 ${ek_name}.dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ "bootm 0x22000000 - 0x21000000" #else #define CONFIG_ENV_IS_NOWHERE -- 1.9.1

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