August 2015 - U-Boot

[U-Boot] [PATCH] arm: socfpga: Fix delay in clock manager
by Marek Vasut 19 Aug '15

19 Aug '15

This code claims it needs to wait 7us, yet it uses get_timer() function which operates with millisecond granularity. Use timer_get_us() instead, which operates with microsecond granularity. Signed-off-by: Marek Vasut <marex(a)denx.de> --- arch/arm/mach-socfpga/clock_manager.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 1341df4..aa71636 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -90,7 +90,7 @@ static void cm_write_with_phase(uint32_t value, void cm_basic_init(const struct cm_config * const cfg) { - uint32_t start, timeout; + unsigned long end; /* Start by being paranoid and gate all sw managed clocks */ @@ -159,12 +159,10 @@ void cm_basic_init(const struct cm_config * const cfg) writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); /* - * Time starts here - * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1) + * Time starts here. Must wait 7 us from + * BGPWRDN_SET(0) to VCO_ENABLE_SET(1). */ - start = get_timer(0); - /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */ - timeout = 7; + end = timer_get_us() + 7; /* main mpu */ writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); @@ -204,7 +202,7 @@ void cm_basic_init(const struct cm_config * const cfg) writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); /* 7 us must have elapsed before we can enable the VCO */ - while (get_timer(start) < timeout) + while (timer_get_us() < end) ; /* Enable vco */ -- 2.1.4

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[U-Boot] [PATCH] arm: socfpga: Make the DT mmc node consistent
by Marek Vasut 19 Aug '15

19 Aug '15

The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node. This makes aliases not very usable, so make everything into mmc0. Moreover, zap the useless mmc alias while at this. Signed-off-by: Marek Vasut <marex(a)denx.de> --- arch/arm/dts/socfpga.dtsi | 3 +-- arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 125034b..8588221 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -23,7 +23,6 @@ spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; - mmc = &mmc; }; cpus { @@ -624,7 +623,7 @@ arm,data-latency = <2 1 1>; }; - mmc: dwmmc0@ff704000 { + mmc0: dwmmc0@ff704000 { compatible = "altr,socfpga-dw-mshc"; reg = <0xff704000 0x1000>; interrupts = <0 139 4>; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 00b1830..3c98558 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -34,7 +34,7 @@ }; }; -&mmc { +&mmc0 { status = "okay"; }; -- 2.1.4

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[U-Boot] [PATCH] arm: socfpga: Do not enable gmac1 in Cyclone V dtsi
by Marek Vasut 19 Aug '15

19 Aug '15

The GMAC which is enabled is purely board property, so do not enable arbitrary GMAC in DT include files. Same goes for PHY mode, which is again a board property. The CycloneV SoCDK does this correctly, but SoCrates doesn't. This bug never manifested itself though, since all the boards ever used the GMAC1 . This bug manifests itself only on boards that utilise GMAC0. Signed-off-by: Marek Vasut <marex(a)denx.de> --- arch/arm/dts/socfpga_cyclone5.dtsi | 6 ------ arch/arm/dts/socfpga_cyclone5_socrates.dts | 1 + 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi index 234a901..de36209 100644 --- a/arch/arm/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -27,12 +27,6 @@ cap-sd-highspeed; }; - ethernet@ff702000 { - phy-mode = "rgmii"; - phy-addr = <0xffffffff>; /* probe for phy addr */ - status = "okay"; - }; - sysmgr@ffd08000 { cpu1-start-addr = <0xffd080c4>; }; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 3c98558..6782691 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -23,6 +23,7 @@ &gmac1 { status = "okay"; + phy-mode = "rgmii"; }; &i2c0 { -- 2.1.4

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[U-Boot] [PATCH v3] usb: xhci: Fix a potential NULL pointer dereference
by Sergey Temerkhanov 19 Aug '15

19 Aug '15

This patch fixes a potential NULL pointer dereference arising on non-present/non-initialized xHCI controllers and adds some error handling to xHCI code Signed-off-by: Sergey Temerkhanov <s.temerkhanov(a)gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla(a)cavium.com> --- Changes in v3: - Assign NULL to *controller so it remains that in case of an error Changes in v2: - Add return value check with setting hccr and hcor to NULL drivers/usb/host/xhci.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 0b09643..307e1a6 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -199,7 +199,7 @@ int xhci_reset(struct xhci_hcor *hcor) int ret; /* Halting the Host first */ - debug("// Halt the HC\n"); + debug("// Halt the HC: %p\n", hcor); state = xhci_readl(&hcor->or_usbsts) & STS_HALT; if (!state) { cmd = xhci_readl(&hcor->or_usbcmd); @@ -1064,6 +1064,8 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) struct xhci_ctrl *ctrl; int ret; + *controller = NULL; + if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0) return -ENODEV; @@ -1077,7 +1079,12 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) ret = xhci_lowlevel_init(ctrl); - *controller = &xhcic[index]; + if (ret) { + ctrl->hccr = NULL; + ctrl->hcor = NULL; + } else { + *controller = &xhcic[index]; + } return ret; } @@ -1093,9 +1100,11 @@ int usb_lowlevel_stop(int index) { struct xhci_ctrl *ctrl = (xhcic + index); - xhci_lowlevel_stop(ctrl); - xhci_hcd_stop(index); - xhci_cleanup(ctrl); + if (ctrl->hcor) { + xhci_lowlevel_stop(ctrl); + xhci_hcd_stop(index); + xhci_cleanup(ctrl); + } return 0; } -- 2.2.0

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[U-Boot] [PATCH] drivers: watchdog: add MAX6373 WDT support
by rnd4＠dave-tech.it 18 Aug '15

18 Aug '15

From: Andrea Scian <andrea.scian(a)dave.eu> MAX6373 is a simple WDT which is programmed its configuration pins and reset via another pin, which is usually connected to a GPIO Signed-off-by: Andrea Scian <andrea.scian(a)dave.eu> --- drivers/watchdog/Makefile | 1 + drivers/watchdog/max6373_wdt.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 drivers/watchdog/max6373_wdt.c diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0276a10..6826100 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o +obj-$(CONFIG_MAX6373_WATCHDOG) += max6373_wdt.o diff --git a/drivers/watchdog/max6373_wdt.c b/drivers/watchdog/max6373_wdt.c new file mode 100644 index 0000000..cda46af --- /dev/null +++ b/drivers/watchdog/max6373_wdt.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015 DAVE Embedded Systems <devel(a)dave.eu> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * MAX6373 is a WDT which uses a simple GPIO to reset its timeout + * + * Use CONFIG_MAX6373_WDT_GPIO to define the GPIO number to use + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <watchdog.h> + +#ifndef CONFIG_MAX6373_WDT_GPIO +#error "Please use CONFIG_MAX6373_WDT_GPIO to define which GPIO to use" +#endif + +void hw_watchdog_reset(void) +{ + gpio_set_value(CONFIG_MAX6373_WDT_GPIO, + !gpio_get_value(CONFIG_MAX6373_WDT_GPIO)); +} + +void hw_watchdog_init(void) +{ + if (gpio_request(CONFIG_MAX6373_WDT_GPIO, "MAX6373 WDT")) { + printf("Cannot request GPIO %d for MAX6373 WDT\n", + CONFIG_MAX6373_WDT_GPIO); + return; + } + gpio_direction_output(CONFIG_MAX6373_WDT_GPIO, 1); +} -- 1.7.9.5

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[U-Boot] [PATCH 1/3] armv7/fsl-ls102xa: Workaround for DDR erratum A008514
by Yuan Yao 18 Aug '15

18 Aug '15

Affects: DDR Description: Memory controller performance is not optimal with default internal target queue register values. Impact: Memory controller performance is not optimal. Workaround: Write a value of 63b2_0002h to address: 157_020Ch. Signed-off-by: Yuan Yao <yao.yuan(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- board/freescale/ls1021aqds/ls1021aqds.c | 10 ++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 10 ++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index d34044a..21bd65b 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -221,7 +221,7 @@ struct ccsr_scfg { u32 scfgrevcr; u32 coresrencr; u32 pex2pmrdsr; - u32 ddrc1cr; + u32 eddrtqcfg; u32 ddrc2cr; u32 ddrc3cr; u32 ddrc4cr; diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d6ef6ba..52bffc8 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -299,6 +299,16 @@ int board_early_init_f(void) out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); /* + * Memory controller require a register write before being enabled. + * Affects: DDR + * Register: EDDRTQCFG + * Description: Memory controller performance is not optimal with + * default internal target queue register values. + * Workaround: Write a value of 63b2_0002h to address: 157_020Ch. + */ + out_be32(&scfg->eddrtqcfg, 0x63b20002); + + /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */ diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b7458a9..c565e91 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -501,6 +501,16 @@ int board_early_init_f(void) out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); /* + * Memory controller require a register write before being enabled. + * Affects: DDR + * Register: EDDRTQCFG + * Description: Memory controller performance is not optimal with + * default internal target queue register values. + * Workaround: Write a value of 63b2_0002h to address: 157_020Ch. + */ + out_be32(&scfg->eddrtqcfg, 0x63b20002); + + /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] i2c: lpc32xx: correct sanity check for requested bus speed
by Vladimir Zapolskiy 18 Aug '15

18 Aug '15

LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit wide. This means that if HCLK is 104MHz, then minimal configurable I2C clock speed is about 51KHz. Only USB OTG I2C bus controller CLK registers are 8 bit wide, thus in assumption that peripheral clock is 13MHz it allows to set the minimal bus speed about 25.5KHz. Check for negative half clock value is removed since it is always false. The change fixes the following problem for I2C busses 0 and 1: => i2c dev 0 Setting bus to 0 => i2c speed 100000 Setting bus speed to 100000 Hz Failure changing bus speed (-22) Signed-off-by: Vladimir Zapolskiy <vz(a)mleia.com> --- The change is based on * https://patchwork.ozlabs.org/patch/503817/ * https://patchwork.ozlabs.org/patch/500511/ drivers/i2c/lpc32xx_i2c.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c index be166b0..6c8b504 100644 --- a/drivers/i2c/lpc32xx_i2c.c +++ b/drivers/i2c/lpc32xx_i2c.c @@ -69,20 +69,20 @@ static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap, unsigned int speed) { int half_period; - int clk_rate; if (speed == 0) return -EINVAL; - if (adap->hwadapnr == 2) - /* OTG I2C clock source is different. */ - clk_rate = get_periph_clk_rate(); - else - clk_rate = get_hclk_clk_rate(); - half_period = (clk_rate / speed) / 2; - - if ((half_period > 255) || (half_period < 0)) - return -EINVAL; + /* OTG I2C clock source and CLK registers are different */ + if (adap->hwadapnr == 2) { + half_period = (get_periph_clk_rate() / speed) / 2; + if (half_period > 0xFF) + return -EINVAL; + } else { + half_period = (get_hclk_clk_rate() / speed) / 2; + if (half_period > 0x3FF) + return -EINVAL; + } writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_hi); writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_lo); @@ -97,7 +97,7 @@ static void _i2c_init(struct i2c_adapter *adap, /* soft reset (auto-clears) */ writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl); - /* set HI and LO periods for about 350 kHz */ + /* set HI and LO periods for half of the default speed */ lpc32xx_i2c_set_bus_speed(adap, requested_speed); } -- 2.1.4

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[U-Boot] [PATCH] lpc32xx: add common USB OHCI defines for all LPC32xx boards
by Vladimir Zapolskiy 18 Aug '15

18 Aug '15

The change adds a number of macro definitions used by USB OHCI driver, if CONFIG_USB_OHCI_LPC32XX is selected from a board config file. Signed-off-by: Vladimir Zapolskiy <vz(a)mleia.com> --- Based on https://patchwork.ozlabs.org/patch/505605/ work, but there is no compilation or merge dependency. arch/arm/include/asm/arch-lpc32xx/config.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index d161ad2..2d082ef 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -90,4 +90,13 @@ #define CONFIG_SYS_FLASH_PROTECTION #endif +/* USB OHCI */ +#if defined(CONFIG_USB_OHCI_LPC32XX) +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci" +#endif + #endif /* _LPC32XX_CONFIG_H */ -- 2.1.4

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[U-Boot] [PATCH] lpc32xx: move common SLC NAND defines to arch/config.h
by Vladimir Zapolskiy 18 Aug '15

18 Aug '15

A number of LPC32xx SLC NAND defines is dictated by controller hardware limits and OOB layout is defined by operating system, the definitions are common for all users. Since those macro are used in out of NAND SLC driver code (simple NAND SPL framework), they can not be placed into the driver, therefore move them from board config files to arch/config.h The change also adds OOB layout details specific to small page NAND devices taken from Linux kernel. Signed-off-by: Vladimir Zapolskiy <vz(a)mleia.com> --- The change is based on * https://patchwork.ozlabs.org/patch/497298/ * https://patchwork.ozlabs.org/patch/497299/ arch/arm/include/asm/arch-lpc32xx/config.h | 29 +++++++++++++++++++++++++++++ include/configs/devkit3250.h | 14 +++----------- 2 files changed, 32 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index d57bc48..d161ad2 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -55,6 +55,35 @@ /* Ethernet */ #define LPC32XX_ETH_BASE ETHERNET_BASE +/* NAND */ +#if defined(CONFIG_NAND_LPC32XX_SLC) +#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 +#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 + +#if !defined(CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE +#endif + +#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) +#define CONFIG_SYS_NAND_OOBSIZE 16 +#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#else +#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" +#endif + +#define CONFIG_SYS_NAND_ECCSIZE 0x100 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#endif /* CONFIG_NAND_LPC32XX_SLC */ + /* NOR Flash */ #if defined(CONFIG_SYS_FLASH_CFI) #define CONFIG_FLASH_CFI_DRIVER diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index cc6a53e..d3b7620 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -111,7 +111,10 @@ #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE #define CONFIG_SYS_NAND_USE_FLASH_BBT + #define CONFIG_CMD_NAND /* @@ -199,17 +202,6 @@ #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_ECCSIZE 0x100 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63, } -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS - #define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_NAND_SOFTECC -- 2.1.4

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[U-Boot] [PATCH] fs-test.sh: minor fixes
by Stephen Warren 18 Aug '15

18 Aug '15

- Re-direct stderr into the log files, so any errors U-Boot emits are visible in the logs. This is relevant if the "reset" shell command attempts to report that it's not supported on the sandbox board. - Fix test_fs_nonfs() to name the files it created differently for each invocation. Otherwise, the logs from different tests overwrite each-other. Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> --- test/fs/fs-test.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/test/fs/fs-test.sh b/test/fs/fs-test.sh index a4fb0559625d..b88a67ca066d 100755 --- a/test/fs/fs-test.sh +++ b/test/fs/fs-test.sh @@ -485,9 +485,9 @@ function test_fs_nonfs() { echo "Creating files in $fs image if not already present." create_files $IMAGE $MD5_FILE_FS - OUT_FILE="${OUT}.fs.${fs}.out" + OUT_FILE="${OUT}.$1.${fs}.out" test_image $IMAGE $fs $SMALL_FILE $BIG_FILE $1 "" \ - > ${OUT_FILE} + > ${OUT_FILE} 2>&1 check_results $OUT_FILE $MD5_FILE_FS $SMALL_FILE $BIG_FILE \ $WRITE_FILE TOTAL_FAIL=$((TOTAL_FAIL + FAIL)) @@ -535,7 +535,7 @@ for fs in ext4 fat; do OUT_FILE="${OUT}.sb.${fs}.out" test_image $IMAGE $fs $SMALL_FILE $BIG_FILE sb `pwd`/$MOUNT_DIR \ - > ${OUT_FILE} + > ${OUT_FILE} 2>&1 sudo umount "$MOUNT_DIR" rmdir "$MOUNT_DIR" -- 1.9.1

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