March 2015 - U-Boot

[U-Boot] [PATCH] mpc85xx/T104xD4RDB: Add T104xD4RDB boards support
by Vijay Rai 28 Apr '15

28 Apr '15

T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. T1040D4RDB is re-designed T1040RDB board with following changes : - Support of DDR4 memory - Support of 0x66 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 - Support of QE-TDM Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes : - Support of DDR4 memory - Support for 0x86 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 - Support of DIU Signed-off-by: Vijay Rai <vijay.rai(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- changes from v2: - adds SGMII suport using CPLD - removes extra endif changes from v3: - removes checkpatch error changes from v4: - wrong use of defined MACRO in eth.c file, adds macro properly changes from v5: - updates README files, t1040d4_rcw.cfg and t1042d4_rcw.cfg - update DDR settings board/freescale/t104xrdb/MAINTAINERS | 8 ++++ board/freescale/t104xrdb/README | 75 ++++++++++++++++++++++++++++-- board/freescale/t104xrdb/cpld.h | 2 + board/freescale/t104xrdb/ddr.c | 6 +++ board/freescale/t104xrdb/ddr.h | 9 +++- board/freescale/t104xrdb/eth.c | 20 +++++++- board/freescale/t104xrdb/t1040d4_rcw.cfg | 7 +++ board/freescale/t104xrdb/t1042d4_rcw.cfg | 7 +++ board/freescale/t104xrdb/t104xrdb.c | 21 +++++++++ configs/T1040D4RDB_NAND_defconfig | 5 ++ configs/T1040D4RDB_SDCARD_defconfig | 5 ++ configs/T1040D4RDB_SPIFLASH_defconfig | 5 ++ configs/T1040D4RDB_defconfig | 4 ++ configs/T1042D4RDB_NAND_defconfig | 5 ++ configs/T1042D4RDB_SDCARD_defconfig | 5 ++ configs/T1042D4RDB_SPIFLASH_defconfig | 5 ++ configs/T1042D4RDB_defconfig | 4 ++ include/configs/T104xRDB.h | 42 +++++++++++++---- 18 files changed, 220 insertions(+), 15 deletions(-) create mode 100644 board/freescale/t104xrdb/t1040d4_rcw.cfg create mode 100644 board/freescale/t104xrdb/t1042d4_rcw.cfg create mode 100644 configs/T1040D4RDB_NAND_defconfig create mode 100644 configs/T1040D4RDB_SDCARD_defconfig create mode 100644 configs/T1040D4RDB_SPIFLASH_defconfig create mode 100644 configs/T1040D4RDB_defconfig create mode 100644 configs/T1042D4RDB_NAND_defconfig create mode 100644 configs/T1042D4RDB_SDCARD_defconfig create mode 100644 configs/T1042D4RDB_SPIFLASH_defconfig create mode 100644 configs/T1042D4RDB_defconfig diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS index 13d9be9..32e044f 100644 --- a/board/freescale/t104xrdb/MAINTAINERS +++ b/board/freescale/t104xrdb/MAINTAINERS @@ -6,7 +6,13 @@ F: include/configs/T104xRDB.h F: configs/T1040RDB_defconfig F: configs/T1040RDB_NAND_defconfig F: configs/T1040RDB_SPIFLASH_defconfig +F: configs/T1040D4RDB_defconfig +F: configs/T1040D4RDB_NAND_defconfig +F: configs/T1040D4RDB_SPIFLASH_defconfig F: configs/T1042RDB_defconfig +F: configs/T1042D4RDB_defconfig +F: configs/T1042D4RDB_NAND_defconfig +F: configs/T1042D4RDB_SPIFLASH_defconfig F: configs/T1042RDB_PI_defconfig F: configs/T1042RDB_PI_NAND_defconfig F: configs/T1042RDB_PI_SPIFLASH_defconfig @@ -15,6 +21,8 @@ T1040RDB_SDCARD BOARD #M: - S: Maintained F: configs/T1040RDB_SDCARD_defconfig +F: configs/T1040D4RDB_SDCARD_defconfig +F: configs/T1042D4RDB_SDCARD_defconfig F: configs/T1042RDB_PI_SDCARD_defconfig T1040RDB_SECURE_BOOT BOARD diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index ac95b5e..66538e2 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -12,6 +12,17 @@ The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC. (a personality of T1040 SoC). The board is similar to T1040RDB but is designed specially with low power features targeted for Printing Image Market. +The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. +The board is re-designed T1040RDB board with following changes : + - Support of DDR4 memory and some enhancements + +The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC. +The board is re-designed T1040RDB board with following changes : + - Support of DDR4 memory + - Support for 0x86 serdes protocol which can support following interfaces + - 2 RGMII's on DTSEC4, DTSEC5 + - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 + Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB ------------------------------------------------------------------------- Board Si Protocol Targeted Market @@ -19,6 +30,8 @@ Board Si Protocol Targeted Market T1040RDB T1040 0x66 Networking T1040RDB T1042 0x86 Networking T1042RDB_PI T1042 0x06 Printing & Imaging +T1040D4RDB T1040 0x66 Networking +T1042D4RDB T1042 0x86 Networking T1040 SoC Overview @@ -70,7 +83,6 @@ The T1040/T1042 SoC includes the following function and features: T1040 SoC Personalities ------------------------- - T1022 Personality: T1022 is a reduced personality of T1040 with less core/clusters. @@ -268,8 +280,13 @@ SPI Flash memory Map on T104xRDB Please note QE Firmware is only valid for T1040RDB -Switch Settings: (ON is 0, OFF is 1) -=============== +Switch Settings for T104xRDB boards: (ON is 0, OFF is 1) +========================================================== +NOR boot SW setting: +SW1: 00010011 +SW2: 10111011 +SW3: 11100001 + NAND boot SW setting: SW1: 10001000 SW2: 00111011 @@ -284,3 +301,55 @@ SD boot SW setting: SW1: 00100000 SW2: 00111011 SW3: 11100001 + +Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1) +============================================================= +NOR boot SW setting: +SW1: 00010011 +SW2: 10111001 +SW3: 11100001 + +NAND boot SW setting: +SW1: 10001000 +SW2: 00111001 +SW3: 11110001 + +SPI boot SW setting: +SW1: 00100010 +SW2: 10111001 +SW3: 11100001 + +SD boot SW setting: +SW1: 00100000 +SW2: 00111001 +SW3: 11100001 + +By default PBI_SRC=14 (which is for IFC-NAND/NOR), which needs to be changed for SPI and SD. + +For SD-boot +============== +1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files) + +example: + RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg + +Change +66000002 40000002 ec027000 01000000 +to +66000002 40000002 6c027000 01000000 + +For SPI-boot +============== +1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files) + +example: + RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg + +Change +66000002 40000002 ec027000 01000000 +to +66000002 40000002 5c027000 01000000 + +2. SPI does not support flush so remove flush from pbl, make changes in + tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 + with 0x091380c0 diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 0da9a01..543ab53 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -38,3 +38,5 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) #define CPLD_WRITE(reg, value)\ cpld_write(offsetof(struct cpld_data, reg), value) +#define MISC_CTL_SG_SEL 0x80 +#define MISC_CTL_AURORA_SEL 0x02 diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index e1148e5..3c4eabf 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -91,8 +91,14 @@ found: popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif } #if defined(CONFIG_DEEP_SLEEP) diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h index ab1c32d..58b7349 100644 --- a/board/freescale/t104xrdb/ddr.h +++ b/board/freescale/t104xrdb/ddr.h @@ -28,6 +28,9 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1600, 4, 4, 6, 0x07090A0d, 0x0D0f100a}, +#elif defined(CONFIG_SYS_FSL_DDR3) {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, @@ -40,10 +43,14 @@ static const struct board_specific_parameters udimm0[] = { {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, +#else +#error DDR type not defined +#endif {} }; +#endif + static const struct board_specific_parameters *udimms[] = { udimm0, }; -#endif diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 7581a4cd..71d0457 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -43,9 +43,11 @@ int board_eth_init(bd_t *bis) int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { -#ifdef CONFIG_T1040RDB +#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) case PHY_INTERFACE_MODE_SGMII: - /* T1040RDB only supports SGMII on DTSEC3 */ + /* T1040RDB & T1040D4RDB only supports SGMII on + * DTSEC3 + */ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_SGMII1_PHY_ADDR); break; @@ -60,6 +62,20 @@ int board_eth_init(bd_t *bis) CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif +#ifdef CONFIG_T1042D4RDB + case PHY_INTERFACE_MODE_SGMII: + /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 + * & DTSEC3 + */ + if (FM1_DTSEC1 == i) + phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR; + if (FM1_DTSEC2 == i) + phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR; + if (FM1_DTSEC3 == i) + phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; +#endif case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; diff --git a/board/freescale/t104xrdb/t1040d4_rcw.cfg b/board/freescale/t104xrdb/t1040d4_rcw.cfg new file mode 100644 index 0000000..c1034b3 --- /dev/null +++ b/board/freescale/t104xrdb/t1040d4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 40000002 ec027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342580f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042d4_rcw.cfg b/board/freescale/t104xrdb/t1042d4_rcw.cfg new file mode 100644 index 0000000..9e0ee27 --- /dev/null +++ b/board/freescale/t104xrdb/t1042d4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x86 +0c18000e 0e000000 00000000 00000000 +86000002 40000002 ec027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 9cd5e15..963cae4 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -28,7 +28,11 @@ int checkboard(void) struct cpu_type *cpu = gd->arch.cpu; u8 sw; +#ifdef CONFIG_T104XD4RDB + printf("Board: %sD4RDB\n", cpu->name); +#else printf("Board: %sRDB\n", cpu->name); +#endif printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", CPLD_READ(hw_ver), CPLD_READ(sw_ver)); @@ -91,6 +95,23 @@ int board_early_init_r(void) int misc_init_r(void) { + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) >> 24; + + printf("SERDES Reference : 0x%X\n", srds_s1); + + /* select SGMII*/ + if (srds_s1 == 0x86) + CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | + MISC_CTL_SG_SEL); + + /* select SGMII and Aurora*/ + if (srds_s1 == 0x8E) + CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | + MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); + return 0; } diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig new file mode 100644 index 0000000..8212b34 --- /dev/null +++ b/configs/T1040D4RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig new file mode 100644 index 0000000..d45c60c --- /dev/null +++ b/configs/T1040D4RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig new file mode 100644 index 0000000..d7ccacf --- /dev/null +++ b/configs/T1040D4RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig new file mode 100644 index 0000000..f9a23cf --- /dev/null +++ b/configs/T1040D4RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig new file mode 100644 index 0000000..2ab2b15 --- /dev/null +++ b/configs/T1042D4RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig new file mode 100644 index 0000000..daba6b7 --- /dev/null +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig new file mode 100644 index 0000000..0aa5178 --- /dev/null +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T104XRDB=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig new file mode 100644 index 0000000..3802637 --- /dev/null +++ b/configs/T1042D4RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T104XRDB=y diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 5263318..f11db1d 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -29,6 +29,14 @@ #ifdef CONFIG_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg #endif +#ifdef CONFIG_T1040D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg +#endif +#ifdef CONFIG_T1042D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg +#endif #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT @@ -220,7 +228,9 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD +#ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDR3 +#endif #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 @@ -278,7 +288,7 @@ #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) #define CPLD_DIU_SEL_DFP 0x80 #endif @@ -448,7 +458,7 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) /* Video */ #define CONFIG_FSL_DIU_FB @@ -493,11 +503,11 @@ /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define I2C_MUX_CH_DEFAULT 0x8 #endif -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 @@ -666,7 +676,7 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define CONFIG_QE #define CONFIG_U_QE #endif @@ -695,7 +705,7 @@ #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_QE_FW_ADDR 0x130000 #elif defined(CONFIG_SDCARD) @@ -720,10 +730,20 @@ #ifdef CONFIG_FMAN_ENET #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB) +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 +#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 +#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 +#endif + +#ifdef CONFIG_T104XD4RDB +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 +#else +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 #endif -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ #ifdef CONFIG_T1040RDB @@ -842,6 +862,10 @@ #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" #elif defined(CONFIG_T1042RDB) #define FDTFILE "t1042rdb/t1042rdb.dtb" +#elif defined(CONFIG_T1040D4RDB) +#define FDTFILE "t1042rdb/t1040d4rdb.dtb" +#elif defined(CONFIG_T1042D4RDB) +#define FDTFILE "t1042rdb/t1042d4rdb.dtb" #endif #ifdef CONFIG_FSL_DIU_FB -- 1.7.9.5

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[U-Boot] [PATCH 0/29] dm: Introduce device tree support in SPL (for Rockchip)
by Simon Glass 28 Apr '15

28 Apr '15

With driver model SPL support in place the remaining driver difference between U-Boot proper and SPL is that SPL does not support device tree. This series adds this support, using a Rockchip board as an example. One problem with device tree is that U-Boot has no way of dropping features it does not need or use. For SPL this problem needs to be solved and this series uses the preprocessor for this. The 45KB Firefly device tree reduces to 693 bytes when unused material is removed. A better solution might involve the 'fdtgrep' tool but this has not made it into the device tree compiler as yet. This series includes some changes aimed at reduce code size in SPL, including: - dropping alias sequence support (the aliases node) since many boards just use a single UART in SPL - adding a smaller panic() function that does not support printf()-format strings - removing device unbind code which will never be used in SPL Overall the resulting SPL binary is 8829 bytes with my Linaro 4.8.2 compiler, including the device tree, using Thumb-2. Of this: 1768 bytes is driver model core code 1556 bytes is device tree code 693 bytes is the device tree itself 4756 is other code, including serial drivers, rodata and data The last figure includes rodata incorrectly added by the tool chain [1]. With a bug-fixed gcc 4.9.2 the total size is 6893 bytes including device tree. Approximately 750 bytes is used for strings and driver data (root device and serial) associated with driver model and device tree. This adds up an overhead of around 4750 bytes for driver model and device tree, including the code, rodata and device tree itself. It should therefore be possible to use driver model and device tree in SPL for board that have enough SRAM. Clearly 4KB is impossible without further work (perhaps removing some error strings). I suspect 8KB would be tricky, allowing only 3KB for stack and other code. But 16KB should work OK. SRAM sizes for recent SoCs I am aware of are: Rockchip RK3288: 96KB Tegra 124: 128KB Samsung Exynos 5420: 384KB The Rockchip Firefly was chosen for this work since it is a fairly recent board and is readily available. Rockchip engineers have been actively upstreaming code to Linux in the past year and there is a very full-featured U-Boot available. But it is invisible to most U-Boot people - mainline Rockchip support seems well overdue. This series does not make a serious start on that, since it only prints a message in SPL and then hangs, but additional work should get it booting to a prompt. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54303 Simon Glass (29): serial: ns16550: Add an option to specify the debug UART register shift dm: ns16550: Support non-byte register spacing with driver model dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model serial: ns16550: Remove unnecessary init on UART setup fdt: arm: Drop device tree padding dm: core: Allow sequence alias support to be removed for SPL dm: core: Remove unbind operations when not required dm: Add a panic_str() function to reduce code size dm: core: Drop device removal error path when not supported fdt: sandbox: Move setup code from board_f to fdtdec fdt: Rename setup_fdt() and make it prepare also Move initf_malloc() to a common place Correct malloc_limit value for pre-relocation malloc() fdt: Add an option to disable device tree in SPL dts: Disable device tree for SPL on all boards fdt: Allow FDT functions to be built for SPL dm: core: Select device tree control correctly for SPL dm: Init device tree as well as driver model in SPL dm: serial: Don't support CONFIG_CONS_INDEX with device tree Remove SPL undefine of CONFIG_OF_CONTROL fdt: arm: Build device tree in SPL dm: rockchip: Add serial support rockchip: Bring in RK3288 device tree file includes and bindings rockchip: dts: Adjust device tree files for U-Boot SPL rockchip: Add base SoC files rockchip: Add basic support for firefly-rk3288 mkimage: Display a better list of available image types rockchip: Add the beginnings of an image tool rockchip: Add a simple README arch/arm/Kconfig | 11 + arch/arm/Makefile | 1 + arch/arm/cpu/armv7/exynos/Kconfig | 8 + arch/arm/cpu/armv7/s5pc1xx/Kconfig | 2 + arch/arm/cpu/u-boot-spl.lds | 2 +- arch/arm/dts/Makefile | 6 +- arch/arm/dts/rk3288-firefly.dts | 82 ++ arch/arm/dts/rk3288-firefly.dtsi | 496 +++++++ arch/arm/dts/rk3288-thermal.dtsi | 90 ++ arch/arm/dts/rk3288.dtsi | 1480 ++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/clock.h | 12 + arch/arm/include/asm/arch-rockchip/gpio.h | 5 + arch/arm/include/asm/arch-rockchip/grf.h | 181 +++ arch/arm/mach-rockchip/Kconfig | 44 + arch/arm/mach-rockchip/Makefile | 12 + arch/arm/mach-rockchip/board-spl.c | 54 + arch/arm/mach-rockchip/board.c | 17 + arch/arm/mach-rockchip/common.c | 11 + arch/arm/mach-rockchip/rk3288/Kconfig | 16 + arch/arm/mach-tegra/Kconfig | 3 + arch/sandbox/cpu/cpu.c | 41 + arch/sandbox/include/asm/u-boot-sandbox.h | 8 + board/firefly/firefly-rk3288/Kconfig | 15 + board/firefly/firefly-rk3288/MAINTAINERS | 6 + board/firefly/firefly-rk3288/Makefile | 7 + board/firefly/firefly-rk3288/firefly-rk3288.c | 7 + common/board_f.c | 84 +- common/dlmalloc.c | 11 + common/image.c | 55 +- common/spl/spl.c | 22 +- configs/Linksprite_pcDuino3_fdt_defconfig | 1 + configs/am335x_boneblack_vboot_defconfig | 1 + configs/arches_defconfig | 1 + configs/canyonlands_defconfig | 1 + configs/firefly-rk3288_defconfig | 11 + configs/galileo_defconfig | 1 + configs/microblaze-generic_defconfig | 1 + configs/odroid_defconfig | 1 + configs/origen_defconfig | 1 + configs/s5pc210_universal_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/trats2_defconfig | 1 + configs/trats_defconfig | 1 + configs/zynq_microzed_defconfig | 1 + configs/zynq_zc70x_defconfig | 1 + configs/zynq_zc770_xm010_defconfig | 1 + configs/zynq_zc770_xm012_defconfig | 1 + configs/zynq_zc770_xm013_defconfig | 1 + configs/zynq_zed_defconfig | 1 + configs/zynq_zybo_defconfig | 1 + doc/README.rockchip | 83 ++ .../clock/rockchip,rk3288-cru.txt | 61 + doc/device-tree-bindings/clock/rockchip.txt | 77 + .../pinctrl/rockchip,pinctrl.txt | 157 +++ .../thermal/rockchip-thermal.txt | 68 + drivers/core/Kconfig | 9 + drivers/core/Makefile | 2 + drivers/core/device.c | 54 +- drivers/core/root.c | 14 +- drivers/core/uclass.c | 4 + drivers/serial/Kconfig | 19 + drivers/serial/Makefile | 1 + drivers/serial/ns16550.c | 44 +- drivers/serial/serial-uclass.c | 69 +- drivers/serial/serial_rockchip.c | 41 + dts/Kconfig | 11 +- dts/Makefile | 9 +- include/config_uncmd_spl.h | 3 + include/configs/firefly-rk3288.h | 50 + include/dm/uclass-internal.h | 8 + include/dt-bindings/clock/rk3288-cru.h | 378 +++++ include/dt-bindings/clock/rockchip,rk808.h | 11 + include/dt-bindings/pinctrl/rockchip.h | 34 + include/dt-bindings/power-domain/rk3288.h | 11 + include/dt-bindings/thermal/thermal.h | 17 + include/fdtdec.h | 16 + include/image.h | 12 + include/malloc.h | 3 + include/vsprintf.h | 23 + lib/Makefile | 6 + lib/fdtdec.c | 39 +- lib/vsprintf.c | 23 +- scripts/Makefile.lib | 12 +- scripts/Makefile.spl | 35 + scripts/Makefile.uncmd_spl | 2 + tools/Makefile | 1 + tools/mkimage.c | 59 +- tools/rkimage.c | 63 + 88 files changed, 4136 insertions(+), 212 deletions(-) create mode 100644 arch/arm/dts/rk3288-firefly.dts create mode 100644 arch/arm/dts/rk3288-firefly.dtsi create mode 100644 arch/arm/dts/rk3288-thermal.dtsi create mode 100644 arch/arm/dts/rk3288.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/clock.h create mode 100644 arch/arm/include/asm/arch-rockchip/gpio.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf.h create mode 100644 arch/arm/mach-rockchip/Kconfig create mode 100644 arch/arm/mach-rockchip/Makefile create mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/board.c create mode 100644 arch/arm/mach-rockchip/common.c create mode 100644 arch/arm/mach-rockchip/rk3288/Kconfig create mode 100644 board/firefly/firefly-rk3288/Kconfig create mode 100644 board/firefly/firefly-rk3288/MAINTAINERS create mode 100644 board/firefly/firefly-rk3288/Makefile create mode 100644 board/firefly/firefly-rk3288/firefly-rk3288.c create mode 100644 configs/firefly-rk3288_defconfig create mode 100644 doc/README.rockchip create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt create mode 100644 doc/device-tree-bindings/clock/rockchip.txt create mode 100644 doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt create mode 100644 doc/device-tree-bindings/thermal/rockchip-thermal.txt create mode 100644 drivers/serial/serial_rockchip.c create mode 100644 include/configs/firefly-rk3288.h create mode 100644 include/dt-bindings/clock/rk3288-cru.h create mode 100644 include/dt-bindings/clock/rockchip,rk808.h create mode 100644 include/dt-bindings/pinctrl/rockchip.h create mode 100644 include/dt-bindings/power-domain/rk3288.h create mode 100644 include/dt-bindings/thermal/thermal.h create mode 100644 tools/rkimage.c -- 2.2.0.rc0.207.ga3a616c

3 35

[U-Boot] fatload from eMMC general purpose partition
by Andreas Naumann 24 Apr '15

24 Apr '15

Hi, using an eMMC I want to load uImage and dtb from a general purpose partition (since these can be configured as pSLC independent of the user data area). From the kernel I can format and access the GP-partition, in my case mkfs.vfat. However, U-Boots fatload/extload on the GP-partition do not work or maybe I just give the wrong parameters. Is this implemented at all, any hints? Regards Andreas

3 3

[U-Boot] [PATCH 00/19] [RFC] Power(full) framework based on Driver Model
by Przemyslaw Marczak 24 Apr '15

24 Apr '15

Hello, This piece of code was a base for prepare my presentation talk for the U-Boot Mini Summit, which taking place at ELCE2014 conference, 13-th October 2014 Dusseldorf, Germany. The tittle of talk: "Power(full) framework based on Driver Model" The presentation will be shared after the Summit. This patchset introduces the new one PMIC framework for the U-Boot. It is still under the construction, but the basic functionality was achieved and tested. Please feel free to comment and share the opinion. I think that each patch is described full enough, but for some more design details, please look into the documentation file. It includes some basic examples for the PMIC drivers. Quick summary of: Framework: - The new approach - UCLASS_PMIC - simple and designed for device I/O only - Add new uclass types: UCLASS_PMIC and UCLASS_PMIC_REGULATOR - Two uclass drivers for above types - A common regulator operations - will easy cover the real devices design Drivers: - Introduce new PMIC API for drivers - now everything base on "struct udevice" - Introduce Regulator Voltage descriptors and Operation Mode descriptors which are usually taken from the device tree (board dependent data) - Two uclass device drivers for MAX77686(PMIC+REGULATOR) User Interface: - command pmic, unchanged functionality and ported to the driver model - command regulator(NEW) for safe regulator setup from commandline, - now can check output Voltage and operation mode of the regulators, - also can check the board Voltage limits and driver available modes The future plans: - Wait for the I2c Driver Model implementation - Introduce a common way to bind pmic devices - now done by alias "pmic" - Add additional uclass types: MUIC, CHARGER, BATTERY, MFD and maybe more. - Introduce optimal operations for new uclasses - Port all U-Boot drivers to the new Framework - Remove the old drivers and the old PMIC Framework code The assumptions of this work is: - Add new code to independent files - Keep two Frameworks as independent and without conflicts - Don't mix OLD/NEW Framework code - for the readability - Port all drivers using new API - Remove the old Framework and the old drivers A disadvantage: - some parts of the present code is duplicated Need help: - After merge this, it is welcome to help with driver porting. - Everything should be tested The extra feature: The first commit introduces errno_str() function. It is a common function which I hope will be usefull for commands and not only. If any visible error says: -19 or some other magic number, then it means that this function should be used. U-Boot Mini Summit members: This code is maybe not as good as it could be, but the time was limited, and the conference is comming soon. I don't expects a code review of this now, but it would be nice if you take a look of this piece of code before our U-Boot Mini Summit. Of course it depends on you. Best Regards and see you in Dusseldorf! Przemyslaw Marczak Przemyslaw Marczak (19): lib: errno: introduce errno_str(): returns errno related message exynos: config-common: enable errno_str() function exynos: config-common: enable generic fs command dm: pmic: add implementation of driver model pmic uclass dm: pmic: add implementation of driver model regulator uclass dm: common: board_r: add call and weak of power_init_dm() dm: pmic: add max77686 pmic driver dm: regulator: add max77686 regulator driver dm: pmic: new commands: pmic and regulator dm: board:samsung: power_init_board: add requirement of CONFIG_DM_PMIC doc: driver-model: pmic and regulator uclass documentation samsung: board: lcd menu: check if any power framework is enabled samsung: misc: power_key_pressed: add support to dm pmic framework trats2: board: add support to dm pmic api trats2: dts: max77686: add pmic alias and names cleanup trats2: config: enable dm pmic, dm regulator api, dm max77686 odroid: board: add support to dm pmic api odroid: dts: add 'voltage-regulators' description to max77686 node odroid: config: enable dm pmic, dm regulator and max77686 driver Makefile | 1 + arch/arm/dts/exynos4412-odroid.dts | 250 +++++++++- arch/arm/dts/exynos4412-trats2.dts | 17 +- board/samsung/common/board.c | 5 +- board/samsung/common/misc.c | 21 +- board/samsung/odroid/odroid.c | 31 +- board/samsung/trats2/trats2.c | 208 ++------ common/board_r.c | 8 + doc/driver-model/dm-pmic-framework.txt | 450 ++++++++++++++++++ drivers/power/Makefile | 6 +- drivers/power/cmd_pmic.c | 845 +++++++++++++++++++++++++++++++++ drivers/power/pmic-uclass.c | 255 ++++++++++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/max77686.c | 89 ++++ drivers/power/pmic_i2c.c | 136 ++++++ drivers/power/pmic_spi.c | 137 ++++++ drivers/power/regulator-uclass.c | 250 ++++++++++ drivers/power/regulator/Makefile | 8 + drivers/power/regulator/max77686.c | 749 +++++++++++++++++++++++++++++ include/configs/exynos-common.h | 3 + include/configs/odroid.h | 8 +- include/configs/trats2.h | 14 +- include/dm/uclass-id.h | 4 + include/errno.h | 3 + include/power/max77686_pmic.h | 28 +- include/power/pmic.h | 82 ++++ include/power/regulator.h | 267 +++++++++++ lib/Makefile | 1 + lib/errno_str.c | 147 ++++++ 29 files changed, 3823 insertions(+), 201 deletions(-) create mode 100644 doc/driver-model/dm-pmic-framework.txt create mode 100644 drivers/power/cmd_pmic.c create mode 100644 drivers/power/pmic-uclass.c create mode 100644 drivers/power/pmic/max77686.c create mode 100644 drivers/power/pmic_i2c.c create mode 100644 drivers/power/pmic_spi.c create mode 100644 drivers/power/regulator-uclass.c create mode 100644 drivers/power/regulator/Makefile create mode 100644 drivers/power/regulator/max77686.c create mode 100644 include/power/regulator.h create mode 100644 lib/errno_str.c -- 1.9.1

6 217

[U-Boot] [PATCH v5 0/8] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
by Albert ARIBAUD (3ADEV) 24 Apr '15

24 Apr '15

This series extends functionality for the LPC32xx platform and introduces the WORK Microwave work_92105 board which makes use of the extended functionality. NOTES: A - I2C driver remains non-DM During v2 review, it was suggested to move to DM for I2C. However, this caused issues with the 'date', 'dtt' and 'eeprom' commands which are configured in this board. Therefore the I2C move to DM was not done. B - Some checkpatch diagnostics are not fixed The following warnings checkpatch warnings and checks were not fixed: 1. "warning: arch/arm/Kconfig,135: please write a paragraph that describes the config symbol fully" Other symbols in the same file have no description either. For consistency, I did not add the requested description. 1. "check: include/configs/work_92105.h,187: spaces required around that ':' (ctx:VxV) (5 occurrences on the same line) This is due to the value of CONFIG_ETHADDR not being in quotes. As it never is in any other definition of CONFIG_ETHADDR, I left it unchanged. Changes in v5: - switch to CONFIG_SYS_NAND_SELF_INIT - switched board NAND config to CONFIG_SYS_NAND_SELF_INIT Changes in v4: - remove two debugging statements - add __iomem to regs struct - remove useless 'else return;' - take BB marker out of free OOB area - replace magic numbers in OOB reads/writes - add timeouts in NAND loops - use DIV_ROUND_UP where applicable - fix erroneous comment - skip bad blocks in SPL chainload loop Changes in v3: - move DM dependency constraint into Kconfig - move regs pointer and function cache into private struct - discourage readers from using functions implementation as an example - move regs and functions in private struct - remove script/Makefile.spl change - use writel() in DRAM initialization code - remove useless conditionals in dram.c - fix and complete the board README - remove redundant CONFIG_CMD_DM from config header file - add a note re the hard-coded MAC address - add 'single flashable file' make target Changes in v2: - move from legacy to Driver Model support - added MUX setting for SSP0 - cosmetic: added a blank line before copyright - move boot image generation to mkimage framework Albert ARIBAUD (3ADEV) (8): lpc32xx: add Ethernet support lpc32xx: mtd: nand: add MLC NAND controller lpc32xx: i2c: add LPC32xx I2C interface support lpc32xx: add GPIO support lpc32xx: add LPC32xx SSP support (SPI mode) dtt: add ds620 support lpc32xx: add lpc32xx-spl.bin boot image target lpc32xx: add support for board work_92105 Makefile | 20 + arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile | 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 13 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 43 ++ arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 79 +++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 ++ arch/arm/include/asm/arch-lpc32xx/clk.h | 16 + arch/arm/include/asm/arch-lpc32xx/config.h | 3 + arch/arm/include/asm/arch-lpc32xx/cpu.h | 3 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ arch/arm/include/asm/arch-lpc32xx/mux.h | 18 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 8 +- board/work-microwave/work_92105/Kconfig | 15 + board/work-microwave/work_92105/MAINTAINERS | 6 + board/work-microwave/work_92105/Makefile | 10 + board/work-microwave/work_92105/README | 91 +++ board/work-microwave/work_92105/work_92105.c | 62 ++ .../work-microwave/work_92105/work_92105_display.c | 349 +++++++++++ .../work-microwave/work_92105/work_92105_display.h | 14 + board/work-microwave/work_92105/work_92105_spl.c | 33 + common/image.c | 1 + configs/work_92105_defconfig | 5 + drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c | 293 +++++++++ drivers/hwmon/Makefile | 1 + drivers/hwmon/ds620.c | 65 ++ drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 ++++++++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_mlc.c | 674 +++++++++++++++++++++ drivers/net/Makefile | 1 + drivers/net/lpc32xx_eth.c | 636 +++++++++++++++++++ drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 144 +++++ include/configs/work_92105.h | 268 ++++++++ include/dtt.h | 15 +- include/image.h | 1 + include/netdev.h | 1 + tools/Makefile | 1 + tools/lpc32xximage.c | 178 ++++++ 43 files changed, 3449 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 board/work-microwave/work_92105/work_92105_spl.c create mode 100644 configs/work_92105_defconfig create mode 100644 drivers/gpio/lpc32xx_gpio.c create mode 100644 drivers/hwmon/ds620.c create mode 100644 drivers/i2c/lpc32xx_i2c.c create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c create mode 100644 drivers/net/lpc32xx_eth.c create mode 100644 drivers/spi/lpc32xx_ssp.c create mode 100644 include/configs/work_92105.h create mode 100644 tools/lpc32xximage.c -- 2.1.0

6 24

[U-Boot] [PATCH v5 0/28] Adding LS2085AQDS and RDB
by York Sun 24 Apr '15

24 Apr '15

This set adds necessary support in common ls2085a support and board support for QDS and RDB. Changes in v5: Re-generate patches using patman default flags s/LayerScape/Layerscape/g Fix board README for inconsistent SoC name Fix comment in board header file s/LS2080/LS2085/g Fix Kconfig help for inconsistent SoC name Update LS2085AQDS README to include instructions to form NAND image Update LS2085ARDB README to include instructions to form NAND image Changes in v4: Remove temporary variable cntfrq. Fix board README for inconsistent SoC name Fix comments in board header file Update MAINTAINERS file Update MAINTAINERS file Changes in v3: Move secondary core fix to mp.c. Replace hard-coded value with COUNTER_FREQUENCY. Changes in v2: Rebase after adding macros CONFIG_SYS_I2C_MXC_I2C3 in another patch set Fix CNTFRQ for secondary cores when COUNTER_FREQUENCY_REAL is defined. Add comment to I2C workaround Bhupesh Sharma (1): armv8/fsl-ch3: Add support to print RCW configuration J. German Rivera (2): drivers/fsl-mc: Changed MC firmware loading for new boot architecture drivers/fsl-mc: Autoload AOIP image from NOR flash Jaiprakash Singh (1): driver/ifc: Add 64KB page support Minghuan Lian (1): armv8: Add SerDes framework for Layerscape Architecture Prabhakar Kushwaha (4): armv8/ls2085a: Update common header file driver/ldpaa_eth: Update ldpaa ethernet driver driver/ldpaa: Add support of WRIOP static data structure board/ls2085qds: Add support ethernet Scott Wood (8): armv8/fsl-lsch3: Set nodes in DVM domain fsl-lsch3: Introduce place for common early SoC init armv8/ls2085a: Add workaround for USB erratum A-008751 armv8/fsl-lsch3: Use correct compatible for serial clock fixup armv8/fsl-lsch3: Enable system error aborts armv8/ls2085aqds: NAND boot support freescale/qixis: Add support for booting from NAND armv8/ls2085ardb: Enable NAND SPL support Shaohui Xie (1): net/memac_phy: reuse driver for little endian SoCs Yangbo Lu (1): ls2085a: esdhc: Add esdhc support for ls2085a York Sun (7): armv8/fsl-lsch3: Implement workaround for erratum A008585 armv8/fsl-lsch3: Fix platform clock calculation armv8/ls2085a: Fix generic timer clock source armv8/fsl-lsch3: Update early MMU table armv8/ls2085aqds: Add support of LS2085AQDS platform armv8/ls2085ardb: Add support of LS2085ARDB platform armv8/fsl-lsch3: Implement workaround for I2C issue pankaj chauhan (2): armv8/ls2085a: Add support for reset request net/phy/cortina: Fix compilation warning README | 8 + arch/arm/Kconfig | 24 + arch/arm/cpu/armv7/ls102xa/clock.c | 4 +- arch/arm/cpu/armv8/fsl-lsch3/Makefile | 2 + arch/arm/cpu/armv8/fsl-lsch3/README | 78 +++- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 123 ++++- arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 9 +- arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c | 115 +++++ arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 15 + arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c | 117 +++++ arch/arm/cpu/armv8/fsl-lsch3/mp.c | 7 + arch/arm/cpu/armv8/fsl-lsch3/mp.h | 1 + arch/arm/cpu/armv8/fsl-lsch3/soc.c | 107 +++++ arch/arm/cpu/armv8/fsl-lsch3/speed.c | 11 +- arch/arm/cpu/armv8/generic_timer.c | 11 + arch/arm/cpu/armv8/u-boot-spl.lds | 77 ++++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 42 ++ arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h | 67 +++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 29 ++ arch/arm/include/asm/arch-fsl-lsch3/soc.h | 8 + arch/arm/lib/crt0_64.S | 7 + arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 8 +- arch/powerpc/cpu/mpc85xx/speed.c | 4 +- board/freescale/bsc9132qds/bsc9132qds.c | 4 +- board/freescale/c29xpcie/c29xpcie.c | 4 +- board/freescale/common/qixis.c | 31 +- board/freescale/ls2085a/ls2085a.c | 29 +- board/freescale/ls2085aqds/Kconfig | 16 + board/freescale/ls2085aqds/MAINTAINERS | 8 + board/freescale/ls2085aqds/Makefile | 9 + board/freescale/ls2085aqds/README | 148 ++++++ board/freescale/ls2085aqds/ddr.c | 196 ++++++++ board/freescale/ls2085aqds/ddr.h | 92 ++++ board/freescale/ls2085aqds/eth.c | 380 +++++++++++++++ board/freescale/ls2085aqds/ls2085aqds.c | 274 +++++++++++ board/freescale/ls2085aqds/ls2085aqds_qixis.h | 30 ++ board/freescale/ls2085ardb/Kconfig | 16 + board/freescale/ls2085ardb/MAINTAINERS | 8 + board/freescale/ls2085ardb/Makefile | 8 + board/freescale/ls2085ardb/README | 128 ++++++ board/freescale/ls2085ardb/ddr.c | 196 ++++++++ board/freescale/ls2085ardb/ddr.h | 92 ++++ board/freescale/ls2085ardb/ls2085ardb.c | 249 ++++++++++ board/freescale/ls2085ardb/ls2085ardb_qixis.h | 20 + board/freescale/p1010rdb/p1010rdb.c | 5 +- board/freescale/p1010rdb/spl.c | 4 +- common/board_r.c | 6 + common/spl/spl.c | 2 +- common/spl/spl_nand.c | 2 +- configs/ls2085aqds_defconfig | 3 + configs/ls2085aqds_nand_defconfig | 4 + configs/ls2085ardb_defconfig | 3 + configs/ls2085ardb_nand_defconfig | 4 + drivers/misc/fsl_ifc.c | 12 + drivers/mmc/fsl_esdhc.c | 36 +- drivers/mtd/nand/fsl_ifc_nand.c | 53 ++- drivers/mtd/nand/fsl_ifc_spl.c | 25 +- drivers/net/Makefile | 1 + drivers/net/fm/eth.c | 2 +- drivers/net/fm/memac.c | 2 +- drivers/net/fm/memac_phy.c | 62 ++- drivers/net/fsl-mc/mc.c | 512 ++++++++++++++++----- drivers/net/ldpaa_eth/Makefile | 3 +- drivers/net/ldpaa_eth/ldpaa_eth.c | 62 ++- drivers/net/ldpaa_eth/ldpaa_eth.h | 4 - drivers/net/ldpaa_eth/ldpaa_wriop.c | 146 ++++++ drivers/net/ldpaa_eth/ls2085a.c | 83 ++++ drivers/net/phy/cortina.c | 4 +- drivers/net/vsc9953.c | 2 +- include/configs/ls2085a_common.h | 225 +++++---- include/configs/ls2085a_emu.h | 65 +++ include/configs/ls2085a_simu.h | 122 +++++ include/configs/ls2085aqds.h | 362 +++++++++++++++ include/configs/ls2085ardb.h | 308 +++++++++++++ include/fsl-mc/ldpaa_wriop.h | 70 +++ include/fsl_ddr_sdram.h | 1 + include/fsl_esdhc.h | 4 + include/fsl_ifc.h | 84 ++-- {arch/powerpc/include/asm => include}/fsl_memac.h | 0 79 files changed, 4658 insertions(+), 437 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c create mode 100644 arch/arm/cpu/armv8/fsl-lsch3/soc.c create mode 100644 arch/arm/cpu/armv8/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/soc.h create mode 100644 board/freescale/ls2085aqds/Kconfig create mode 100644 board/freescale/ls2085aqds/MAINTAINERS create mode 100644 board/freescale/ls2085aqds/Makefile create mode 100644 board/freescale/ls2085aqds/README create mode 100644 board/freescale/ls2085aqds/ddr.c create mode 100644 board/freescale/ls2085aqds/ddr.h create mode 100644 board/freescale/ls2085aqds/eth.c create mode 100644 board/freescale/ls2085aqds/ls2085aqds.c create mode 100644 board/freescale/ls2085aqds/ls2085aqds_qixis.h create mode 100644 board/freescale/ls2085ardb/Kconfig create mode 100644 board/freescale/ls2085ardb/MAINTAINERS create mode 100644 board/freescale/ls2085ardb/Makefile create mode 100644 board/freescale/ls2085ardb/README create mode 100644 board/freescale/ls2085ardb/ddr.c create mode 100644 board/freescale/ls2085ardb/ddr.h create mode 100644 board/freescale/ls2085ardb/ls2085ardb.c create mode 100644 board/freescale/ls2085ardb/ls2085ardb_qixis.h create mode 100644 configs/ls2085aqds_defconfig create mode 100644 configs/ls2085aqds_nand_defconfig create mode 100644 configs/ls2085ardb_defconfig create mode 100644 configs/ls2085ardb_nand_defconfig create mode 100644 drivers/net/ldpaa_eth/ldpaa_wriop.c create mode 100644 drivers/net/ldpaa_eth/ls2085a.c create mode 100644 include/configs/ls2085aqds.h create mode 100644 include/configs/ls2085ardb.h create mode 100644 include/fsl-mc/ldpaa_wriop.h rename {arch/powerpc/include/asm => include}/fsl_memac.h (100%) -- 1.7.9.5

4 38

[U-Boot] [PATCH] drivers/net/e1000.c: Cleanup whitespace
by York Sun 24 Apr '15

24 Apr '15

From: Minghuan Lian <Minghuan.Lian(a)freescale.com> The patch removes unnecessary whitespace to fix checkpatch's warning: unnecessary whitespace before a quoted newline Signed-off-by: Minghuan Lian <Minghuan.Lian(a)freescale.com> CC: Joe Hershberger <joe.hershberger(a)ni.com> --- drivers/net/e1000.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index cd44222..e747d97 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -2174,7 +2174,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw) DEBUGOUT("Error, did not detect valid phy.\n"); return ret_val; } - DEBUGOUT("Phy ID = %x \n", hw->phy_id); + DEBUGOUT("Phy ID = %x\n", hw->phy_id); /* Set PHY to class A mode (if necessary) */ ret_val = e1000_set_phy_mode(hw); @@ -3485,11 +3485,11 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw) * some "sticky" (latched) bits. */ if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { - DEBUGOUT("PHY Read Error \n"); + DEBUGOUT("PHY Read Error\n"); return -E1000_ERR_PHY; } if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { - DEBUGOUT("PHY Read Error \n"); + DEBUGOUT("PHY Read Error\n"); return -E1000_ERR_PHY; } @@ -5152,7 +5152,7 @@ e1000_poll(struct eth_device *nic) if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) return 0; - /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ + /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ /* Packet received, make sure the data are re-loaded from RAM. */ len = le32_to_cpu(rd->length); invalidate_dcache_range((unsigned long)packet, -- 1.7.9.5

2 5

[U-Boot] [PATCH] cmd_mem: Store last address/size/etc as ulong
by York Sun 24 Apr '15

24 Apr '15

From: Scott Wood <scottwood(a)freescale.com> Otherwise the high 32 bits get truncated on 64-bit U-boot. Signed-off-by: Scott Wood <scottwood(a)freescale.com> CC: Simon Glass <sjg(a)chromium.org> --- common/cmd_mem.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index bcb3ee3..62a0404 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -35,9 +35,9 @@ static int mod_mem(cmd_tbl_t *, int, int, int, char * const []); /* Display values from last command. * Memory modify remembered values are different from display memory. */ -static uint dp_last_addr, dp_last_size; -static uint dp_last_length = 0x40; -static uint mm_last_addr, mm_last_size; +static ulong dp_last_addr, dp_last_size; +static ulong dp_last_length = 0x40; +static ulong mm_last_addr, mm_last_size; static ulong base_address = 0; -- 1.7.9.5

2 3

[U-Boot] [PATCH 1/4] drivers/ddr/fsl: Update DDR driver for DDR4
by York Sun 24 Apr '15

24 Apr '15

Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun <yorksun(a)freescale.com> --- drivers/ddr/fsl/ctrl_regs.c | 17 ++++++++++---- drivers/ddr/fsl/interactive.c | 51 ++++++++++++++++++++++++++++++++++++++++- drivers/ddr/fsl/main.c | 2 +- drivers/ddr/fsl/util.c | 28 +++++++++++++++++++--- include/fsl_ddr.h | 4 +--- 5 files changed, 89 insertions(+), 13 deletions(-) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 690e73d..9ccddef 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -313,7 +313,10 @@ static void set_timing_cfg_0(const unsigned int ctrl_num, #ifdef CONFIG_SYS_FSL_DDR4 /* tXP=max(4nCK, 6ns) */ int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */ - trwt_mclk = 2; + unsigned int data_rate = get_ddr_freq(ctrl_num); + + /* for faster clock, need more time for data setup */ + trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2; twrt_mclk = 1; act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); pre_pd_exit_mclk = act_pd_exit_mclk; @@ -338,7 +341,7 @@ static void set_timing_cfg_0(const unsigned int ctrl_num, */ txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000)); - ip_rev = fsl_ddr_get_version(); + ip_rev = fsl_ddr_get_version(ctrl_num); if (ip_rev >= 0x40700) { /* * MRS_CYC = max(tMRD, tMOD) @@ -544,7 +547,7 @@ static void set_timing_cfg_1(const unsigned int ctrl_num, * we need set extend bit for it at * TIMING_CFG_3[EXT_CASLAT] */ - if (fsl_ddr_get_version() <= 0x40400) + if (fsl_ddr_get_version(ctrl_num) <= 0x40400) caslat_ctrl = 2 * cas_latency - 1; else caslat_ctrl = (cas_latency - 1) << 1; @@ -1114,12 +1117,16 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */ unsigned short esdmode5; /* Extended SDRAM mode 5 */ - esdmode5 = 0x00000400; /* Data mask enabled */ + esdmode5 = 0x00000500; /* Data mask enabled */ ddr->ddr_sdram_mode_9 = (0 | ((esdmode4 & 0xffff) << 16) | ((esdmode5 & 0xffff) << 0) ); + + /* only mode_9 use 0x500, others use 0x400 */ + esdmode5 = 0x00000400; /* Data mask enabled */ + debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9); if (unq_mrs_en) { /* unique mode registers are supported */ for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { @@ -2349,7 +2356,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num, set_ddr_cdr1(ddr, popts); set_ddr_cdr2(ddr, popts); set_ddr_sdram_cfg(ddr, popts, common_dimm); - ip_rev = fsl_ddr_get_version(); + ip_rev = fsl_ddr_get_version(ctrl_num); if (ip_rev > 0x40400) unq_mrs_en = 1; diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index 32ba6d8..57d14e8 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -205,6 +205,8 @@ static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo, #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \ sizeof((dimm_params_t *)0)->x, 0} +#define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \ + sizeof((dimm_params_t *)0)->x, 1} static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, unsigned int ctrl_num, @@ -220,6 +222,7 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, DIMM_PARM(primary_sdram_width), DIMM_PARM(ec_sdram_width), DIMM_PARM(registered_dimm), + DIMM_PARM(mirrored_dimm), DIMM_PARM(device_width), DIMM_PARM(n_row_addr), @@ -274,7 +277,27 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, DIMM_PARM(tdqsq_max_ps), DIMM_PARM(tqhs_ps), #endif - +#ifdef CONFIG_SYS_FSL_DDR4 + DIMM_PARM_HEX(dq_mapping[0]), + DIMM_PARM_HEX(dq_mapping[1]), + DIMM_PARM_HEX(dq_mapping[2]), + DIMM_PARM_HEX(dq_mapping[3]), + DIMM_PARM_HEX(dq_mapping[4]), + DIMM_PARM_HEX(dq_mapping[5]), + DIMM_PARM_HEX(dq_mapping[6]), + DIMM_PARM_HEX(dq_mapping[7]), + DIMM_PARM_HEX(dq_mapping[8]), + DIMM_PARM_HEX(dq_mapping[9]), + DIMM_PARM_HEX(dq_mapping[10]), + DIMM_PARM_HEX(dq_mapping[11]), + DIMM_PARM_HEX(dq_mapping[12]), + DIMM_PARM_HEX(dq_mapping[13]), + DIMM_PARM_HEX(dq_mapping[14]), + DIMM_PARM_HEX(dq_mapping[15]), + DIMM_PARM_HEX(dq_mapping[16]), + DIMM_PARM_HEX(dq_mapping[17]), + DIMM_PARM(dq_mapping_ors), +#endif DIMM_PARM(rank_density), DIMM_PARM(capacity), DIMM_PARM(base_address), @@ -296,6 +319,7 @@ static void print_dimm_parameters(const dimm_params_t *pdimm) DIMM_PARM(primary_sdram_width), DIMM_PARM(ec_sdram_width), DIMM_PARM(registered_dimm), + DIMM_PARM(mirrored_dimm), DIMM_PARM(device_width), DIMM_PARM(n_row_addr), @@ -314,6 +338,7 @@ static void print_dimm_parameters(const dimm_params_t *pdimm) DIMM_PARM(tckmax_ps), DIMM_PARM(caslat_x), + DIMM_PARM_HEX(caslat_x), DIMM_PARM(taa_ps), DIMM_PARM(caslat_x_minus_1), DIMM_PARM(caslat_x_minus_2), @@ -322,6 +347,9 @@ static void print_dimm_parameters(const dimm_params_t *pdimm) DIMM_PARM(trcd_ps), DIMM_PARM(trp_ps), DIMM_PARM(tras_ps), +#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3) + DIMM_PARM(tfaw_ps), +#endif #ifdef CONFIG_SYS_FSL_DDR4 DIMM_PARM(trfc1_ps), DIMM_PARM(trfc2_ps), @@ -347,6 +375,27 @@ static void print_dimm_parameters(const dimm_params_t *pdimm) DIMM_PARM(tdqsq_max_ps), DIMM_PARM(tqhs_ps), #endif +#ifdef CONFIG_SYS_FSL_DDR4 + DIMM_PARM_HEX(dq_mapping[0]), + DIMM_PARM_HEX(dq_mapping[1]), + DIMM_PARM_HEX(dq_mapping[2]), + DIMM_PARM_HEX(dq_mapping[3]), + DIMM_PARM_HEX(dq_mapping[4]), + DIMM_PARM_HEX(dq_mapping[5]), + DIMM_PARM_HEX(dq_mapping[6]), + DIMM_PARM_HEX(dq_mapping[7]), + DIMM_PARM_HEX(dq_mapping[8]), + DIMM_PARM_HEX(dq_mapping[9]), + DIMM_PARM_HEX(dq_mapping[10]), + DIMM_PARM_HEX(dq_mapping[11]), + DIMM_PARM_HEX(dq_mapping[12]), + DIMM_PARM_HEX(dq_mapping[13]), + DIMM_PARM_HEX(dq_mapping[14]), + DIMM_PARM_HEX(dq_mapping[15]), + DIMM_PARM_HEX(dq_mapping[16]), + DIMM_PARM_HEX(dq_mapping[17]), + DIMM_PARM(dq_mapping_ors), +#endif }; static const unsigned int n_opts = ARRAY_SIZE(options); diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index b72b242..fa22383 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -453,7 +453,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, retval = compute_dimm_parameters( i, spd, pdimm, j); #ifdef CONFIG_SYS_DDR_RAW_TIMING - if (!i && !j && retval) { + if (!j && retval) { printf("SPD error on controller %d! " "Trying fallback to raw timing " "calculation\n", i); diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 664081b..ce55aea 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -23,12 +23,34 @@ #define ULL_8FS 0xFFFFFFFFULL -u32 fsl_ddr_get_version(void) +u32 fsl_ddr_get_version(unsigned int ctrl_num) { struct ccsr_ddr __iomem *ddr; u32 ver_major_minor_errata; - ddr = (void *)_DDR_ADDR; + switch (ctrl_num) { + case 0: + ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + break; +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) + case 1: + ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; + break; +#endif + default: + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); + return 0; + } ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; @@ -212,7 +234,7 @@ void print_ddr_info(unsigned int start_ctrl) /* Calculate CAS latency based on timing cfg values */ cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); - if (fsl_ddr_get_version() <= 0x40400) + if (fsl_ddr_get_version(0) <= 0x40400) cas_lat += 1; else cas_lat += 2; diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index feccef9..4099a74 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -34,9 +34,7 @@ #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) #endif -#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR - -u32 fsl_ddr_get_version(void); +u32 fsl_ddr_get_version(unsigned int ctrl_num); #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* -- 1.7.9.5

1 4

[U-Boot] [PATCH 1/8] armv8/fsl-lsch3: Add Freescale Debug Server driver
by York Sun 24 Apr '15

24 Apr '15

From: Bhupesh Sharma <bhupesh.sharma(a)freescale.com> The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma <bhupesh.sharma(a)freescale.com> --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 2 +- arch/arm/include/asm/arch-fsl-lsch3/config.h | 10 +- board/freescale/ls2085a/ls2085a.c | 29 +++ drivers/misc/Makefile | 1 + drivers/misc/fsl_debug_server.c | 246 ++++++++++++++++++++++++++ drivers/net/fsl-mc/mc.c | 4 + include/configs/ls2085a_common.h | 20 ++- include/fsl-mc/fsl_mc.h | 1 + include/fsl_debug_server.h | 32 ++++ 9 files changed, 338 insertions(+), 7 deletions(-) create mode 100644 drivers/misc/fsl_debug_server.c create mode 100644 include/fsl_debug_server.h diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 4997487..618fbc2 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -10,6 +10,7 @@ #include <asm/armv8/mmu.h> #include <asm/io.h> #include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <fsl_debug_server.h> #include <fsl-mc/fsl_mc.h> #include "cpu.h" #include "mp.h" @@ -384,7 +385,6 @@ int cpu_eth_init(bd_t *bis) return error; } - int arch_early_init_r(void) { int rv; diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index b140c1f..59d10bf 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -30,6 +30,15 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +/* SP (Cortex-A5) related */ +#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) +#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \ + (CONFIG_SYS_FSL_SP_ADDR + 0x0008) +#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \ + (CONFIG_SYS_FSL_SP_ADDR + 0x1000) + #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL @@ -88,7 +97,6 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 - /* IFC */ #define CONFIG_SYS_FSL_IFC_LE diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c index 519d61c..a16c2c8 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2085a/ls2085a.c @@ -12,6 +12,7 @@ #include <asm/io.h> #include <fdt_support.h> #include <libfdt.h> +#include <fsl_debug_server.h> #include <fsl-mc/fsl_mc.h> #include <environment.h> @@ -79,6 +80,34 @@ void reset_cpu(ulong addr) { } +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ +#ifdef CONFIG_FSL_DEBUG_SERVER + debug_server_init(); +#endif + + return 0; +} +#endif + +unsigned long get_dram_size_to_hide(void) +{ + unsigned long dram_to_hide = 0; + +/* Carve the Debug Server private DRAM block from the end of DRAM */ +#ifdef CONFIG_FSL_DEBUG_SERVER + dram_to_hide += debug_server_get_dram_block_size(); +#endif + +/* Carve the MC private DRAM block from the end of DRAM */ +#ifdef CONFIG_FSL_MC_ENET + dram_to_hide += mc_get_dram_block_size(); +#endif + + return dram_to_hide; +} + int board_eth_init(bd_t *bis) { int error = 0; diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 6028cd4..3dd76eb 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_FSL_DEBUG_SERVER) += fsl_debug_server.o obj-$(CONFIG_FSL_IIM) += fsl_iim.o obj-$(CONFIG_GPIO_LED) += gpio_led.o obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o diff --git a/drivers/misc/fsl_debug_server.c b/drivers/misc/fsl_debug_server.c new file mode 100644 index 0000000..e080fe6 --- /dev/null +++ b/drivers/misc/fsl_debug_server.c @@ -0,0 +1,246 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/system.h> +#include <asm/arch-fsl-lsch3/immap_lsch3.h> + +#include <fsl_debug_server.h> + +DECLARE_GLOBAL_DATA_PTR; +static int debug_server_ver_info_maj, debug_server_ver_info_min; + +/** + * Copying Debug Server firmware to DDR + */ +static int debug_server_copy_image(const char *title, u64 image_addr, + u32 image_size, u64 debug_server_ram_addr) +{ + debug("%s copied to address %p\n", title, + (void *)debug_server_ram_addr); + memcpy((void *)debug_server_ram_addr, (void *)image_addr, image_size); + + return 0; +} + +/** + * Debug Server FIT image parser checks if the image is in FIT + * format, verifies integrity of the image and calculates + * raw image address and size values. + * + * Returns 0 if success and -1 if any of the above mentioned + * task fail. + **/ +int debug_server_parse_firmware_fit_image(const void **raw_image_addr, + size_t *raw_image_size) +{ + int format; + void *fit_hdr; + int node_offset; + const void *data; + size_t size; + const char *uname = "firmware"; + char *desc; + char *debug_server_ver_info; + char *debug_server_ver_info_major, *debug_server_ver_info_minor; + + /* Check if the image is in NOR flash */ +#ifdef CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR + fit_hdr = (void *)CONFIG_SYS_DEBUG_SERVER_FW_ADDR; +#else +#error "CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR not defined" +#endif + + /* Check if Image is in FIT format */ + format = genimg_get_format(fit_hdr); + if (format != IMAGE_FORMAT_FIT) { + printf("Error! Not a FIT image\n"); + goto out_error; + } + + if (!fit_check_format(fit_hdr)) { + printf("Error! Bad FIT image format\n"); + goto out_error; + } + + node_offset = fit_image_get_node(fit_hdr, uname); + if (node_offset < 0) { + printf("Error! Can not find %s subimage\n", uname); + goto out_error; + } + + /* Verify Debug Server firmware image */ + if (!fit_image_verify(fit_hdr, node_offset)) { + printf("Error! Bad Debug Server firmware hash"); + goto out_error; + } + + if (fit_get_desc(fit_hdr, node_offset, &desc) < 0) { + printf("Error! Failed to get Debug Server fw description"); + goto out_error; + } + + debug_server_ver_info = strstr(desc, "Version"); + debug_server_ver_info_major = strtok(debug_server_ver_info, "."); + debug_server_ver_info_minor = strtok(NULL, "."); + + debug_server_ver_info_maj = + simple_strtoul(debug_server_ver_info_major, NULL, 10); + debug_server_ver_info_min = + simple_strtoul(debug_server_ver_info_minor, NULL, 10); + + /* Debug server version checking */ + if ((debug_server_ver_info_maj < DEBUG_SERVER_VER_MAJOR) || + (debug_server_ver_info_min < DEBUG_SERVER_VER_MINOR)) { + printf("Debug server FW mismatches the min version required\n"); + printf("Expected:%d.%d, Got %d.%d\n", + DEBUG_SERVER_VER_MAJOR, DEBUG_SERVER_VER_MINOR, + debug_server_ver_info_maj, + debug_server_ver_info_min); + goto out_error; + } + + /* Get address and size of raw image */ + fit_image_get_data(fit_hdr, node_offset, &data, &size); + + *raw_image_addr = data; + *raw_image_size = size; + + return 0; + +out_error: + return -1; +} + +/** + * Return the actual size of the Debug Server private DRAM block. + * + * NOTE: For now this function always returns the minimum required size, + * However, in the future, the actual size may be obtained from an environment + * variable. + */ +unsigned long debug_server_get_dram_block_size(void) +{ + return CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE; +} + +int debug_server_init(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + int error, timeout = CONFIG_SYS_DEBUG_SERVER_TIMEOUT; + int debug_server_boot_status; + u64 debug_server_ram_addr, debug_server_ram_size; + const void *raw_image_addr; + size_t raw_image_size = 0; + + debug("debug_server_init called\n"); + /* + * The Debug Server private DRAM block was already carved at the end of + * DRAM by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: + */ + debug_server_ram_size = debug_server_get_dram_block_size(); + if (gd->bd->bi_dram[1].start) + debug_server_ram_addr = + gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; + else + debug_server_ram_addr = + gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; + + error = debug_server_parse_firmware_fit_image(&raw_image_addr, + &raw_image_size); + if (error != 0) + goto out; + + debug("debug server (ram addr = 0x%llx, ram size = 0x%llx)\n", + debug_server_ram_addr, debug_server_ram_size); + /* + * Load the Debug Server FW at the beginning of the Debug Server + * private DRAM block: + */ + debug_server_copy_image("Debug Server Firmware", + (u64)raw_image_addr, raw_image_size, + debug_server_ram_addr); + + /* flush dcache */ + flush_dcache_range((unsigned long)debug_server_ram_addr, + (unsigned long)debug_server_ram_addr + + (unsigned long)debug_server_ram_size); + + /* + * Tell SP that the Debug Server FW is about to be launched. Before that + * populate the following: + * 1. Write the size allocated to SP Memory region into Bits {31:16} of + * SCRATCHRW5. + * 2. Write the start address of the SP memory regions into + * SCRATCHRW5 (Bits {15:0}, contain most significant bits, Bits + * {47:32} of the SP Memory Region physical start address + * (SoC address)) and SCRATCHRW6 (Bits {31:0}). + * 3. To know the Debug Server FW boot status, set bit 0 of SCRATCHRW11 + * to 1. The Debug Server sets this to 0 to indicate a + * successul boot. + * 4. Wakeup SP by writing 0x1F to VSG GIC reg VIGR2. + */ + + /* 512 MB */ + out_le32(&gur->scratchrw[5 - 1], + (u32)((u64)debug_server_ram_addr >> 32) | (0x000D << 16)); + out_le32(&gur->scratchrw[6 - 1], + ((u32)debug_server_ram_addr) & 0xFFFFFFFF); + + out_le32(&gur->scratchrw[11 - 1], DEBUG_SERVER_INIT_STATUS); + /* Allow the changes to reflect in GUR block */ + mb(); + + /* + * Program VGIC to raise an interrupt to SP + */ + out_le32(CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2, 0x1F); + /* Allow the changes to reflect in VIGR2 */ + mb(); + + dmb(); + debug("Polling for Debug server to launch ...\n"); + + while (1) { + debug_server_boot_status = in_le32(&gur->scratchrw[11 - 1]); + if (!(debug_server_boot_status & DEBUG_SERVER_INIT_STATUS_MASK)) + break; + + udelay(1); /* throttle polling */ + if (timeout-- <= 0) + break; + } + + if (timeout <= 0) { + printf("Debug Server FW timed out (boot status: 0x%x)\n", + debug_server_boot_status); + error = -ETIMEDOUT; + goto out; + } + + if (debug_server_boot_status & DEBUG_SERVER_INIT_STATUS_MASK) { + printf("Debug server FW error'ed out (boot status: 0x%x)\n", + debug_server_boot_status); + error = -ENODEV; + goto out; + } + + printf("Debug server booted\n"); + printf("Detected firmware %d.%d, (boot status: 0x0%x)\n", + debug_server_ver_info_maj, debug_server_ver_info_min, + debug_server_boot_status); + +out: + if (error != 0) + debug_server_boot_status = -error; + else + debug_server_boot_status = 0; + + return debug_server_boot_status; +} + diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 74b0085..76581cb 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -9,6 +9,7 @@ #include <fsl-mc/fsl_mc.h> #include <fsl-mc/fsl_mc_sys.h> #include <fsl-mc/fsl_dpmng.h> +#include <fsl_debug_server.h> DECLARE_GLOBAL_DATA_PTR; static int mc_boot_status; @@ -112,6 +113,9 @@ int mc_init(bd_t *bis) gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; } +#ifdef CONFIG_FSL_DEBUG_SERVER + mc_ram_addr -= debug_server_get_dram_block_size(); +#endif /* * Management Complex cores should be held at reset out of POR. * U-boot should be the first software to touch MC. To be safe, diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index f80efed..c70ba70 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -19,6 +19,9 @@ #define CONFIG_ARM_ERRATA_828024 #define CONFIG_ARM_ERRATA_826974 +/* We need architecture specific misc initializations */ +#define CONFIG_ARCH_MISC_INIT + /* Link Definitions */ #define CONFIG_SYS_TEXT_BASE 0x30001000 @@ -206,6 +209,14 @@ #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +/* Debug Server firmware */ +#define CONFIG_FSL_DEBUG_SERVER +#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR +#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL +/* 2 sec timeout */ +#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000) + /* MC firmware */ #define CONFIG_FSL_MC_ENET #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) @@ -217,9 +228,9 @@ #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH (256 * 1024) #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000 -/* Carve the MC private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_MEM_TOP_HIDE mc_get_dram_block_size() +/* Carve out a DDR region which will not be used by u-boot/Linux */ +#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) +#define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide() #endif /* Command line configuration */ @@ -251,7 +262,6 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 - #define CONFIG_NR_DRAM_BANKS 3 #define CONFIG_HWCONFIG @@ -298,7 +308,7 @@ #define CONFIG_SYS_MAXARGS 64 /* max command args */ #ifndef __ASSEMBLY__ -unsigned long mc_get_dram_block_size(void); +unsigned long get_dram_size_to_hide(void); #endif #endif /* __LS2_COMMON_H */ diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index b9f089e..28d5961 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -56,4 +56,5 @@ struct mc_ccsr_registers { int mc_init(bd_t *bis); int get_mc_boot_status(void); +unsigned long mc_get_dram_block_size(void); #endif diff --git a/include/fsl_debug_server.h b/include/fsl_debug_server.h new file mode 100644 index 0000000..28d8adb --- /dev/null +++ b/include/fsl_debug_server.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_DBG_SERVER_H__ +#define __FSL_DBG_SERVER_H__ + +#include <asm/io.h> +#include <common.h> + +/* + * Define Debug Server firmware version information + */ + +/* Major version number: incremented on API compatibility changes */ +#define DEBUG_SERVER_VER_MAJOR 0 + +/* Minor version number: incremented on API additions (backward + * compatible); reset when major version is incremented. + */ +#define DEBUG_SERVER_VER_MINOR 1 + +#define DEBUG_SERVER_INIT_STATUS (1 << 0) +#define DEBUG_SERVER_INIT_STATUS_MASK (0x00000001) + +int debug_server_init(void); +unsigned long debug_server_get_dram_block_size(void); + +#endif /* __FSL_DBG_SERVER_H__ */ + -- 1.7.9.5

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