March 2015 - U-Boot

[U-Boot] [PATCH 0/2 v3] arm: socfpga: Add Cadence QSPI support
by Stefan Roese 15 May '15

15 May '15

Hi! So this is my 3rd posting regarding the Candence SPI driver on SoCFPGA. The current status is, that SPI NOR flash works now without problems. And dcache is still enabled. The previous disabling was not needed. And only caused problems while booting into Linux. No cache flush or invalidate is needed. As no DMA engine is involved in this transfer. The "solution" I used to get SPI NOR flash support working now is implemented in patch 0004 (still marked as RFC). Here a software reset is issued on the Micron N25Q256A SPI NOR flash. This seems to solve all problems and reading / writing to the SPI NOR flash seems to work now just fine. Even rebooting via pushbutton-reset or reset command works. I think this version is now in much better state. Thats why I removed the WIP from the subject lines. Again, this is tested on the EBV SoCrates eval board. Thanks, Stefan Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Vince Bridgers <vbridger(a)altera.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Pavel Machek <pavel(a)denx.de> Cc: Michael Trimarchi <michael(a)amarulasolutions.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com>

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[U-Boot] [PATCH] am33xx, spl, siemens: enable debug uart output again
by Heiko Schocher 15 May '15

15 May '15

a6b541b090: TI ARMv7: Don't use GD before crt0.S has set it moves the init of the debug uart at the very end of SPL code. Enable it for the siemens board earlier, as they print ddr settings ... all debug output before board_init_r() is here currently useless. Maybe we must rework this globally? Signed-off-by: Heiko Schocher <hs(a)denx.de> --- board/siemens/common/board.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index cc0ac6b..fb2de48 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -43,6 +43,11 @@ void set_mux_conf_regs(void) /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_set_bus_num(0); + + /* enable early the console */ + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; if (read_eeprom() < 0) puts("Could not get board ID.\n"); -- 2.1.0

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[U-Boot] [PATCH v2] misc: led: Add PCA9551 LED driver
by Stefan Roese 10 May '15

10 May '15

This patch adds a driver for the PCA9551 LED controller. Originated-by: Timo Herbrecher <t.herbrecher(a)gateware.de> Signed-off-by: Stefan Roese <sr(a)denx.de> Reviewed-by: Tom Rini <trini(a)konsulko.com> Cc: Fabio Estevam <festevam(a)gmail.com> --- v2: - Removed __packed fromstruct pca9551_blink_rate as it doesn't seem to be needed - Removed PCA9551 dependency from Kconfig to allow usage with other boards - Better handling of return codes as suggested by Fabio drivers/misc/Kconfig | 13 ++++ drivers/misc/Makefile | 1 + drivers/misc/pca9551_led.c | 155 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 169 insertions(+) create mode 100644 drivers/misc/pca9551_led.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 36a8f0d..4114be3 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -61,3 +61,16 @@ config CONFIG_FSL_SEC_MON system states. Security Monitor can be transitioned on any security failures, like software violations or hardware security violations. + +config PCA9551_LED + bool "Enable PCA9551 LED driver" + help + Enable driver for PCA9551 LED controller. This controller + is connected via I2C. So I2C needs to be enabled. + +config PCA9551_I2C_ADDR + hex "I2C address of PCA9551 LED controller" + depends on PCA9551_LED + default 0x60 + help + The I2C address of the PCA9551 LED controller. diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 6028cd4..149e686 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -29,3 +29,4 @@ obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o +obj-$(CONFIG_PCA9551_LED) += pca9551_led.o diff --git a/drivers/misc/pca9551_led.c b/drivers/misc/pca9551_led.c new file mode 100644 index 0000000..79b1e20 --- /dev/null +++ b/drivers/misc/pca9551_led.c @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2015 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <i2c.h> + +#ifndef CONFIG_PCA9551_I2C_ADDR +#error "CONFIG_PCA9551_I2C_ADDR not defined!" +#endif + +#define PCA9551_REG_INPUT 0x00 /* Input register (read only) */ +#define PCA9551_REG_PSC0 0x01 /* Frequency prescaler 0 */ +#define PCA9551_REG_PWM0 0x02 /* PWM0 */ +#define PCA9551_REG_PSC1 0x03 /* Frequency prescaler 1 */ +#define PCA9551_REG_PWM1 0x04 /* PWM1 */ +#define PCA9551_REG_LS0 0x05 /* LED0 to LED3 selector */ +#define PCA9551_REG_LS1 0x06 /* LED4 to LED7 selector */ + +#define PCA9551_CTRL_AI (1 << 4) /* Auto-increment flag */ + +#define PCA9551_LED_STATE_ON 0x00 +#define PCA9551_LED_STATE_OFF 0x01 +#define PCA9551_LED_STATE_BLINK0 0x02 +#define PCA9551_LED_STATE_BLINK1 0x03 + +struct pca9551_blink_rate { + u8 psc; /* Frequency preescaler, see PCA9551_7.pdf p. 6 */ + u8 pwm; /* Pulse width modulation, see PCA9551_7.pdf p. 6 */ +}; + +static int freq0, freq1; + +static int pca9551_led_get_state(int led, int *state) +{ + unsigned int reg; + u8 shift, buf; + int ret; + + if (led < 0 || led > 7) { + return -EINVAL; + } else if (led < 4) { + reg = PCA9551_REG_LS0; + shift = led << 1; + } else { + reg = PCA9551_REG_LS1; + shift = (led - 4) << 1; + } + + ret = i2c_read(CONFIG_PCA9551_I2C_ADDR, reg, 1, &buf, 1); + if (ret) + return ret; + + *state = (buf >> shift) & 0x03; + return 0; +} + +static int pca9551_led_set_state(int led, int state) +{ + unsigned int reg; + u8 shift, buf, mask; + int ret; + + if (led < 0 || led > 7) { + return -EINVAL; + } else if (led < 4) { + reg = PCA9551_REG_LS0; + shift = led << 1; + } else { + reg = PCA9551_REG_LS1; + shift = (led - 4) << 1; + } + mask = 0x03 << shift; + + ret = i2c_read(CONFIG_PCA9551_I2C_ADDR, reg, 1, &buf, 1); + if (ret) + return ret; + + buf = (buf & ~mask) | ((state & 0x03) << shift); + + ret = i2c_write(CONFIG_PCA9551_I2C_ADDR, reg, 1, &buf, 1); + if (ret) + return ret; + + return 0; +} + +static int pca9551_led_set_blink_rate(int idx, struct pca9551_blink_rate rate) +{ + unsigned int reg; + int ret; + + switch (idx) { + case 0: + reg = PCA9551_REG_PSC0; + break; + case 1: + reg = PCA9551_REG_PSC1; + break; + default: + return -EINVAL; + } + reg |= PCA9551_CTRL_AI; + + ret = i2c_write(CONFIG_PCA9551_I2C_ADDR, reg, 1, (u8 *)&rate, 2); + if (ret) + return ret; + + return 0; +} + +/* + * Functions referenced by cmd_led.c + */ +void __led_set(led_id_t mask, int state) +{ + if (state == STATUS_LED_OFF) + pca9551_led_set_state(mask, PCA9551_LED_STATE_OFF); + else + pca9551_led_set_state(mask, PCA9551_LED_STATE_ON); +} + +void __led_toggle(led_id_t mask) +{ + int state = 0; + + pca9551_led_get_state(mask, &state); + pca9551_led_set_state(mask, !state); +} + +void __led_blink(led_id_t mask, int freq) +{ + struct pca9551_blink_rate rate; + int mode; + int blink; + + if ((freq0 == 0) || (freq == freq0)) { + blink = 0; + mode = PCA9551_LED_STATE_BLINK0; + freq0 = freq; + } else { + blink = 1; + mode = PCA9551_LED_STATE_BLINK1; + freq1 = freq; + } + + rate.psc = ((freq * 38) / 1000) - 1; + rate.pwm = 128; /* 50% duty cycle */ + + pca9551_led_set_blink_rate(blink, rate); + pca9551_led_set_state(mask, mode); +} -- 2.3.2

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[U-Boot] [PATCH V2] sf: Add support for flag status register on Micron chips
by Hou Zhiqiang 09 May '15

09 May '15

Enter 3 Byte address mode at first, because it may change to 4 Byte address mode in kernel driver and not reset to 3 Byte address mode after reboot. Add clear flag status register operation that some Micron SPI flash chips required after reading the flag status register to check some operations completion. Signed-off-by: Hou Zhiqiang <B48286(a)freescale.com> Signed-off-by: Mingkai.Hu <Mingkai.Hu(a)freescale.com> --- V1: Based on git://git.denx.de/u-boot.git. Also can be applied to git://www.denx.de/git/u-boot-mpc85xx.git. Tested on board T2080QDS and T2080RDB. V2: Add the operation of enter 3 Byte address mode in probe. drivers/mtd/spi/sf_internal.h | 17 ++++++++++++ drivers/mtd/spi/sf_ops.c | 64 +++++++++++++++++++++++++++++++++++++------ drivers/mtd/spi/sf_probe.c | 5 ++++ 3 files changed, 78 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 19d4914..49e5a2c 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -36,6 +36,11 @@ #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 +#define CMD_CLEAR_FLAG_STATUS 0x50 + +/* Used for Macronix and Winbond flashes */ +#define CMD_ENTER_4B_ADDR 0xB7 +#define CMD_EXIT_4B_ADDR 0xE9 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -59,6 +64,8 @@ #define STATUS_QEB_WINSPAN (1 << 1) #define STATUS_QEB_MXIC (1 << 6) #define STATUS_PEC (1 << 7) +#define STATUS_PROT (1 << 1) +#define STATUS_ERASE (1 << 5) #ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN #define STATUS_SRWD (1 << 7) /* SR write protect */ @@ -124,6 +131,12 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); } +/* Clear flag status register */ +static inline int spi_flash_cmd_clear_flag_status(struct spi_flash *flash) +{ + return spi_flash_cmd(flash->spi, CMD_CLEAR_FLAG_STATUS, NULL, 0); +} + /* * Send the read status command to the device and wait for the wip * (write-in-progress) bit to clear itself. @@ -160,4 +173,8 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data); +#if defined(CONFIG_SPI_FLASH_STMICRO) +int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable); +#endif + #endif /* _SF_INTERNAL_H_ */ diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 85cf22d..8a532b8 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -93,6 +93,30 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) } #endif +#if defined(CONFIG_SPI_FLASH_STMICRO) +int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable) +{ + int ret; + u8 cmd; + + cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: unable to claim SPI bus\n"); + return ret; + } + + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); + return ret; + } + + return spi_flash_cmd(flash->spi, cmd, NULL, 0); +} +#endif + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) { @@ -160,6 +184,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) unsigned long timebase; unsigned long flags = SPI_XFER_BEGIN; int ret; + int out_of_time = 1; u8 status; u8 check_status = 0x0; u8 poll_bit = STATUS_WIP; @@ -186,22 +211,45 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) WATCHDOG_RESET(); ret = spi_xfer(spi, 8, NULL, &status, 0); - if (ret) + if (ret) { + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); return -1; + } - if ((status & poll_bit) == check_status) + if ((status & poll_bit) == check_status) { + out_of_time = 0; break; + } } while (get_timer(timebase) < timeout); spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); - if ((status & poll_bit) == check_status) - return 0; + if (out_of_time) { + /* Timed out */ + debug("SF: time out!\n"); + if (cmd == CMD_FLAG_STATUS) { + if (spi_flash_cmd_clear_flag_status(flash) < 0) + debug("SF: clear flag status failed\n"); + } + ret = -1; + } +#ifdef CONFIG_SPI_FLASH_STMICRO + else if (cmd == CMD_FLAG_STATUS) { + if (!(status & (STATUS_PROT | STATUS_ERASE))) { + ret = 0; + } else { + debug("SF: flag status error"); + ret = -1; + } - /* Timed out */ - debug("SF: time out!\n"); - return -1; + if (spi_flash_cmd_clear_flag_status(flash) < 0) { + debug("SF: clear flag status failed\n"); + ret = -1; + } + } +#endif + return ret; } int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, @@ -234,7 +282,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, ret = spi_flash_cmd_wait_ready(flash, timeout); if (ret < 0) { - debug("SF: write %s timed out\n", + debug("SF: write %s failed\n", timeout == SPI_FLASH_PROG_TIMEOUT ? "program" : "page erase"); return ret; diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 4d148d1..79b876d 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -221,6 +221,11 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, #ifdef CONFIG_SPI_FLASH_STMICRO if (params->flags & E_FSR) flash->poll_cmd = CMD_FLAG_STATUS; + + if (flash->size > SPI_FLASH_16MB_BOUN) { + if (spi_flash_cmd_4B_addr_switch(flash, 0) < 0) + debug("SF: enter 3B address mode failed\n"); + } #endif /* Configure the BAR - discover bank cmds and read current bank */ -- 2.1.0.27.g96db324

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[U-Boot] Recommended SH toolchain
by Vasili Galka 08 May '15

08 May '15

Hi Nobuhiro, I'm trying to verify the correct build of all SH boards in U-Boot. What is the recommended toolchain to use? I tried the one from kernel.org [1], but it does not work for all the boards, I get build errors like this one: Building rsk7203 board... sh4-linux-gcc: error: command line option '-m3e' is not supported by this configuration sh4-linux-gcc: error: command line option '-m3e' is not supported by this configuration make[3]: *** [include/autoconf.mk] Error 1 make[3]: *** [include/autoconf.mk.dep] Error 1 make[2]: *** [silentoldconfig] Error 1 make: *** [sub-make] Error 2 sh4-linux-size: '/home/lab/dev/u-boot/out/all_sh/u-boot': No such file sh4-linux-gcc: error: command line option '-m3e' is not supported by this configuration sh4-linux-gcc: error: command line option '-m3e' is not supported by this configuration make[3]: *** [include/autoconf.mk] Error 1 make[3]: *** Waiting for unfinished jobs.... make[3]: *** [include/autoconf.mk.dep] Error 1 'make -f /home/lab/dev/u-boot/scripts/Makefile.autoconf obj=include include/autoconf.mk include/autoconf.mk.dep' Failed make[2]: *** [silentoldconfig] Error 1 make[1]: *** No rule to make target `include/config/auto.conf', needed by `include/config/uboot.release'. Stop. make: *** [sub-make] Error 2 I'll appreciate your help. [1] https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ Regards, Vasili

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[U-Boot] [PATCH v2 0/9] PSCI v0.2 framework for ARMv8
by Arnab Basu 08 May '15

08 May '15

Apologies for the long delay, this is v2 of the series of patches that creates a generic PSCI v0.2 framework for ARMv8. The first 3 patches refactor existing code so that ARMv7 PSCI, ARMv8 spin-table and ARMv8 PSCI can coexist. The 4th patch modifies the spin table implementation for the ARMv8 foundation model to create per cpu release addresses The next 5 patches create a generic framework for PSCI v0.2 in ARMv8. The implementation is modelled on the pre-existing PSCI v0.1 support in ARMv7. PSCI support patches for the ARMv8 Foundation model that implement the mandatory PSCI functions and enable PCSI will follow very soon. Arnab Basu (9): ARM: PSCI: Update psci.h for psci v0.2 ARM: PSCI: Alow arch specific DT patching ARMv8/fsl-lsch3: Refactor spin-table code vexpress_aemv8a: Add spin table handling with per cpu release addresses ARMv8: PSCI: Add linker section to hold PSCI code ARMv8: PCSI: Add generic ARMv8 PSCI code ARMv8: PSCI: Fixup the device tree for PSCI v0.2 ARMv8: PSCI: Setup ARMv8 PSCI ARMv8: PSCI: Enable SMC arch/arm/config.mk | 2 +- arch/arm/cpu/armv7/virt-dt.c | 7 +- arch/arm/cpu/armv8/Makefile | 4 +- arch/arm/cpu/armv8/cpu-dt.c | 189 +++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/cpu.c | 136 ++++++++++++++++++++++++++ arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 48 ++++------ arch/arm/cpu/armv8/psci.S | 168 +++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/start.S | 141 ++++++++++++++++++++------- arch/arm/cpu/armv8/u-boot.lds | 30 ++++++ arch/arm/include/asm/armv8/esr.h | 12 +++ arch/arm/include/asm/armv8/mp.h | 36 +++++++ arch/arm/include/asm/config.h | 1 + arch/arm/include/asm/macro.h | 5 + arch/arm/include/asm/psci.h | 42 ++++++++- arch/arm/include/asm/system.h | 7 ++ arch/arm/lib/bootm-fdt.c | 11 ++- arch/arm/lib/bootm.c | 3 + include/configs/vexpress_aemv8a.h | 2 + 18 files changed, 772 insertions(+), 72 deletions(-) create mode 100644 arch/arm/cpu/armv8/cpu-dt.c create mode 100644 arch/arm/cpu/armv8/psci.S create mode 100644 arch/arm/include/asm/armv8/esr.h create mode 100644 arch/arm/include/asm/armv8/mp.h -- 1.9.1

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[U-Boot] [PATCH] tools/kwbimage.c: Correct header size for SPI boot
by Kevin Smith 07 May '15

07 May '15

If defined, the macro CONFIG_SYS_SPI_U_BOOT_OFFS allows a board to specify the offset of the payload image into the kwb image file. This value was being used to locate the image, but was not used in the "header size" field of the main header. Move the use of this macro into the function that returns the header size so that the same value is used in all places. Signed-off-by: Kevin Smith <kevin.smith(a)elecsyscorp.com> --- tools/kwbimage.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 9540e7e..1ff17ca 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -420,6 +420,18 @@ static size_t image_headersz_v1(struct image_tool_params *params, *hasext = 1; } +#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) + if (headersz > CONFIG_SYS_SPI_U_BOOT_OFFS) { + fprintf(stderr, "Error: Image header (incl. SPL image) too big!\n"); + fprintf(stderr, "header=0x%x CONFIG_SYS_SPI_U_BOOT_OFFS=0x%x!\n", + (int)headersz, CONFIG_SYS_SPI_U_BOOT_OFFS); + fprintf(stderr, "Increase CONFIG_SYS_SPI_U_BOOT_OFFS!\n"); + return 0; + } else { + headersz = CONFIG_SYS_SPI_U_BOOT_OFFS; + } +#endif + /* * The payload should be aligned on some reasonable * boundary @@ -869,16 +881,6 @@ static int kwbimage_generate(struct image_tool_params *params, sizeof(struct ext_hdr_v0); } else { alloc_len = image_headersz_v1(params, NULL); -#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) - if (alloc_len > CONFIG_SYS_SPI_U_BOOT_OFFS) { - fprintf(stderr, "Error: Image header (incl. SPL image) too big!\n"); - fprintf(stderr, "header=0x%x CONFIG_SYS_SPI_U_BOOT_OFFS=0x%x!\n", - alloc_len, CONFIG_SYS_SPI_U_BOOT_OFFS); - fprintf(stderr, "Increase CONFIG_SYS_SPI_U_BOOT_OFFS!\n"); - } else { - alloc_len = CONFIG_SYS_SPI_U_BOOT_OFFS; - } -#endif } hdr = malloc(alloc_len); -- 2.3.2

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[U-Boot] [PATCH] autoboot.c: Add feature to stop autobooting via SHA256 encrypted password
by Stefan Roese 05 May '15

05 May '15

This patch adds the feature to only stop the autobooting, and therefor boot into the U-Boot prompt, when the input string / password matches a values that is encypted via a SHA256 hash and saved in the environment. This feature is enabled by defined these config options: CONFIG_AUTOBOOT_KEYED CONFIG_AUTOBOOT_STOP_STR_SHA256 Signed-off-by: Stefan Roese <sr(a)denx.de> --- common/autoboot.c | 45 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/common/autoboot.c b/common/autoboot.c index c27cc2c..4635551 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -12,6 +12,7 @@ #include <fdtdec.h> #include <menu.h> #include <post.h> +#include <u-boot/sha256.h> DECLARE_GLOBAL_DATA_PTR; @@ -35,6 +36,11 @@ static int abortboot_keyed(int bootdelay) { int abort = 0; uint64_t etime = endtick(bootdelay); +#if defined(CONFIG_AUTOBOOT_STOP_STR_SHA256) + const char *sha_env_str = getenv("bootstopkeysha256"); + u8 sha_env[SHA256_SUM_LEN]; + u8 sha[SHA256_SUM_LEN]; +#else struct { char *str; u_int len; @@ -46,10 +52,11 @@ static int abortboot_keyed(int bootdelay) { .str = getenv("bootstopkey"), .retry = 0 }, { .str = getenv("bootstopkey2"), .retry = 0 }, }; + u_int presskey_max = 0; +#endif char presskey[MAX_DELAY_STOP_STR]; u_int presskey_len = 0; - u_int presskey_max = 0; u_int i; #ifndef CONFIG_ZERO_BOOTDELAY_CHECK @@ -61,6 +68,41 @@ static int abortboot_keyed(int bootdelay) printf(CONFIG_AUTOBOOT_PROMPT); # endif +#if defined(CONFIG_AUTOBOOT_STOP_STR_SHA256) + if (sha_env_str == NULL) + sha_env_str = CONFIG_AUTOBOOT_STOP_STR_SHA256; + + /* + * Generate the binary value from the environment hash value + * so that we can compare this value with the computed hash + * from the user input + */ + for (i = 0; i < SHA256_SUM_LEN; i++) { + char chr[3]; + + strncpy(chr, &sha_env_str[i * 2], 2); + sha_env[i] = simple_strtoul(chr, NULL, 16); + } + + /* + * We don't know how long the stop-string is, so we need to + * generate the sha256 hash upon each input character and + * compare the value with the one saved in the environment + */ + do { + if (tstc()) { + presskey[presskey_len++] = getc(); + + /* Calculate sha256 upon each new char */ + sha256_csum_wd((unsigned char *)presskey, presskey_len, + sha, CHUNKSZ_SHA256); + + /* And check if sha matches saved value in env */ + if (memcmp(sha, sha_env, SHA256_SUM_LEN) == 0) + abort = 1; + } + } while (!abort && get_ticks() <= etime); +#else # ifdef CONFIG_AUTOBOOT_DELAY_STR if (delaykey[0].str == NULL) delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR; @@ -124,6 +166,7 @@ static int abortboot_keyed(int bootdelay) } } } while (!abort && get_ticks() <= etime); +#endif if (!abort) debug_bootkeys("key timeout\n"); -- 2.3.2

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[U-Boot] [PATCH v4] powerpc/t1023rdb: Add T1023 RDB board support
by Shengzhou Liu 05 May '15

05 May '15

T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC. T1023RDB board Overview ----------------------- - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - one 1G RGMII port on-board(RTL8211F PHY) - one 1G SGMII port on-board(RTL8211F PHY) - one 2.5G SGMII port on-board(AQR105 PHY) - PCIe: Two Mini-PCIe connectors on-board. - SerDes: 4 lanes up to 10.3125GHz - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. - USB: one Type-A USB 2.0 port with internal PHY - eSDHC: support SD/MMC card and eMMC on-board - 256Kbit M24256 I2C EEPROM - RTC: Real-time clock DS1339 on I2C bus - UART: one serial port on-board with RJ45 connector - Debugging: JTAG/COP for T1023 debugging As well updated T1024RDB to add T1023RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- v4: squashed ddr patch to this one. v3: updated readme. v2: updated the printout of serdes refclk. board/freescale/t102xrdb/MAINTAINERS | 5 ++ board/freescale/t102xrdb/Makefile | 2 +- board/freescale/t102xrdb/README | 97 ++++++++++++++++++++++++++------- board/freescale/t102xrdb/ddr.c | 78 +++++++++++++++++++++++++- board/freescale/t102xrdb/eth_t102xrdb.c | 27 ++++++++- board/freescale/t102xrdb/t1023_rcw.cfg | 8 +++ board/freescale/t102xrdb/t102xrdb.c | 93 ++++++++++++++++++++++++++++++- board/freescale/t102xrdb/t102xrdb.h | 4 +- configs/T1023RDB_NAND_defconfig | 5 ++ configs/T1023RDB_SDCARD_defconfig | 5 ++ configs/T1023RDB_SECURE_BOOT_defconfig | 4 ++ configs/T1023RDB_SPIFLASH_defconfig | 5 ++ configs/T1023RDB_defconfig | 4 ++ configs/T1024RDB_NAND_defconfig | 2 +- configs/T1024RDB_SDCARD_defconfig | 2 +- configs/T1024RDB_SECURE_BOOT_defconfig | 2 +- configs/T1024RDB_SPIFLASH_defconfig | 2 +- configs/T1024RDB_defconfig | 2 +- include/configs/T102xRDB.h | 79 +++++++++++++++++++++++---- 19 files changed, 382 insertions(+), 44 deletions(-) create mode 100644 board/freescale/t102xrdb/t1023_rcw.cfg create mode 100644 configs/T1023RDB_NAND_defconfig create mode 100644 configs/T1023RDB_SDCARD_defconfig create mode 100644 configs/T1023RDB_SECURE_BOOT_defconfig create mode 100644 configs/T1023RDB_SPIFLASH_defconfig create mode 100644 configs/T1023RDB_defconfig diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS index dc554d4..297e63a 100644 --- a/board/freescale/t102xrdb/MAINTAINERS +++ b/board/freescale/t102xrdb/MAINTAINERS @@ -8,3 +8,8 @@ F: configs/T1024RDB_NAND_defconfig F: configs/T1024RDB_SDCARD_defconfig F: configs/T1024RDB_SPIFLASH_defconfig F: configs/T1024RDB_SECURE_BOOT_defconfig +F: configs/T1023RDB_defconfig +F: configs/T1023RDB_NAND_defconfig +F: configs/T1023RDB_SDCARD_defconfig +F: configs/T1023RDB_SPIFLASH_defconfig +F: configs/T1023RDB_SECURE_BOOT_defconfig diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile index a0cf8f6..0520066 100644 --- a/board/freescale/t102xrdb/Makefile +++ b/board/freescale/t102xrdb/Makefile @@ -8,7 +8,7 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-y += t102xrdb.o -obj-y += cpld.o +obj-$(CONFIG_T1024RDB) += cpld.o obj-y += eth_t102xrdb.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index 2b17f50..922450e 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -98,6 +98,30 @@ T1024RDB board Overview - Four I2C ports +T1023RDB board Overview +----------------------- +- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz +- CoreNet fabric supporting coherent and noncoherent transactions with + prioritization and bandwidth allocation +- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC +- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC +- Ethernet interfaces: + - one 1G RGMII port on-board(RTL8211FS PHY) + - one 1G SGMII port on-board(RTL8211FS PHY) + - one 2.5G SGMII port on-board(AQR105 PHY) +- PCIe: Two Mini-PCIe connectors on-board. +- SerDes: 4 lanes up to 10.3125GHz +- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash +- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash +- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. +- USB: one Type-A USB 2.0 port with internal PHY +- eSDHC: support SD/MMC and eMMC card +- 256Kbit M24256 I2C EEPROM +- RTC: Real-time clock DS1339U on I2C bus +- UART: one serial port on-board with RJ45 connector +- Debugging: JTAG/COP for T1023 debugging + + Memory map on T1024RDB ---------------------- Start Address End Address Description Size @@ -117,29 +141,39 @@ Start Address End Address Description Size 0x0_0000_0000 0x0_ffff_ffff DDR 4GB -128MB NOR Flash memory Map --------------------------- +128MB NOR Flash Memory Layout +----------------------------- Start Address End Address Definition Max size 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB -0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB +0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB +0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB +0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB +0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB -0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB +0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB 0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB 0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB -0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB +0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB +0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB +0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB +0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB -0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB 0xE8000000 0xE801FFFF RCW (current bank) 128KB -T1024 Clock frequency ---------------------- +T1024/T1023 Clock frequency +--------------------------- BIN Core DDR Platform FMan Bin1: 1400MHz 1600MT/s 400MHz 700MHz Bin2: 1200MHz 1600MT/s 400MHz 600MHz @@ -155,16 +189,27 @@ Software configurations and board settings b. program u-boot.bin image to NOR flash => tftp 1000000 u-boot.bin => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize - set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot + on T1024RDB: + set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot + on T1023RDB: + set SW1[1:8] = '00010110', SW2[1] = '0', SW3[4] = '0' for NOR boot Switching between default bank0 and alternate bank4 on NOR flash To change boot source to vbank4: - via software: run command 'cpld reset altbank' in u-boot. - via DIP-switch: set SW3[5:7] = '100' + on T1024RDB: + via software: run command 'cpld reset altbank' in u-boot. + via DIP-switch: set SW3[5:7] = '100' + on T1023RDB: + via software: run command 'gpio vbank4' in u-boot. + via DIP-switch: set SW3[5:7] = '100' To change boot source to vbank0: - via software: run command 'cpld reset' in u-boot. - via DIP-Switch: set SW3[5:7] = '000' + on T1024RDB: + via software: run command 'cpld reset' in u-boot. + via DIP-Switch: set SW3[5:7] = '000' + on T1023RDB: + via software: run command 'gpio vbank0' in u-boot. + via DIP-switch: set SW3[5:7] = '000' 2. NAND Boot: a. build PBL image for NAND boot @@ -183,8 +228,11 @@ Software configurations and board settings b. program u-boot-with-spl-pbl.bin to SPI flash => tftp 1000000 u-boot-with-spl-pbl.bin => sf probe 0 - => sf erase 0 f0000 + => sf erase 0 100000 => sf write 1000000 0 $filesize + => tftp 1000000 fsl_fman_ucode_t1024_xx.bin + => sf erase 100000 100000 + => sf write 1000000 110000 20000 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot 4. SD Boot: @@ -236,23 +284,34 @@ Start End Definition Size 0x200000 0x27FFFF QE Firmware 512KB(1 block) +NAND Flash memory Map on T1023RDB +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x100000 0x15FFFF u-boot env 8KB +0x160000 0x17FFFF FMAN Ucode 128KB + + SD Card memory Map on T1024RDB ---------------------------------------------------- Block #blocks Definition Size 0x008 2048 u-boot img 1MB 0x800 0016 u-boot env 8KB 0x820 0256 FMAN Ucode 128KB -0x920 0256 QE Firmware 128KB +0x920 0256 QE Firmware 128KB(only T1024RDB) -SPI Flash memory Map on T1024RDB +64MB SPI Flash memory Map on T102xRDB ---------------------------------------------------- Start End Definition Size 0x000000 0x0FFFFF u-boot img 1MB 0x100000 0x101FFF u-boot env 8KB 0x110000 0x12FFFF FMAN Ucode 128KB -0x130000 0x14FFFF QE Firmware 128KB +0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB) +0x300000 0x3FFFFF device tree 128KB +0x400000 0x9FFFFF Linux kernel 6MB +0xa00000 0x3FFFFFF rootfs 54MB -For more details, please refer to T1024RDB Reference Manual and access -website www.freescale.com and Freescale QorIQ SDK Infocenter document. +For more details, please refer to T1024RDB Reference Manual +and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index a2a8f4c..adf9fd5 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -135,8 +135,83 @@ found: /* for DDR bus 32bit test on T1024 */ popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; #endif + +#ifdef CONFIG_T1023RDB + popts->wrlvl_ctl_2 = 0x07070606; + popts->half_strength_driver_enable = 1; +#endif } +#ifdef CONFIG_SYS_DDR_RAW_TIMING +/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 0x80000000, + .capacity = 0x80000000, + .primary_sdram_width = 32, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .bank_addr_bits = 2, + .bank_group_bits = 2, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + .tckmin_x_ps = 938, + .tckmax_ps = 1500, + .caslat_x = 0x000DFA00, + .taa_ps = 13500, + .trcd_ps = 13500, + .trp_ps = 13500, + .tras_ps = 33000, + .trc_ps = 46500, + .trfc1_ps = 260000, + .trfc2_ps = 160000, + .trfc4_ps = 110000, + .tfaw_ps = 25000, + .trrds_ps = 3700, + .trrdl_ps = 5300, + .tccdl_ps = 5355, + .refresh_rate_ps = 7800000, + .dq_mapping[0] = 0x0, + .dq_mapping[1] = 0x0, + .dq_mapping[2] = 0x0, + .dq_mapping[3] = 0x0, + .dq_mapping[4] = 0x0, + .dq_mapping[5] = 0x0, + .dq_mapping[6] = 0x0, + .dq_mapping[7] = 0x0, + .dq_mapping[8] = 0x0, + .dq_mapping[9] = 0x0, + .dq_mapping[10] = 0x0, + .dq_mapping[11] = 0x0, + .dq_mapping[12] = 0x0, + .dq_mapping[13] = 0x0, + .dq_mapping[14] = 0x0, + .dq_mapping[15] = 0x0, + .dq_mapping[16] = 0x0, + .dq_mapping[17] = 0x0, + .dq_mapping_ors = 1, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR4 on board"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif + #if defined(CONFIG_DEEP_SLEEP) void board_mem_sleep_setup(void) { @@ -155,8 +230,9 @@ phys_size_t initdram(int board_type) phys_size_t dram_size; #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) +#ifndef CONFIG_SYS_DDR_RAW_TIMING puts("Initializing....using SPD\n"); - +#endif dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index f611ff0..dd386bc 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -1,6 +1,8 @@ /* * Copyright 2014 Freescale Semiconductor, Inc. * + * Shengzhou Liu <Shengzhou.Liu(a)freescale.com> + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -56,6 +58,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); switch (srds_s1) { +#ifdef CONFIG_T1024RDB case 0x95: /* set the on-board RGMII2 PHY */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); @@ -63,10 +66,17 @@ int board_eth_init(bd_t *bis) /* set 10G XFI with Aquantia AQR105 PHY */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); break; +#endif + case 0x6a: + case 0x6b: case 0x77: case 0x135: /* set the on-board 2.5G SGMII AQR105 PHY */ - fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR); +#ifdef CONFIG_T1023RDB + /* set the on-board 1G SGMII RTL8211F PHY */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR); +#endif break; default: printf("SerDes protocol 0x%x is not supported on T102xRDB\n", @@ -81,6 +91,14 @@ int board_eth_init(bd_t *bis) dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; + case PHY_INTERFACE_MODE_SGMII: +#if defined(CONFIG_T1023RDB) + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); +#elif defined(CONFIG_T1024RDB) + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); +#endif + fm_info_set_mdio(i, dev); + break; case PHY_INTERFACE_MODE_SGMII_2500: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(i, dev); @@ -110,13 +128,16 @@ int board_eth_init(bd_t *bis) void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, enum fm_port port, int offset) { - if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) && - (port == FM1_DTSEC3)) { +#if defined(CONFIG_T1024RDB) + if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) || + (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && + (port == FM1_DTSEC3)) { fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); fdt_setprop(fdt, offset, "phy-connection-type", "sgmii-2500", 10); fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); } +#endif } void fdt_fixup_board_enet(void *fdt) diff --git a/board/freescale/t102xrdb/t1023_rcw.cfg b/board/freescale/t102xrdb/t1023_rcw.cfg new file mode 100644 index 0000000..fa781d6 --- /dev/null +++ b/board/freescale/t102xrdb/t1023_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header for T1023RDB +aa55aa55 010e0100 +#SerDes Protocol: 0x77 +#Core/DDR: 1400Mhz/1600MT/s with single source clock +0810000e 00000000 00000000 00000000 +3b800003 00000012 e8104000 21000000 +00000000 00000000 00000000 00020800 +00000130 04020200 00000000 00000006 diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index e196f12..f971976 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -18,11 +18,25 @@ #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "t102xrdb.h" +#ifdef CONFIG_T1024RDB #include "cpld.h" +#endif #include "../common/sleep.h" DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_T1023RDB +enum { + GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: EMMC, 1:SD/MMC */ + GPIO1_EMMC_SEL, + GPIO1_VBANK0, + GPIO1_VBANK4 = 0x00008000, /* GPIO1_16/20/22, 100:vBank4 */ + GPIO1_VBANK_MASK = 0x00008a00, + GPIO1_DIR_OUTPUT = 0x00028a00, + GPIO1_GET_VAL, +}; +#endif + int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; @@ -34,14 +48,17 @@ int checkboard(void) srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; printf("Board: %sRDB, ", cpu->name); - printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", +#ifdef CONFIG_T1024RDB + printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", CPLD_READ(hw_ver), CPLD_READ(sw_ver)); +#endif + printf("boot from "); #ifdef CONFIG_SDCARD puts("SD/MMC\n"); #elif CONFIG_SPIFLASH puts("SPI\n"); -#else +#elif defined(CONFIG_T1024RDB) u8 reg; reg = CPLD_READ(flash_csr); @@ -52,17 +69,25 @@ int checkboard(void) reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); printf("NOR vBank%d\n", reg); } +#elif defined(CONFIG_T1023RDB) +#ifdef CONFIG_NAND + puts("NAND\n"); +#else + printf("NOR vBank%d\n", (t1023rdb_gpio_ctrl(GPIO1_GET_VAL) & + GPIO1_VBANK4) >> 15 ? 4 : 0); +#endif #endif puts("SERDES Reference Clocks:\n"); if (srds_s1 == 0x95) printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); else - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]); + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]); return 0; } +#ifdef CONFIG_T1024RDB static void board_mux_lane(void) { ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -82,6 +107,7 @@ static void board_mux_lane(void) } CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN); } +#endif int board_early_init_f(void) { @@ -124,7 +150,9 @@ int board_early_init_r(void) #ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); #endif +#ifdef CONFIG_T1024RDB board_mux_lane(); +#endif return 0; } @@ -170,3 +198,62 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + + +#ifdef CONFIG_T1023RDB +static u32 t1023rdb_gpio_ctrl(u32 ctrl_type) +{ + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + u32 gpioval; + + setbits_be32(&pgpio->gpdir, GPIO1_DIR_OUTPUT); + gpioval = in_be32(&pgpio->gpdat); + + switch (ctrl_type) { + case GPIO1_SD_SEL: + gpioval |= GPIO1_SD_SEL; + break; + case GPIO1_EMMC_SEL: + gpioval &= ~GPIO1_SD_SEL; + break; + case GPIO1_VBANK0: + gpioval &= ~GPIO1_VBANK_MASK; + break; + case GPIO1_VBANK4: + gpioval &= ~GPIO1_VBANK_MASK; + gpioval |= GPIO1_VBANK4; + break; + case GPIO1_GET_VAL: + return gpioval; + default: + break; + } + out_be32(&pgpio->gpdat, gpioval); + + return 0; +} + +static int gpio_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc < 2) + return CMD_RET_USAGE; + if (!strcmp(argv[1], "vbank0")) + t1023rdb_gpio_ctrl(GPIO1_VBANK0); + else if (!strcmp(argv[1], "vbank4")) + t1023rdb_gpio_ctrl(GPIO1_VBANK4); + else if (!strcmp(argv[1], "sd")) + t1023rdb_gpio_ctrl(GPIO1_SD_SEL); + else if (!strcmp(argv[1], "EMMC")) + t1023rdb_gpio_ctrl(GPIO1_EMMC_SEL); + else + return CMD_RET_USAGE; + return 0; +} + +U_BOOT_CMD( + gpio, 2, 0, gpio_cmd, + "for vbank0/vbank4/SD/eMMC switch control in runtime", + "command (e.g. gpio vbank4)" +); +#endif diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h index 2f23579..3f5d85a 100644 --- a/board/freescale/t102xrdb/t102xrdb.h +++ b/board/freescale/t102xrdb/t102xrdb.h @@ -9,5 +9,7 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); - +#ifdef CONFIG_T1023RDB +static u32 t1023rdb_gpio_ctrl(u32 ctrl_type); +#endif #endif diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig new file mode 100644 index 0000000..23c2f03 --- /dev/null +++ b/configs/T1023RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig new file mode 100644 index 0000000..cc374ea --- /dev/null +++ b/configs/T1023RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig new file mode 100644 index 0000000..c2e2d7e --- /dev/null +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig new file mode 100644 index 0000000..e0b7116 --- /dev/null +++ b/configs/T1023RDB_SPIFLASH_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig new file mode 100644 index 0000000..a839925 --- /dev/null +++ b/configs/T1023RDB_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 73d14ab..8fd569a 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -1,5 +1,5 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" +S:CONFIG_PPC=y +S:CONFIG_MPC85xx=y +S:CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 3599f1d..e617df5 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -1,5 +1,5 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" +S:CONFIG_PPC=y +S:CONFIG_MPC85xx=y +S:CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index 8377260..be01417 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index c8ea985..b752e70 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -1,5 +1,5 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" +S:CONFIG_PPC=y +S:CONFIG_MPC85xx=y +S:CONFIG_TARGET_T102XRDB=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index e19e404..c22b3ed 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index bd40d6a..ed24e5e 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -11,6 +11,12 @@ #ifndef __T1024RDB_H #define __T1024RDB_H +#if defined(CONFIG_T1023RDB) +#ifdef CONFIG_SPL +#define CONFIG_SYS_NO_FLASH +#endif +#endif + /* High Level Configuration Options */ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO @@ -35,7 +41,9 @@ #define CONFIG_ENV_OVERWRITE /* support deep sleep */ +#ifdef CONFIG_PPC_T1024 #define CONFIG_DEEP_SLEEP +#endif #if defined(CONFIG_DEEP_SLEEP) #define CONFIG_SILENT_CONSOLE #define CONFIG_BOARD_EARLY_INIT_F @@ -43,7 +51,11 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg +#if defined(CONFIG_T1024RDB) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg +#endif #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT @@ -177,7 +189,11 @@ #define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#if defined(CONFIG_T1024RDB) #define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_T1023RDB) +#define CONFIG_ENV_SECT_SIZE 0x40000 +#endif #elif defined(CONFIG_SDCARD) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_MMC @@ -188,7 +204,11 @@ #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE 0x2000 +#if defined(CONFIG_T1024RDB) #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_T1023RDB) +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#endif #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 @@ -209,7 +229,7 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 66660000 +#define CONFIG_DDR_CLK_FREQ 100000000 /* * These can be toggled for performance analysis, otherwise use default. @@ -224,6 +244,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif +#define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_SYS_ALT_MEMTEST @@ -265,13 +286,18 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_FSL_DDR_INTERACTIVE +#if defined(CONFIG_T1024RDB) #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 - #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 - #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_SDRAM_SIZE 2048 +#endif /* * IFC Definitions @@ -291,7 +317,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ +#if defined(CONFIG_T1024RDB) #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) +#endif #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) @@ -315,6 +346,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#ifdef CONFIG_T1024RDB /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) @@ -336,6 +368,7 @@ unsigned long get_board_ddr_clk(void); FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 +#endif /* NAND Flash on IFC */ #define CONFIG_NAND_FSL_IFC @@ -352,6 +385,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#if defined(CONFIG_T1024RDB) #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ @@ -359,9 +393,17 @@ unsigned long get_board_ddr_clk(void); | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ + | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif #define CONFIG_SYS_NAND_ONFI_DETECTION - /* ONFI NAND Flash mode0 Timing Params */ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ @@ -382,8 +424,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) - #if defined(CONFIG_NAND) #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -537,7 +577,11 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_FSL_ESPI #define CONFIG_SPI_FLASH +#if defined(CONFIG_T1024RDB) #define CONFIG_SPI_FLASH_STMICRO +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SPI_FLASH_SPANSION +#endif #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_SPEED 10000000 @@ -737,8 +781,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#if defined(CONFIG_T1024RDB) #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_T1023RDB) +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) +#endif #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing @@ -763,10 +812,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PHYLIB_10G #define CONFIG_PHY_REALTEK #define CONFIG_PHY_AQUANTIA +#if defined(CONFIG_T1024RDB) #define RGMII_PHY1_ADDR 0x2 #define RGMII_PHY2_ADDR 0x6 -#define SGMII_PHY1_ADDR 0x2 +#define SGMII_AQR_PHY_ADDR 0x2 #define FM1_10GEC1_PHY_ADDR 0x1 +#elif defined(CONFIG_T1023RDB) +#define RGMII_PHY1_ADDR 0x1 +#define SGMII_RTK_PHY_ADDR 0x3 +#define SGMII_AQR_PHY_ADDR 0x2 +#endif #endif #ifdef CONFIG_FMAN_ENET @@ -856,21 +911,23 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 #define __USB_PHY_TYPE utmi #ifdef CONFIG_PPC_T1024 -#define CONFIG_BOARDNAME "t1024rdb" +#define CONFIG_BOARDNAME t1024rdb +#define BANK_INTLV cs0_cs1 #else -#define CONFIG_BOARDNAME "t1023rdb" +#define CONFIG_BOARDNAME t1023rdb +#define BANK_INTLV null #endif #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1\0" \ + "bank_intlv=" __stringify(BANK_INTLV) "\0" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] fsl/pci: Set CFG_READY for PCIe v3.0 and later
by Minghuan Lian 05 May '15

05 May '15

Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version. Signed-off-by: Ed Swarthout <Ed.Swarthout(a)freescale.com> Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian(a)freescale.com> --- arch/powerpc/include/asm/fsl_pci.h | 1 + drivers/pci/fsl_pci_init.c | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 5be718b..8bee8ca 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -19,6 +19,7 @@ #define FSL_PCI_PBFR 0x44 #define FSL_PCIE_CFG_RDY 0x4b0 +#define FSL_PCIE_V3_CFG_RDY 0x1 #define FSL_PROG_IF_AGENT 0x1 #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 231b075..1143178 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -682,8 +682,14 @@ void fsl_pci_config_unlock(struct pci_controller *hose) pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); if (pcie_cap != 0x0) { + ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr; + u32 block_rev = in_be32(&pci->block_rev1); /* PCIe - set CFG_READY bit of Configuration Ready Register */ - pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); + if (block_rev >= PEX_IP_BLK_REV_3_0) + setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY); + else + pci_hose_write_config_byte(hose, dev, + FSL_PCIE_CFG_RDY, 0x1); } else { /* PCI - clear ACL bit of PBFR */ pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); -- 1.9.1

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