March 2015 - U-Boot

[U-Boot] [PATCH v3] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue
by Zhao Qiang 05 May '15

05 May '15

T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. Soft reset PCIe can fix this issue. Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- changes for v2 - modify the commit message changes for v3 - use CONFIG_FSL_PCIE_RESET instead of CONFIG_FSL_PCIE_T2080QDS_RESET drivers/pci/fsl_pci_init.c | 15 +++++++++++++++ include/configs/T208xQDS.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 231b075..152045e 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -444,6 +444,21 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) ltssm = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; enabled = (ltssm == 0x11) ? 1 : 0; +#ifdef CONFIG_FSL_PCIE_RESET + int i; + /* assert PCIe reset */ + setbits_be32(&pci->pdb_stat, 0x08000000); + (void) in_be32(&pci->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(&pci->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { + pci_hose_read_config_word(hose, dev, PCI_LTSSM, + &ltssm); + udelay(1000); + } +#endif } else { /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */ /* enabled = ltssm >= PCI_LTSSM_L0; */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 395472b..839896a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -558,6 +558,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controler 2 */ #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCIE_RESET #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH] powerpc/t4rdb: Add SD boot support for T4240RDB board
by Chunhe Lan 05 May '15

05 May '15

This patch adds SD boot support for T4240RDB board. SPL framework is used. PBL initializes the internal RAM and copies SPL to it. Then SPL initializes DDR using SPD and copies u-boot from SD card to DDR, finally SPL transfers control to u-boot. Signed-off-by: Chunhe Lan <Chunhe.Lan(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/Kconfig | 1 + board/freescale/t4rdb/MAINTAINERS | 1 + board/freescale/t4rdb/Makefile | 6 ++- board/freescale/t4rdb/ddr.c | 6 ++- board/freescale/t4rdb/spl.c | 95 +++++++++++++++++++++++++++++++++++++ board/freescale/t4rdb/t4_pbi.cfg | 3 - board/freescale/t4rdb/t4_rcw.cfg | 6 +- board/freescale/t4rdb/tlb.c | 8 +++ configs/T4240RDB_SDCARD_defconfig | 5 ++ include/configs/T4240RDB.h | 71 ++++++++++++++++++++++++--- 10 files changed, 186 insertions(+), 16 deletions(-) create mode 100644 board/freescale/t4rdb/spl.c create mode 100644 configs/T4240RDB_SDCARD_defconfig diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index adb5bd3..27eea29 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -131,6 +131,7 @@ config TARGET_T4240QDS config TARGET_T4240RDB bool "Support T4240RDB" + select SUPPORT_SPL config TARGET_CONTROLCENTERD bool "Support controlcenterd" diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS index 845c1b6..53ccabc 100644 --- a/board/freescale/t4rdb/MAINTAINERS +++ b/board/freescale/t4rdb/MAINTAINERS @@ -5,3 +5,4 @@ F: board/freescale/t4rdb/ F: include/configs/T4240RDB.h F: configs/T4160RDB_defconfig F: configs/T4240RDB_defconfig +F: configs/T4240RDB_SDCARD_defconfig diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index 3886e3d..83b55ee 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -4,10 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-$(CONFIG_T4240RDB) += t4240rdb.o obj-y += cpld.o -obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c index 5a43c1b..27b37b5 100644 --- a/board/freescale/t4rdb/ddr.c +++ b/board/freescale/t4rdb/ddr.c @@ -108,11 +108,15 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif - puts(" DDR: "); return dram_size; } diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c new file mode 100644 index 0000000..68ecde7 --- /dev/null +++ b/board/freescale/t4rdb/spl.c @@ -0,0 +1,95 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * Author: Chunhe Lan <Chunhe.Lan(a)freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/spl.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <i2c.h> + +#include "t4rdb.h" + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + + puts("\nSD boot...\n"); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + + mmc_boot(); +} diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg index c9f8ced..e7bb673 100644 --- a/board/freescale/t4rdb/t4_pbi.cfg +++ b/board/freescale/t4rdb/t4_pbi.cfg @@ -19,9 +19,6 @@ 09000d00 00000000 09000d04 fff80000 09000d08 81000012 -#slow mdio clock -095fc030 00008148 -095fd030 00808148 #Configure alternate space 09000010 00000000 09000014 ff000000 diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg index e46c7b2..282fea4 100644 --- a/board/freescale/t4rdb/t4_rcw.cfg +++ b/board/freescale/t4rdb/t4_rcw.cfg @@ -2,6 +2,6 @@ aa55aa55 010e0100 #serdes protocol 27_55_1_9 16070019 18101916 00000000 00000000 -6c6e0848 00448c00 6c020000 f5000000 -00000000 ee0000ee 00000000 000287fc -00000000 50000000 00000000 00000028 +6c6e0848 00448c00 ec020000 f5000000 +00000000 ee0000ee 00000000 000307fc +00000000 00000000 00000000 00000028 diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 474301e..6a6b4b5 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -51,6 +51,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -91,6 +92,8 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif + #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -111,6 +114,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 18, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig new file mode 100644 index 0000000..648b789 --- /dev/null +++ b/configs/T4240RDB_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T4240RDB=y diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index b644a6c..e58d301 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -21,11 +21,53 @@ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg +#ifndef CONFIG_SDCARD +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#else +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#define CONFIG_SPL_MMC_BOOT +#endif + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif + #endif +#endif /* CONFIG_RAMBOOT_PBL */ #define CONFIG_DDR_ECC @@ -84,7 +126,16 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE (512 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -112,7 +163,11 @@ #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ #define CONFIG_MISC_INIT_R @@ -135,7 +190,7 @@ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* Serial Port - controlled on board with jumper J8 @@ -351,7 +406,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) +#define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND @@ -618,11 +673,11 @@ unsigned long get_board_ddr_clk(void); #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) -- 1.7.6.5

2 1

[U-Boot] [PATCH] drivers: usb: fsl: Workaround for Erratum A004477
by Nikhil Badola 05 May '15

05 May '15

Add a delay of 1 microsecond before issuing soft reset to the controller to let ongoing ULPI transaction complete. This prevents corruption of ULPI Function Control Register which eventually prevents phy clock from entering to low power mode Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- Depends on patch https://patchwork.ozlabs.org/patch/404879/ arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++++ drivers/usb/host/ehci-fsl.c | 10 ++++++++++ include/fsl_usb.h | 29 +++++++++++++++++++++++++++++ 4 files changed, 49 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index fe3eb06..bc59352 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -298,6 +298,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (has_erratum_a007798()) puts("Work-around for Erratum A007798 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004477 + if (has_erratum_a004477()) + puts("Work-around for Erratum A004477 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7860b40..fe9e9c1 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -161,6 +161,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 #define CONFIG_ESDHC_HC_BLK_ADDR @@ -292,6 +293,7 @@ #define CONFIG_FSL_SATA_ERRATUM_A001 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #elif defined(CONFIG_P1023) #define CONFIG_MAX_CPUS 2 @@ -372,6 +374,7 @@ #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ @@ -589,6 +592,7 @@ #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_BSC9132) @@ -613,6 +617,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_A005434 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR @@ -712,6 +717,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006475 #define CONFIG_SYS_FSL_ERRATUM_A006384 #define CONFIG_SYS_FSL_ERRATUM_A007212 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 5d4288d..41ff1a7 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -138,6 +138,16 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (has_erratum_a007798()) set_txfifothresh(ehci, TXFIFOTHRESH); + if (has_erratum_a004477()) { + /* + * When reset is issued while any ULPI transaction is ongoing + * then it may result to corruption of ULPI Function Control + * Register which eventually causes phy clock to enter low + * power mode which stops the clock. Thus delay is required + * before reset to let ongoing ULPI transaction complete. + */ + udelay(1); + } return 0; } diff --git a/include/fsl_usb.h b/include/fsl_usb.h index d251f5d..88d8a8b 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -164,6 +164,30 @@ static inline bool has_erratum_a007792(void) return false; } +static inline bool has_erratum_a004477(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P1022: + case SVR_9131: + case SVR_9132: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + case SVR_P2020: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0) || + IS_SVR_REV(svr, 2, 1); + case SVR_B4860: + case SVR_B4420: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P4080: + return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); + } + + return false; +} #else static inline bool has_erratum_a006261(void) { @@ -184,5 +208,10 @@ static inline bool has_erratum_a007792(void) { return false; } + +static inline bool has_erratum_a004477(void) +{ + return false; +} #endif #endif /*_ASM_FSL_USB_H_ */ -- 1.7.11.7

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[U-Boot] [PATCH 1/3] arm: mx6: tqma6: Fix USB and add other filesystems
by Stefan Roese 05 May '15

05 May '15

This patch fixes the USB EHCI support on the TQMa6 SoM. Additionally some filesystems are added, included the generic FS commands (e.g. ls...). Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Markus Niebel <Markus.Niebel(a)tq-group.com> Cc: Stefano Babic <sbabic(a)denx.de> --- include/configs/tqma6.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index a099687..9022550 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -125,16 +125,19 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX -#define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ /* Fuses */ #define CONFIG_MXC_OCOTP #define CONFIG_CMD_FUSE #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC #define CONFIG_DOS_PARTITION #define CONFIG_CMD_PING -- 2.3.2

5 16

[U-Boot] [PATCH] gpio: mvmfp: support newer MFP bit definitions
by Rob Herring 05 May '15

05 May '15

From: Xiang Wang <wangx(a)marvell.com> 1. The bits 11..10 for mfp driver strength is only valid for aspen and old xscale family, for newer Marvell chip, this range has been moved to 12..11. 2. add sleep bit support Signed-off-by: Xiang Wang <wangx(a)marvell.com> [robh: rebase to current mainline] Signed-off-by: Rob Herring <robh(a)kernel.org> --- drivers/gpio/mvmfp.c | 14 ++------ include/mvmfp.h | 90 +++++++++++++++++++++++++++++++--------------------- 2 files changed, 55 insertions(+), 49 deletions(-) diff --git a/drivers/gpio/mvmfp.c b/drivers/gpio/mvmfp.c index 97bbe99..43ecf66 100644 --- a/drivers/gpio/mvmfp.c +++ b/drivers/gpio/mvmfp.c @@ -43,18 +43,8 @@ void mfp_config(u32 *mfp_cfgs) /* Write a mfg register as per configuration */ val = 0; - if (cfg_val & MFP_AF_FLAG) - /* Abstract and program Afternate-Func Selection */ - val |= cfg_val & MFP_AF_MASK; - if (cfg_val & MFP_EDGE_FLAG) - /* Abstract and program Edge configuration */ - val |= cfg_val & MFP_LPM_EDGE_MASK; - if (cfg_val & MFP_DRIVE_FLAG) - /* Abstract and program Drive configuration */ - val |= cfg_val & MFP_DRIVE_MASK; - if (cfg_val & MFP_PULL_FLAG) - /* Abstract and program Pullup/down configuration */ - val |= cfg_val & MFP_PULL_MASK; + if (cfg_val & MFP_VALUE_MASK) + val |= cfg_val & MFP_VALUE_MASK; writel(val, p_mfpr); } while (1); diff --git a/include/mvmfp.h b/include/mvmfp.h index 961d799..e61e92d 100644 --- a/include/mvmfp.h +++ b/include/mvmfp.h @@ -21,61 +21,77 @@ /* * MFP configuration is represented by a 32-bit unsigned integer */ -#define MFP(_off, _pull, _pF, _drv, _dF, _edge, _eF, _afn, _aF) ( \ +#ifdef CONFIG_MVMFP_V2 +#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ + /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ + /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ + /* bit 12..11 - Driver Strength */ (((_drv) & 0x3) << 11) | \ + /* bits 10 - pad driver */ (((_slp) & 0x1) << 10) | \ + /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ + /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ + /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ + /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) +#else +#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ /* bit 12 - Unused */ \ /* bits 11..10 - Driver Strength */ (((_drv) & 0x3) << 10) | \ - /* bit 09 - Pull State flag */ (((_pF) & 0x1) << 9) | \ - /* bit 08 - Drv-strength flag */ (((_dF) & 0x1) << 8) | \ - /* bit 07 - Edge-det flag */ (((_eF) & 0x1) << 7) | \ + /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ - /* bits 03..00 - Alt-fun flag */ (((_aF) & 0x1) << 3) | \ - /* bits Alternate-fun select */ ((_afn) & 0x7)) + /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ + /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) +#endif /* * to facilitate the definition, the following macros are provided * * offset, pull,pF, drv,dF, edge,eF ,afn,aF */ -#define MFP_OFFSET_MASK MFP(0xffff, 0,0, 0,0, 0,0, 0,0) -#define MFP_REG(x) MFP(x, 0,0, 0,0, 0,0, 0,0) +#define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0) +#define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0) #define MFP_REG_GET_OFFSET(x) ((x & MFP_OFFSET_MASK) >> 16) -#define MFP_AF_FLAG MFP(0x0000, 0,0, 0,0, 0,0, 0,1) -#define MFP_DRIVE_FLAG MFP(0x0000, 0,0, 0,1, 0,0, 0,0) -#define MFP_EDGE_FLAG MFP(0x0000, 0,0, 0,0, 0,1, 0,0) -#define MFP_PULL_FLAG MFP(0x0000, 0,1, 0,0, 0,0, 0,0) +#define MFP_AF0 MFP(0x0000, 0, 0, 0, 0, 0, 0) +#define MFP_AF1 MFP(0x0000, 0, 0, 0, 0, 0, 1) +#define MFP_AF2 MFP(0x0000, 0, 0, 0, 0, 0, 2) +#define MFP_AF3 MFP(0x0000, 0, 0, 0, 0, 0, 3) +#define MFP_AF4 MFP(0x0000, 0, 0, 0, 0, 0, 4) +#define MFP_AF5 MFP(0x0000, 0, 0, 0, 0, 0, 5) +#define MFP_AF6 MFP(0x0000, 0, 0, 0, 0, 0, 6) +#define MFP_AF7 MFP(0x0000, 0, 0, 0, 0, 0, 7) +#define MFP_AF_MASK MFP(0x0000, 0, 0, 0, 0, 0, 7) + +#define MFP_SLEEP_CTRL2 MFP(0x0000, 0, 0, 0, 0, 1, 0) +#define MFP_SLEEP_DIR MFP(0x0000, 0, 0, 0, 0, 2, 0) +#define MFP_SLEEP_DATA MFP(0x0000, 0, 0, 0, 0, 4, 0) +#define MFP_SLEEP_CTRL MFP(0x0000, 0, 0, 0, 0, 8, 0) +#define MFP_SLEEP_MASK MFP(0x0000, 0, 0, 0, 0, 0xf, 0) -#define MFP_AF0 MFP(0x0000, 0,0, 0,0, 0,0, 0,1) -#define MFP_AF1 MFP(0x0000, 0,0, 0,0, 0,0, 1,1) -#define MFP_AF2 MFP(0x0000, 0,0, 0,0, 0,0, 2,1) -#define MFP_AF3 MFP(0x0000, 0,0, 0,0, 0,0, 3,1) -#define MFP_AF4 MFP(0x0000, 0,0, 0,0, 0,0, 4,1) -#define MFP_AF5 MFP(0x0000, 0,0, 0,0, 0,0, 5,1) -#define MFP_AF6 MFP(0x0000, 0,0, 0,0, 0,0, 6,1) -#define MFP_AF7 MFP(0x0000, 0,0, 0,0, 0,0, 7,1) -#define MFP_AF_MASK MFP(0x0000, 0,0, 0,0, 0,0, 7,0) +#define MFP_LPM_EDGE_NONE MFP(0x0000, 0, 0, 0, 4, 0, 0) +#define MFP_LPM_EDGE_RISE MFP(0x0000, 0, 0, 0, 1, 0, 0) +#define MFP_LPM_EDGE_FALL MFP(0x0000, 0, 0, 0, 2, 0, 0) +#define MFP_LPM_EDGE_BOTH MFP(0x0000, 0, 0, 0, 3, 0, 0) +#define MFP_LPM_EDGE_MASK MFP(0x0000, 0, 0, 0, 7, 0, 0) -#define MFP_LPM_EDGE_NONE MFP(0x0000, 0,0, 0,0, 0,1, 0,0) -#define MFP_LPM_EDGE_RISE MFP(0x0000, 0,0, 0,0, 1,1, 0,0) -#define MFP_LPM_EDGE_FALL MFP(0x0000, 0,0, 0,0, 2,1, 0,0) -#define MFP_LPM_EDGE_BOTH MFP(0x0000, 0,0, 0,0, 3,1, 0,0) -#define MFP_LPM_EDGE_MASK MFP(0x0000, 0,0, 0,0, 3,0, 0,0) +#define MFP_SLP_DI MFP(0x0000, 0, 0, 1, 0, 0, 0) -#define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0,0, 0,1, 0,0, 0,0) -#define MFP_DRIVE_SLOW MFP(0x0000, 0,0, 1,1, 0,0, 0,0) -#define MFP_DRIVE_MEDIUM MFP(0x0000, 0,0, 2,1, 0,0, 0,0) -#define MFP_DRIVE_FAST MFP(0x0000, 0,0, 3,1, 0,0, 0,0) -#define MFP_DRIVE_MASK MFP(0x0000, 0,0, 3,0, 0,0, 0,0) +#define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0, 0, 0, 0, 0, 0) +#define MFP_DRIVE_SLOW MFP(0x0000, 0, 1, 0, 0, 0, 0) +#define MFP_DRIVE_MEDIUM MFP(0x0000, 0, 2, 0, 0, 0, 0) +#define MFP_DRIVE_FAST MFP(0x0000, 0, 3, 0, 0, 0, 0) +#define MFP_DRIVE_MASK MFP(0x0000, 0, 3, 0, 0, 0, 0) -#define MFP_PULL_NONE MFP(0x0000, 0,1, 0,0, 0,0, 0,0) -#define MFP_PULL_LOW MFP(0x0000, 1,1, 0,0, 0,0, 0,0) -#define MFP_PULL_HIGH MFP(0x0000, 2,1, 0,0, 0,0, 0,0) -#define MFP_PULL_BOTH MFP(0x0000, 3,1, 0,0, 0,0, 0,0) -#define MFP_PULL_FLOAT MFP(0x0000, 4,1, 0,0, 0,0, 0,0) -#define MFP_PULL_MASK MFP(0x0000, 7,0, 0,0, 0,0, 0,0) +#define MFP_PULL_NONE MFP(0x0000, 0, 0, 0, 0, 0, 0) +#define MFP_PULL_LOW MFP(0x0000, 5, 0, 0, 0, 0, 0) +#define MFP_PULL_HIGH MFP(0x0000, 6, 0, 0, 0, 0, 0) +#define MFP_PULL_BOTH MFP(0x0000, 7, 0, 0, 0, 0, 0) +#define MFP_PULL_FLOAT MFP(0x0000, 4, 0, 0, 0, 0, 0) +#define MFP_PULL_MASK MFP(0x0000, 7, 0, 0, 0, 0, 0) +#define MFP_VALUE_MASK (MFP_PULL_MASK | MFP_DRIVE_MASK | MFP_SLP_DI \ + | MFP_LPM_EDGE_MASK | MFP_SLEEP_MASK \ + | MFP_AF_MASK) #define MFP_EOC 0xffffffff /* indicates end-of-conf */ /* Functions */ -- 2.1.0

3 8

[U-Boot] [PATCH 0/6] mmc: Fix OCR polling and splitted initialization
by Andrew Gabbasov 05 May '15

05 May '15

Patch 4 contains a fix for a problem that really occures with some MMC cards, that are capable to get to ready state within a single polling call. Patch 6 is a fix for an error, that may be not so important and is not visible at the moment, since no platform does actually use pre-initialization. However, it still makes sense to fix it. It also makes the code more clean, straightforward, and understandable. Patch 5 eliminates some unneeded delays in polling loops, thus improving overall performance. Patches 2 and 3 clean up the code, making it simpler and more correct. Patch 1 is actually not directly related to the patched code area, but just uses the occasion to fix the typo. This is a series of patches, the next patch depending on previous ones, so that should be applied in order, on top of previous ones. Andrew Gabbasov (6): mmc: Fix typo in MMC type checking macro mmc: Avoid extra duplicate entry in mmc device structure mmc: Do not pass external mmc_cmd structure to mmc_send_op_cond_iter() mmc: Continue polling MMC card for OCR only if it is still not ready mmc: Restructure polling loops to avoid extra delays mmc: Fix splitting device initialization drivers/mmc/mmc.c | 90 ++++++++++++++++++++++++++++++------------------------- include/mmc.h | 6 ++-- 2 files changed, 51 insertions(+), 45 deletions(-) -- 2.1.0

5 14

Re: [U-Boot] [PATCH 4/6] mmc: Continue polling MMC card for OCR only if it is still not ready
by Andrew Gabbasov 05 May '15

05 May '15

Hi Troy, > From: Troy Kisky [mailto:troy.kisky@boundarydevices.com] > Sent: Friday, March 20, 2015 9:39 PM > To: Peng.Fan(a)freescale.com; Gabbasov, Andrew; u-boot(a)lists.denx.de > Cc: Eric Nelson > Subject: Re: [U-Boot] [PATCH 4/6] mmc: Continue polling MMC card for OCR > only if it is still not ready > > [skipped] > > Here's another patch that solves the problem a little earlier. It has this > disadvantage of being slightly bigger, though it makes the code look better. > > https://github.com/boundarydevices/u-boot-imx6/commit/c0260ca > I have a couple of doubts regarding that patch. First, my personal taste objects to such duplicating of the code (I mean setting of version, ocr, rca, etc fields of mmc structure). If we'll have to change or add anything to these settings, we'll have to make the same change in 2 different place, which is error-prone and extremely inconvenient from maintenance point of view. Second, what about SPI mode? Doesn't this patch skip retrieving of OCR register with a special command for SPI host case (thus setting ocr field incorrectly), if the card comes to ready state with the first attempt? Thanks. Best regards, Andrew

3 5

[U-Boot] [PATCH] mmc: fix OCR Polling
by Peng Fan 05 May '15

05 May '15

If in mmc_send_op_cond, OCR_BUSY is set in CMD1's response, then state is transfered to Ready state, and there is no need to send CMD1 again. Otherwise following CMD1 will recieve no response, or timeour error from driver such as fsl_esdhc.c. If not into Ready state in previous CMD1, then continue CMD1 command. In mmc_complete_op_cond, we use the value mmc->op_cond_response from mmc_send_op_cond, since there should be no CMD1 command between mmc_send_op_cond and mmc_complete_op_cond Before fixing this, uboot log shows: " CMD_SEND:0 ARG 0x00000000 MMC_RSP_NONE CMD_SEND:8 ARG 0x000001AA MMC_RSP_R1,5,6,7 0x18EC1504 CMD_SEND:55 ARG 0x00000000 MMC_RSP_R1,5,6,7 0x18EC1504 CMD_SEND:0 ARG 0x00000000 MMC_RSP_NONE CMD_SEND:1 ARG 0x00000000 MMC_RSP_R3,4 0x00FF8080 CMD_SEND:1 ARG 0x40300000 MMC_RSP_R3,4 0xC0FF8080 --> Already OCR_BUSY set CMD_SEND:1 ARG 0x40300000 MMC_RSP_R3,4 0x0096850A --> Failed CMD1 MMC init failed " Using this patch, this issue is fixed, emmc can be detected correctly. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- drivers/mmc/mmc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index a13769e..43a9a8a 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -406,14 +406,23 @@ static int mmc_complete_op_cond(struct mmc *mmc) mmc->op_cond_pending = 0; start = get_timer(0); - do { + /* + * If in mmc_send_op_cond, OCR_BUSY is set in CMD1's response, then + * state is transfered to Ready state, and there is no need to + * send CMD1 again. Otherwise following CMD1 will recieve no response, + * or timeour error from driver such as fsl_esdhc.c. + * + * If not into Ready state in previous CMD1, then continue CMD1 + * command. + */ + while (!(mmc->op_cond_response & OCR_BUSY)) { err = mmc_send_op_cond_iter(mmc, &cmd, 1); if (err) return err; if (get_timer(start) > timeout) return UNUSABLE_ERR; udelay(100); - } while (!(mmc->op_cond_response & OCR_BUSY)); + } if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ cmd.cmdidx = MMC_CMD_SPI_READ_OCR; -- 1.8.4

2 1

[U-Boot] [PATCH 1/1] ARM: mxs: Get boot mode from OCRAM
by Jörg Krause 29 Apr '15

29 Apr '15

Reading the boot mode pins after power-up does not necessarily represent the boot mode used by the ROM loader. For example the state of a pin may have changed because a recovery switch which was pressed to enter USB mode is already released after plugging in USB. The ROM loader stores the value a fixed address in OCRAM. Use this value instead of reading the boot map pins. The GLOBAL_BOOT_MODE_ADDR for i.MX28 is taken from an U-Boot patch for the MX28EVK: http://repository.timesys.com/buildsources/u/u-boot/u-boot-2009.08/u-boot-2… Leave the boot mode detection for the i.MX23 untouched. Someone has to test whether the i.MX ROM loader does also store the boot mode in OCRAM and if the address match. This patch superseeds my incorrect patch: ARM: mxs: get boot mode from OTP http://patchwork.ozlabs.org/patch/454930/ Signed-off-by: Jörg Krause <joerg.krause(a)embedded.rocks> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 29 ++++++----------------------- 1 file changed, 6 insertions(+), 23 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index d7956e5..eb8669b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -49,13 +49,6 @@ static const iomux_cfg_t iomux_boot[] = { MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, -#elif defined(CONFIG_MX28) - MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, #endif }; @@ -65,10 +58,10 @@ static uint8_t mxs_get_bootmode_index(void) int i; uint8_t masked; +#if defined(CONFIG_MX23) /* Setup IOMUX of bootmode pads to GPIO */ mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot)); -#if defined(CONFIG_MX23) /* Setup bootmode pins as GPIO input */ gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0); gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1); @@ -83,21 +76,11 @@ static uint8_t mxs_get_bootmode_index(void) bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; #elif defined(CONFIG_MX28) - /* Setup bootmode pins as GPIO input */ - gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0); - gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1); - gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2); - gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3); - gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4); - gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5); - - /* Read bootmode pads */ - bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; + /* The global boot mode will be detected by ROM code and its value + * is stored at the fixed address 0x00019BF0 in OCRAM. + */ +#define GLOBAL_BOOT_MODE_ADDR 0x00019BF0 + bootmode = __raw_readl(GLOBAL_BOOT_MODE_ADDR); #endif for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) { -- 2.3.4

3 2

[U-Boot] [UBOOT PATCH] ci_udc: Update the ci_udc driver to support bulk transfers
by Siva Durga Prasad Paladugu 29 Apr '15

29 Apr '15

Update the ci_udc driver to support bulk transfer and also added capability of having multiple dtds if requested data is more thank 16K. These changes are tested for both the DFU and lthor. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- drivers/usb/gadget/ci_udc.c | 135 +++++++++++++++++++++++++++++++++++++------ drivers/usb/gadget/ci_udc.h | 1 + 2 files changed, 117 insertions(+), 19 deletions(-) diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 2572b34..d1d19dc 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -50,6 +50,8 @@ /* For each endpoint, we need 2 QTDs, one for each of IN and OUT */ #define ILIST_SZ (NUM_ENDPOINTS * 2 * ILIST_ENT_SZ) +#define EP_MAX_LENGTH_TRANSFER 0x4000 + #ifndef DEBUG #define DBG(x...) do {} while (0) #else @@ -102,13 +104,28 @@ static struct usb_ep_ops ci_ep_ops = { }; /* Init values for USB endpoints. */ -static const struct usb_ep ci_ep_init[2] = { +static const struct usb_ep ci_ep_init[5] = { [0] = { /* EP 0 */ .maxpacket = 64, .name = "ep0", .ops = &ci_ep_ops, }, - [1] = { /* EP 1..n */ + [1] = { + .maxpacket = 512, + .name = "ep1in-bulk", + .ops = &ci_ep_ops, + }, + [2] = { + .maxpacket = 512, + .name = "ep2out-bulk", + .ops = &ci_ep_ops, + }, + [3] = { + .maxpacket = 512, + .name = "ep3in-int", + .ops = &ci_ep_ops, + }, + [4] = { .maxpacket = 512, .name = "ep-", .ops = &ci_ep_ops, @@ -197,6 +214,19 @@ static void ci_flush_qtd(int ep_num) } /** + * ci_flush_td - flush cache over queue item + * @td: td pointer + * + * This function flushes cache for particular transfer descriptor. + */ +static void ci_flush_td(struct ept_queue_item *td) +{ + const uint32_t start = (uint32_t)td; + const uint32_t end = (uint32_t) td + ILIST_ENT_SZ; + flush_dcache_range(start, end); +} + +/** * ci_invalidate_qtd - invalidate cache over queue item * @ep_num: Endpoint number * @@ -211,6 +241,19 @@ static void ci_invalidate_qtd(int ep_num) invalidate_dcache_range(start, end); } +/** + * ci_invalidate_td - invalidate cache over queue item + * @td: td pointer + * + * This function invalidates cache for particular transfer descriptor. + */ +static void ci_invalidate_td(struct ept_queue_item *td) +{ + const uint32_t start = (uint32_t)td; + const uint32_t end = start + ILIST_ENT_SZ; + invalidate_dcache_range(start, end); +} + static struct usb_request * ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) { @@ -376,6 +419,9 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) struct ept_queue_head *head; int bit, num, len, in; struct ci_req *ci_req; + u8 *buf; + uint32_t length, actlen; + struct ept_queue_item *dtd, *qtd; ci_ep->req_primed = true; @@ -387,16 +433,41 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); len = ci_req->req.length; - item->info = INFO_BYTES(len) | INFO_ACTIVE; - item->page0 = (uint32_t)ci_req->hw_buf; - item->page1 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x1000; - item->page2 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x2000; - item->page3 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x3000; - item->page4 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x4000; - head->next = (unsigned) item; head->info = 0; + ci_req->dtd_count = 0; + buf = ci_req->hw_buf; + actlen = 0; + dtd = item; + + do { + length = min(ci_req->req.length - actlen, + (unsigned)EP_MAX_LENGTH_TRANSFER); + + dtd->info = INFO_BYTES(length) | INFO_ACTIVE; + dtd->page0 = (uint32_t)buf; + dtd->page1 = ((uint32_t)buf & 0xfffff000) + 0x1000; + dtd->page2 = ((uint32_t)buf & 0xfffff000) + 0x2000; + dtd->page3 = ((uint32_t)buf & 0xfffff000) + 0x3000; + dtd->page4 = ((uint32_t)buf & 0xfffff000) + 0x4000; + + len -= length; + actlen += length; + buf += length; + + if (len) { + qtd = (struct ept_queue_item *) + memalign(ILIST_ALIGN, ILIST_ENT_SZ); + dtd->next = (uint32_t)qtd; + dtd = qtd; + memset(dtd, 0, ILIST_ENT_SZ); + } + + ci_req->dtd_count++; + } while (len); + + item = dtd; /* * When sending the data for an IN transaction, the attached host * knows that all data for the IN is sent when one of the following @@ -432,6 +503,12 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) ci_flush_qtd(num); + item = (struct ept_queue_item *)head->next; + while (item->next != TERMINATE) { + ci_flush_td((struct ept_queue_item *)item->next); + item = (struct ept_queue_item *)item->next; + } + DBG("ept%d %s queue len %x, req %p, buffer %p\n", num, in ? "in" : "out", len, ci_req, ci_req->hw_buf); ci_flush_qh(num); @@ -497,21 +574,31 @@ static void flip_ep0_direction(void) static void handle_ep_complete(struct ci_ep *ci_ep) { - struct ept_queue_item *item; - int num, in, len; + struct ept_queue_item *item, *next_td; + int num, in, len, j; struct ci_req *ci_req; num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; item = ci_get_qtd(num, in); ci_invalidate_qtd(num); + ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); - len = (item->info >> 16) & 0x7fff; - if (item->info & 0xff) - printf("EP%d/%s FAIL info=%x pg0=%x\n", - num, in ? "in" : "out", item->info, item->page0); + next_td = item; + len = 0; + for (j = 0; j < ci_req->dtd_count; j++) { + ci_invalidate_td(next_td); + item = next_td; + len += (item->info >> 16) & 0x7fff; + if (item->info & 0xff) + printf("EP%d/%s FAIL info=%x pg0=%x\n", + num, in ? "in" : "out", item->info, item->page0); + if (j != ci_req->dtd_count - 1) + next_td = (struct ept_queue_item *)item->next; + if (j != 0) + free(item); + } - ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); list_del_init(&ci_req->queue); ci_ep->req_primed = false; @@ -847,9 +934,19 @@ static int ci_udc_probe(void) controller.gadget.ep0 = &controller.ep[0].ep; INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); - /* Init EP 1..n */ - for (i = 1; i < NUM_ENDPOINTS; i++) { - memcpy(&controller.ep[i].ep, &ci_ep_init[1], + /* Init EP 1..3 */ + for (i = 1; i < 4; i++) { + memcpy(&controller.ep[i].ep, &ci_ep_init[i], + sizeof(*ci_ep_init)); + INIT_LIST_HEAD(&controller.ep[i].queue); + controller.ep[i].req_primed = false; + list_add_tail(&controller.ep[i].ep.ep_list, + &controller.gadget.ep_list); + } + + /* Init EP 4..n */ + for (i = 4; i < NUM_ENDPOINTS; i++) { + memcpy(&controller.ep[i].ep, &ci_ep_init[4], sizeof(*ci_ep_init)); INIT_LIST_HEAD(&controller.ep[i].queue); controller.ep[i].req_primed = false; diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h index 346164a..95cc079 100644 --- a/drivers/usb/gadget/ci_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -86,6 +86,7 @@ struct ci_req { /* Buffer for the current transfer. Either req.buf/len or b_buf/len */ uint8_t *hw_buf; uint32_t hw_len; + uint32_t dtd_count; }; struct ci_ep { -- 1.7.4

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