February 2015 - U-Boot

[U-Boot] [PATCH 0/6] Allow sandbox to use config_distro_bootcmd
by Sjoerd Simons 01 Apr '15

01 Apr '15

Testing whether images will correctly boot with the standard distro bootcmds can be rather time-consuming as it tends to require flashing the images and booting on a device. Ditto for testing changes to config_distro_bootcmd. Adding support for sandbox to run distro bootcmds makes things a lot more convenient. Sjoerd Simons (6): sandbox: only do sandboxfs for hostfs interface sandbox: Add support for bootz sandbox: Implement host dev [device] config_distro_bootcmd.h: Add shared block definition for the host interface pxe: Ensure all memory access is to mapped memory sandbox: add config_distro_defaults and config_distro_bootcmd arch/sandbox/cpu/cpu.c | 20 +++++++++++ common/cmd_pxe.c | 80 +++++++++++++++++++++++------------------ common/cmd_sandbox.c | 48 +++++++++++++++++++++++++ fs/sandbox/sandboxfs.c | 5 ++- include/config_distro_bootcmd.h | 13 +++++++ include/configs/sandbox.h | 29 +++++++++++++-- 6 files changed, 157 insertions(+), 38 deletions(-) -- 2.1.4

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[U-Boot] [PATCH 1/2] spl_atmel.c: Switch s_init to board_init_f
by Tom Rini 01 Apr '15

01 Apr '15

To facilitate changing lowlevel_init to become s_init, move the current contents of s_init into board_init_f and add the rest of what board_init_f does here. Cc: Bo Shen <voice.shen(a)atmel.com> Cc: Andreas Bießmann <andreas.devel(a)googlemail.com> Tested-by: Matt Porter <mporter(a)konsulko.com> on sama5d3_xplained Signed-off-by: Tom Rini <trini(a)ti.com> --- arch/arm/cpu/at91-common/spl_atmel.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/at91-common/spl_atmel.c b/arch/arm/cpu/at91-common/spl_atmel.c index 7297530..d815050 100644 --- a/arch/arm/cpu/at91-common/spl_atmel.c +++ b/arch/arm/cpu/at91-common/spl_atmel.c @@ -58,7 +58,7 @@ static void switch_to_main_crystal_osc(void) writel(tmp, &pmc->mor); } -void s_init(void) +void board_init_f(ulong dummy) { switch_to_main_crystal_osc(); @@ -77,4 +77,9 @@ void s_init(void) preloader_console_init(); mem_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); } -- 1.7.9.5

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[U-Boot] [PATCH v2 1/2] ARM: atmel: arm9: switch to use common timer functions
by Bo Shen 01 Apr '15

01 Apr '15

Signed-off-by: Bo Shen <voice.shen(a)atmel.com> --- Changes in v2: None arch/arm/cpu/arm926ejs/at91/timer.c | 59 ---------------------------- arch/arm/include/asm/arch-at91/at91sam9260.h | 3 ++ arch/arm/include/asm/arch-at91/at91sam9261.h | 3 ++ arch/arm/include/asm/arch-at91/at91sam9263.h | 3 ++ arch/arm/include/asm/arch-at91/at91sam9g45.h | 3 ++ arch/arm/include/asm/arch-at91/at91sam9rl.h | 3 ++ arch/arm/include/asm/arch-at91/at91sam9x5.h | 3 ++ 7 files changed, 18 insertions(+), 59 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c index b0b7fb9..31ce646 100644 --- a/arch/arm/cpu/arm926ejs/at91/timer.c +++ b/arch/arm/cpu/arm926ejs/at91/timer.c @@ -33,22 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define TIMER_LOAD_VAL 0xfffff -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, gd->arch.timer_rate_hz); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= gd->arch.timer_rate_hz; - do_div(usec, 1000000); - - return usec; -} - /* * Use the PITC in full 32 bit incrementing mode */ @@ -64,54 +48,11 @@ int timer_init(void) writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16; - gd->arch.tbu = gd->arch.tbl = 0; return 0; } /* - * Get the current 64 bit timer tick count - */ -unsigned long long get_ticks(void) -{ - at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; - - ulong now = readl(&pit->piir); - - /* increment tbu if tbl has rolled over */ - if (now < gd->arch.tbl) - gd->arch.tbu++; - gd->arch.tbl = now; - return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; -} - -void __udelay(unsigned long usec) -{ - unsigned long long start; - ulong tmo; - - start = get_ticks(); /* get current timestamp */ - tmo = usec_to_tick(usec); /* convert usecs to ticks */ - while ((get_ticks() - start) < tmo) - ; /* loop till time has passed */ -} - -/* - * get_timer(base) can be used to check for timeouts or - * to measure elasped time relative to an event: - * - * ulong start_time = get_timer(0) sets start_time to the current - * time value. - * get_timer(start_time) returns the time elapsed since then. - * - * The time is used in CONFIG_SYS_HZ units! - */ -ulong get_timer(ulong base) -{ - return tick_to_time(get_ticks()) - base; -} - -/* * Return the number of timer ticks per second. */ ulong get_tbclk(void) diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h index 8950d67..1a4e84b 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260.h @@ -133,6 +133,9 @@ #define ATMEL_BASE_CS6 0x70000000 #define ATMEL_BASE_CS7 0x80000000 +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h index 6dfcf4c..914a3b0 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261.h +++ b/arch/arm/include/asm/arch-at91/at91sam9261.h @@ -117,6 +117,9 @@ #define ATMEL_BASE_CS6 0x70000000 #define ATMEL_BASE_CS7 0x80000000 +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h index 64a3888..71675ab 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263.h +++ b/arch/arm/include/asm/arch-at91/at91sam9263.h @@ -132,6 +132,9 @@ #define ATMEL_BASE_CS6 0x70000000 #define ATMEL_BASE_CS7 0x80000000 +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h index 6df8cdb..cf1c73f 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45.h @@ -136,6 +136,9 @@ #define ATMEL_BASE_CS6 0x70000000 #define ATMEL_BASE_CS7 0x80000000 +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h b/arch/arm/include/asm/arch-at91/at91sam9rl.h index 3a8e6d6..70bbf4e 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9rl.h +++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h @@ -116,6 +116,9 @@ #define ATMEL_BASE_CS4 0x50000000 /* Compact Flash Slot 0 */ #define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */ +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h index 36a5cdf..7e7b531 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h @@ -154,6 +154,9 @@ #define ATMEL_CPU_NAME get_cpu_name() #endif +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c + /* * Other misc defines */ -- 2.3.0.rc0

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[U-Boot] [PATCH] ARM: at91: sama5d4: display the U-Boot version on LCD
by Josh Wu 01 Apr '15

01 Apr '15

This patch will display the U-Boot version on LCD. Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 2 ++ board/atmel/sama5d4ek/sama5d4ek.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 1c5b92c..a8c476b 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -23,6 +23,7 @@ #include <netdev.h> #include <nand.h> #include <spi.h> +#include <version.h> DECLARE_GLOBAL_DATA_PTR; @@ -178,6 +179,7 @@ void lcd_show_board_info(void) int i; char temp[32]; + lcd_printf("%s\n", U_BOOT_VERSION); lcd_printf("2014 ATMEL Corp\n"); lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), strmhz(temp, get_cpu_clk_rate())); diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index d8ff648..b55db06 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -23,6 +23,7 @@ #include <netdev.h> #include <nand.h> #include <spi.h> +#include <version.h> DECLARE_GLOBAL_DATA_PTR; @@ -173,6 +174,7 @@ void lcd_show_board_info(void) int i; char temp[32]; + lcd_printf("%s\n", U_BOOT_VERSION); lcd_printf("2014 ATMEL Corp\n"); lcd_printf("at91(a)atmel.com\n"); lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), -- 1.9.1

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[U-Boot] [PATCH v2 0/8] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
by Albert ARIBAUD (3ADEV) 31 Mar '15

31 Mar '15

This series extends functionality for the LPC32xx platform and introduces the WORK Microwave work_92105 board which makes use of the extended functionality. NOTES: The series is not entirely checkpatch-clean. The following warnings and checks were not fixed: 1. "warning: arch/arm/Kconfig,241: please write a paragraph that describes the config symbol fully" Other symbols in the same file have no description either. For consistency, I did not add the requested description. 1. "check: include/configs/work_92105.h,177: spaces required around that ':' (ctx:VxV) (5 occurrences on the same line) This is due to the value of CONFIG_ETHADDR not being in quotes. As it never is in any other definition of CONFIG_ETHADDR, I left it unchanged. Changes in v2: - move from legacy to Driver Model support - added MUX setting for SSP0 - cosmetic: added a blank line before copyright - move boot image generation to mkimage framework Albert ARIBAUD (3ADEV) (8): lpc32xx: add Ethernet support lpc32xx: mtd: nand: add MLC NAND controller lpc32xx: i2c: add LPC32xx I2C interface support lpc32xx: add GPIO support lpc32xx: add LPC32xx SSP support (SPI mode) dtt: add ds620 support lpc32xx: add lpc32xx-spl.bin boot image target lpc32xx: add support for board work_92105 arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile | 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 13 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 43 ++ arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 80 +++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 ++ arch/arm/include/asm/arch-lpc32xx/clk.h | 16 + arch/arm/include/asm/arch-lpc32xx/config.h | 3 + arch/arm/include/asm/arch-lpc32xx/cpu.h | 3 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ arch/arm/include/asm/arch-lpc32xx/mux.h | 18 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 8 +- board/work-microwave/work_92105/Kconfig | 15 + board/work-microwave/work_92105/MAINTAINERS | 6 + board/work-microwave/work_92105/Makefile | 8 + board/work-microwave/work_92105/README | 23 + board/work-microwave/work_92105/work_92105.c | 86 +++ .../work-microwave/work_92105/work_92105_display.c | 349 +++++++++++ .../work-microwave/work_92105/work_92105_display.h | 14 + common/image.c | 1 + configs/work_92105_defconfig | 5 + drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c | 268 +++++++++ drivers/hwmon/Makefile | 1 + drivers/hwmon/ds620.c | 65 +++ drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 ++++++++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_mlc.c | 589 +++++++++++++++++++ drivers/net/Makefile | 1 + drivers/net/lpc32xx_eth.c | 636 +++++++++++++++++++++ drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 132 +++++ include/configs/work_92105.h | 259 +++++++++ include/dtt.h | 15 +- include/image.h | 1 + include/netdev.h | 1 + scripts/Makefile.spl | 9 + tools/Makefile | 1 + tools/lpc32xximage.c | 178 ++++++ 41 files changed, 3222 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 configs/work_92105_defconfig create mode 100644 drivers/gpio/lpc32xx_gpio.c create mode 100644 drivers/hwmon/ds620.c create mode 100644 drivers/i2c/lpc32xx_i2c.c create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c create mode 100644 drivers/net/lpc32xx_eth.c create mode 100644 drivers/spi/lpc32xx_ssp.c create mode 100644 include/configs/work_92105.h create mode 100644 tools/lpc32xximage.c -- 2.1.0

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[U-Boot] [PATCH 0/6] ARM: at91: SAMA5: extract the common sama5 chip configurations to a common header
by Josh Wu 30 Mar '15

30 Mar '15

This patch series reorganized the configurations for SAMA5 chips. Make the common part into one file. That way we don't need to have many copy of the same configurations. Josh Wu (6): ARM: at91: sama5d3_xplained: spl: enable PMECC header generation ARM: at91: sama5: move the common part of configurations to at91-sama5_common.h ARM: at91: sama5d3_xplained: set ENV_FAT_DEVICE_AND_PART intead of using number ARM: at91: sama5d3: mmc: save enviroment as a fat file (uboot.env) ARM: at91: sama5: move the bootcmd definition to the common header ARM: at91: at91sam9x5: mmc: save environment as a file in FAT partition. include/configs/at91-sama5_common.h | 126 ++++++++++++++++++++++++++++++++++++ include/configs/at91sam9x5ek.h | 12 ++-- include/configs/sama5d3_xplained.h | 100 ++-------------------------- include/configs/sama5d3xek.h | 114 ++------------------------------ include/configs/sama5d4_xplained.h | 116 ++------------------------------- include/configs/sama5d4ek.h | 116 ++------------------------------- 6 files changed, 153 insertions(+), 431 deletions(-) create mode 100644 include/configs/at91-sama5_common.h -- 1.9.1

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[U-Boot] [PATCH] spi: designware_spi: revisit FIFO size detection again
by Axel Lin 29 Mar '15

29 Mar '15

By specification the FIFO size would be in a range 2-256 bytes. From TX Level prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes. Hence there are currently two issues: a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be either 0 or 1 byte; b) FIFO size is incorrectly decreased by 1 which already done by meaning of TX Level register. Fixes: 501943696ea4 (spi: designware_spi: Fix detecting FIFO depth) Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- This fix is from linux-spi tree: http://git.kernel.org/cgit/linux/kernel/git/broonie/spi.git/commit/?h=for-l… drivers/spi/designware_spi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 2624844..8f5c0fc 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -164,13 +164,13 @@ static void spi_hw_init(struct dw_spi_priv *priv) if (!priv->fifo_len) { u32 fifo; - for (fifo = 2; fifo <= 256; fifo++) { + for (fifo = 1; fifo < 256; fifo++) { dw_writew(priv, DW_SPI_TXFLTR, fifo); if (fifo != dw_readw(priv, DW_SPI_TXFLTR)) break; } - priv->fifo_len = (fifo == 2) ? 0 : fifo - 1; + priv->fifo_len = (fifo == 1) ? 0 : fifo; dw_writew(priv, DW_SPI_TXFLTR, 0); } debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); -- 1.9.1

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[U-Boot] [PATCH 1/2] spi: cf_spi: Use to_cf_spi_slave to resolve cfslave from slave
by Axel Lin 29 Mar '15

29 Mar '15

Don't assume slave is always the first member of struct cf_spi_slave. Use container_of instead of casting first structure member. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- drivers/spi/cf_spi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 879a809..7453538 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -46,6 +46,11 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_MODE_MOD 0x00200000 #define SPI_DBLRATE 0x00100000 +static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave) +{ + return container_of(slave, struct cf_spi_slave, slave); +} + void cfspi_init(void) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -105,7 +110,7 @@ u16 cfspi_rx(void) int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, void *din, ulong flags) { - struct cf_spi_slave *cfslave = (struct cf_spi_slave *)slave; + struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); u16 *spi_rd16 = NULL, *spi_wr16 = NULL; u8 *spi_rd = NULL, *spi_wr = NULL; static u32 ctrl = 0; @@ -326,7 +331,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, void spi_free_slave(struct spi_slave *slave) { - free(slave); + struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); + + free(cfslave); } int spi_claim_bus(struct spi_slave *slave) -- 1.9.1

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[U-Boot] [PATCH] ARM: HYP/non-sec: relocation before enable secondary cores
by Peng Fan 27 Mar '15

27 Mar '15

If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined, smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr( _smp_pen), before code is relocated to secure ram. So need relocation to secure ram before enable secondary cores. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> --- arch/arm/cpu/armv7/virt-v7.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index b69fd37..4cb8806 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -112,13 +112,20 @@ int armv7_init_nonsec(void) for (i = 1; i <= itlinesnr; i++) writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); + /* + * Relocate secure section before any cpu runs in secure ram. + * smp_kick_all_cpus may enable other cores and runs into secure + * ram, so need to relocate secure section before enabling other + * cores. + */ + relocate_secure_section(); + #ifndef CONFIG_ARMV7_PSCI smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1); smp_kick_all_cpus(); #endif /* call the non-sec switching code on this CPU also */ - relocate_secure_section(); secure_ram_addr(_nonsec_init)(); return 0; } -- 1.8.4

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[U-Boot] [PATCH] ARMv8: bug fix of mmu setup and code optimization
by fenghua＠phytium.com.cn 27 Mar '15

27 Mar '15

From: David Feng <fenghua(a)phytium.com.cn> 1. Fix a bug of mmu_setup that variable i and j should be type long instead of int. 2. Give mmu_setup weak attribute so that other implementation can redfine it. 3. A more common set_pgtable_section(). 4. Give device memory PXN and UXN attribute. CPU may speculatively prefetch instructions from device memory, but the IO subsystem of some implementation may not support this operation. The two attributes prevent this behavior. Signed-off-by: David Feng <fenghua(a)phytium.com.cn> --- arch/arm/cpu/armv8/cache_v8.c | 73 +++++++++++++++++++++++------------- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 22 +++++------ arch/arm/include/asm/armv8/mmu.h | 71 +++++++++++++++++++---------------- 3 files changed, 95 insertions(+), 71 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index e4415e8..023dd23 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -22,55 +22,74 @@ __weak void outer_cache_flush_range(unsigned long start, unsigned long end) {} __weak void outer_cache_inval_range(unsigned long start, unsigned long end) {} #ifndef CONFIG_SYS_DCACHE_OFF -void set_pgtable_section(u64 *page_table, u64 index, u64 section, - u64 memory_type) -{ - u64 value; - value = section | PMD_TYPE_SECT | PMD_SECT_AF; - value |= PMD_ATTRINDX(memory_type); - page_table[index] = value; +/* 42 bits virtual address */ +#define VA_BITS (42) + +/* 42 bits physical address */ +#define TCR_EL1_IPS_BITS TCR_EL1_IPS_BITS_42 +#define TCR_EL2_IPS_BITS TCR_EL2_IPS_BITS_42 +#define TCR_EL3_IPS_BITS TCR_EL3_IPS_BITS_42 + +/* PTWs cacheable, inner/outer WBWA and inner-shareable */ +#define TCR_FLAGS (TCR_TG0_64K | \ + TCR_SHARED_INNER | \ + TCR_ORGN_WBWA | \ + TCR_IRGN_WBWA | \ + TCR_T0SZ(VA_BITS)) + +void set_pgtable_section(u64 *page_table, u64 index, u64 output_address, + u64 memory_type, u64 extra_flags) +{ + page_table[index] = output_address | PMD_TYPE_SECT | PMD_SECT_AF | + PMD_SECT_SHARED_INNER | PMD_ATTRINDX(memory_type) | + extra_flags; } /* to activate the MMU we need to set up virtual memory */ -static void mmu_setup(void) +void __weak mmu_setup(void) { - int i, j, el; + int el; + u64 i, j, tcr; bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr; /* Setup an identity-mapping for all spaces */ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { set_pgtable_section(page_table, i, i << SECTION_SHIFT, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, + PMD_SECT_PXN | PMD_SECT_UXN); + } - /* Setup an identity-mapping for all RAM space */ + /* + * Setup an identity-mapping for all RAM space. + * The secure or non-secure memory access make sense + * when u-boot running at el3 and is mostly implementation + * specific. + */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - ulong start = bd->bi_dram[i].start; - ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size; + u64 start = bd->bi_dram[i].start; + u64 end = bd->bi_dram[i].start + bd->bi_dram[i].size; for (j = start >> SECTION_SHIFT; j < end >> SECTION_SHIFT; j++) { set_pgtable_section(page_table, j, j << SECTION_SHIFT, - MT_NORMAL); + MT_NORMAL, PMD_SECT_NS); } } /* load TTBR0 */ + tcr = TCR_FLAGS; el = current_el(); - if (el == 1) { - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL1_IPS_BITS, - MEMORY_ATTRIBUTES); - } else if (el == 2) { - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL2_IPS_BITS, - MEMORY_ATTRIBUTES); - } else { - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL3_IPS_BITS, - MEMORY_ATTRIBUTES); - } + if (el == 1) + tcr |= TCR_EL1_IPS_BITS; + else if (el == 2) + tcr |= TCR_EL2_IPS_BITS; + else + tcr |= TCR_EL3_IPS_BITS; + + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, tcr, MEMORY_ATTRIBUTES); + /* enable the mmu */ set_sctlr(get_sctlr() | CR_M); } diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 1f36f7e..bcd2cf2 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -82,11 +82,11 @@ static inline void early_mmu_setup(void) section_l2 = 0; for (i = 0; i < 512; i++) { set_pgtable_section(level1_table_0, i, section_l1t0, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); set_pgtable_section(level1_table_1, i, section_l1t1, - MT_NORMAL); + MT_NORMAL, 0); set_pgtable_section(level2_table, i, section_l2, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); section_l1t0 += BLOCK_SIZE_L1; section_l1t1 += BLOCK_SIZE_L1; section_l2 += BLOCK_SIZE_L2; @@ -108,13 +108,13 @@ static inline void early_mmu_setup(void) set_pgtable_section(level2_table, CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, CONFIG_SYS_FSL_OCRAM_BASE, - MT_NORMAL); + MT_NORMAL, 0); for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2; i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE) >> SECTION_SHIFT_L2; i++) { section_l2 = i << SECTION_SHIFT_L2; set_pgtable_section(level2_table, i, - section_l2, MT_NORMAL); + section_l2, MT_NORMAL, 0); } el = current_el(); @@ -154,11 +154,11 @@ static inline void final_mmu_setup(void) section_l2 = 0; for (i = 0; i < 512; i++) { set_pgtable_section(level1_table_0, i, section_l1t0, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); set_pgtable_section(level1_table_1, i, section_l1t1, - MT_NORMAL); + MT_NORMAL, 0); set_pgtable_section(level2_table_0, i, section_l2, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); section_l1t0 += BLOCK_SIZE_L1; section_l1t1 += BLOCK_SIZE_L1; section_l2 += BLOCK_SIZE_L2; @@ -177,7 +177,7 @@ static inline void final_mmu_setup(void) set_pgtable_section(level2_table_0, CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, CONFIG_SYS_FSL_OCRAM_BASE, - MT_NORMAL); + MT_NORMAL, 0); /* * Fill in other part of tables if cache is needed @@ -190,7 +190,7 @@ static inline void final_mmu_setup(void) section_l2 = section_base; for (i = 0; i < 512; i++) { set_pgtable_section(level2_table_1, i, section_l2, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, 0); section_l2 += BLOCK_SIZE_L2; } tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1); @@ -200,7 +200,7 @@ static inline void final_mmu_setup(void) i < tbl_limit >> SECTION_SHIFT_L2; i++) { section_l2 = section_base + (i << SECTION_SHIFT_L2); set_pgtable_section(level2_table_1, i, - section_l2, MT_NORMAL); + section_l2, MT_NORMAL, 0); } /* flush new MMU table */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 4b7b67b..2ae5ab6 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -16,27 +16,6 @@ #define UL(x) _AC(x, UL) -/***************************************************************/ -/* - * The following definitions are related each other, shoud be - * calculated specifically. - */ -#define VA_BITS (42) /* 42 bits virtual address */ - -/* PAGE_SHIFT determines the page size */ -#undef PAGE_SIZE -#define PAGE_SHIFT 16 -#define PAGE_SIZE (1 << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -/* - * section address mask and size definitions. - */ -#define SECTION_SHIFT 29 -#define SECTION_SIZE (UL(1) << SECTION_SHIFT) -#define SECTION_MASK (~(SECTION_SIZE-1)) -/***************************************************************/ - /* * Memory types */ @@ -65,7 +44,10 @@ /* * Section */ -#define PMD_SECT_S (3 << 8) +#define PMD_SECT_NS (1 << 5) +#define PMD_SECT_SHARED_NON (0 << 8) +#define PMD_SECT_SHARED_OUTER (2 << 8) +#define PMD_SECT_SHARED_INNER (3 << 8) #define PMD_SECT_AF (1 << 10) #define PMD_SECT_NG (1 << 11) #define PMD_SECT_PXN (UL(1) << 53) @@ -97,20 +79,42 @@ #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) -#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ -#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ -#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ +#define TCR_EL1_IPS_BITS_32 (UL(0) << 32) /* 32 bits physical address */ +#define TCR_EL1_IPS_BITS_36 (UL(1) << 32) /* 36 bits physical address */ +#define TCR_EL1_IPS_BITS_40 (UL(2) << 32) /* 40 bits physical address */ +#define TCR_EL1_IPS_BITS_42 (UL(3) << 32) /* 42 bits physical address */ +#define TCR_EL1_IPS_BITS_44 (UL(4) << 32) /* 44 bits physical address */ +#define TCR_EL1_IPS_BITS_48 (UL(5) << 32) /* 48 bits physical address */ +#define TCR_EL2_IPS_BITS_32 (0 << 16) /* 32 bits physical address */ +#define TCR_EL2_IPS_BITS_36 (1 << 16) /* 36 bits physical address */ +#define TCR_EL2_IPS_BITS_40 (2 << 16) /* 40 bits physical address */ +#define TCR_EL2_IPS_BITS_42 (3 << 16) /* 42 bits physical address */ +#define TCR_EL2_IPS_BITS_44 (4 << 16) /* 44 bits physical address */ +#define TCR_EL2_IPS_BITS_48 (5 << 16) /* 48 bits physical address */ +#define TCR_EL3_IPS_BITS_32 TCR_EL2_IPS_BITS_32 +#define TCR_EL3_IPS_BITS_36 TCR_EL2_IPS_BITS_36 +#define TCR_EL3_IPS_BITS_40 TCR_EL2_IPS_BITS_40 +#define TCR_EL3_IPS_BITS_42 TCR_EL2_IPS_BITS_42 +#define TCR_EL3_IPS_BITS_44 TCR_EL2_IPS_BITS_44 +#define TCR_EL3_IPS_BITS_48 TCR_EL2_IPS_BITS_48 -/* PTWs cacheable, inner/outer WBWA and non-shareable */ -#define TCR_FLAGS (TCR_TG0_64K | \ - TCR_SHARED_NON | \ - TCR_ORGN_WBWA | \ - TCR_IRGN_WBWA | \ - TCR_T0SZ(VA_BITS)) +/***************************************************************/ +/* PAGE_SHIFT determines the page size */ +#undef PAGE_SIZE +#define PAGE_SHIFT 16 +#define PAGE_SIZE (1 << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +/* Section address mask and size definitions */ +#define SECTION_SHIFT 29 +#define SECTION_SIZE (UL(1) << SECTION_SHIFT) +#define SECTION_MASK (~(SECTION_SIZE-1)) +/***************************************************************/ #ifndef __ASSEMBLY__ -void set_pgtable_section(u64 *page_table, u64 index, - u64 section, u64 memory_type); +void set_pgtable_section(u64 *page_table, u64 index, u64 output_address, + u64 memory_type, u64 extra_flags); + static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy"); @@ -132,4 +136,5 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) asm volatile("isb"); } #endif + #endif /* _ASM_ARMV8_MMU_H_ */ -- 1.7.9.5

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