February 2015 - U-Boot

[U-Boot] spi and block bits
by Michael Walle 21 Apr '15

21 Apr '15

Hi there, I stumbled across a situation where the SPI flash on my board was write protected and i could not unlock it in the bootloader. This is especially unfortunate because the recovery mechanism relies on the bootloader to be able to erase the environment. So any ideas how to fix this? I didn't see any code which unlocks the sectors yet. We could add a lock/unlock function to the spi system, then call unlock in the beginning of saveenv() and lock at the end of saveenv(). Eg. lockbits = read_status() & LOCK_BITS spi_unlock_all() saveenv() spi_lock(lockbits) Also this should be exposed to the CLI somehow. "sf lock/unlock"? -michael

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[U-Boot] [PATCH 0/4] dm: rpi: Move Raspberry Pi to use driver model
by Simon Glass 21 Apr '15

21 Apr '15

This series adds driver model support to the GPIO and serial drivers used by Raspberry Pi, and moves Raspberry Pi over to driver model. This requires adding driver model support to the pl01x serial driver, and replacing the bcm2835 GPIO driver with a driver model version (since there are no longer clients that don't use driver model). See u-boot-dm.git branch rpi-working for the tree this is based on. Simon Glass (4): dm: rpi: Convert GPIO driver to driver model dm: serial: Tidy up the pl01x driver dm: serial: Support driver model in pl01x driver dm: rpi: Move serial to driver model arch/arm/include/asm/arch-bcm2835/gpio.h | 9 + board/raspberrypi/rpi_b/rpi_b.c | 23 ++ drivers/gpio/bcm2835_gpio.c | 180 ++++++++-- drivers/serial/Makefile | 5 +- drivers/serial/serial_pl01x.c | 373 +++++++++++++-------- .../{serial_pl01x.h => serial_pl01x_internal.h} | 0 include/configs/rpi_b.h | 11 +- include/serial_pl01x.h | 27 ++ 8 files changed, 462 insertions(+), 166 deletions(-) rename drivers/serial/{serial_pl01x.h => serial_pl01x_internal.h} (100%) create mode 100644 include/serial_pl01x.h -- 2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH 1/1] MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register
by Curt Brune 20 Apr '15

20 Apr '15

According to the MPC8555/MPC8541 reference manual the SS_EN (source synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set during initialization. >From section 9.4.1.8 of that manual: Source synchronous enable. This bit field must be set during initialization. See Section 9.6.1, "DDR SDRAM Initialization Sequence," details. 0 - Reserved 1 - The address and command are sent to the DDR SDRAMs source synchronously. In addition, Freescale application note AN2805 is also very clear that this bit must be set. This patch reverts a change introduced by commit 457caecdbca3df21a93abff19eab12dbc61b7897. Testing Done: Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS and inspected the generated assembly code to verify the SS_EN bit was being set. There is one extra instruction emitted: fff9b774: 65 29 80 00 oris r9,r9,32768 Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no additional instructions were emitted related to this patch. Booted an image on a MPC8541 based board successfully. Signed-off-by: Curt Brune <curt(a)cumulusnetworks.com> --- drivers/ddr/fsl/ctrl_regs.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 03d7ff1..6bdc47e 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1730,13 +1730,21 @@ static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) */ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) { unsigned int clk_adjust; /* Clock adjust */ + unsigned int ss_en = 0; /* Source synchronous enable */ +#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) + /* Per FSL Application Note: AN2805 */ + ss_en = 1; +#endif clk_adjust = popts->clk_adjust; - ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; + ddr->ddr_sdram_clk_cntl = (0 + | ((ss_en & 0x1) << 31) + | ((clk_adjust & 0xF) << 23) + ); debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); } /* DDR Initialization Address (DDR_INIT_ADDR) */ static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) -- 1.7.10.4

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[U-Boot] [PATCH 0/6] buildman: Support comparison of CONFIG options between commits
by Simon Glass 19 Apr '15

19 Apr '15

At present it is hard to see the changes in CONFIG between different commits in a branch. The CONFIG options exist in multiple files and the interaction between Kconfig and the board config files makes it difficult to see exactly what is going on. This series is an attempt to improve the situation. It is likely to be useful mostly to those who are converting things to Kconfig. A new .cfg file is generated during a build which includes a list of all preprocessor symbols visible to the source code. This is created for U-Boot, SPL and TPL. Its value is that it shows all CONFIGs that affect the source code, regardless of whether they come from Kconfig or board config headers. Buildman stores these files as well as the .config and autoconf files when doing a build. A new -K option allows you to see changes in the contents of these files, for example: 14: dm: Move Raspberry Pi driver model CONFIGs to Kconfig + .config: CONFIG_CMD_DM=y CONFIG_DM=y CONFIG_DM_DEVICE_REMOVE=y CONFIG_DM_GPIO=y CONFIG_DM_SERIAL=y CONFIG_DM_STDIO=y CONFIG_DM_WARN=y - autoconf.mk: CONFIG_CMD_DM=y CONFIG_DM=y CONFIG_DM_DEVICE_REMOVE=y CONFIG_DM_GPIO=y CONFIG_DM_SERIAL=y CONFIG_DM_STDIO=y CONFIG_DM_WARN=y + autoconf.h: CONFIG_CMD_DM=1 CONFIG_DM=1 CONFIG_DM_DEVICE_REMOVE=1 CONFIG_DM_GPIO=1 CONFIG_DM_SERIAL=1 CONFIG_DM_STDIO=1 CONFIG_DM_WARN=1 15: dm: exynos: Move driver model CONFIGs to Kconfig The above fragment shows that commit 14 added some options to Kconfig and removed them from autoconf. Everything looks fine. If there were any net change in the config, then it would show up in u-boot.cfg, as the following example shows: 23: dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig + .config: CONFIG_SYS_MALLOC_F=y CONFIG_SYS_MALLOC_F_LEN=0x400 - autoconf.mk: CONFIG_SYS_MALLOC_F_LEN="(1 << 10)" + autoconf.h: CONFIG_SYS_MALLOC_F=1 CONFIG_SYS_MALLOC_F_LEN=0x400 + u-boot.cfg: CONFIG_SYS_MALLOC_F=1 Here we see (from u-boot.cfg) that a new CONFIG_SYS_MALLOC_F option was added that did not exist before. The -K option is normally only useful when used with a single board, or a group of related boards. Simon Glass (6): Create a .cfg file containing the CONFIG options used to build buildman: Add a space before the list of boards buildman: Show 'make' command line when -V is used buildman: Adjust the 'aborted' heuristic for writing output buildman: Store build config files buildman: Allow comparison of build configuration Makefile | 10 ++- scripts/Makefile.spl | 9 +- tools/buildman/builder.py | 186 +++++++++++++++++++++++++++++++++++++--- tools/buildman/builderthread.py | 62 +++++++++++--- tools/buildman/cmdline.py | 4 +- tools/buildman/control.py | 3 +- tools/buildman/test.py | 2 +- 7 files changed, 244 insertions(+), 32 deletions(-) -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] u-boot for Snow problem
by Michal Suchanek 17 Apr '15

17 Apr '15

Hello, I changed the SYS_START to work around the bug in the manufacturer firmware, applied snow_defconfig, built u-boot.bin, packed it into kernel uimage, signed it, copied it to a kernel partition, bumped priority of the partition, and rebooted. I get black screen with backlight on. So 1) is u-boot supposed to have graphics console output? If so where is that output? LCD/HDMI/what HDMI mode? The only display related option in menuconfig seems to be some SPI display bridge. 2) is u-boot supposed to have serial console output? If so where is that console? There is supposed to be some 'servo' connector somewhere but I did not find any information on the pinout. 3) how do I tell if u-boot is even running? Thanks Michal

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[U-Boot] [PATCH v3] powerpc/t1040qds: Add support of SD boot for T1040QDS Board
by Vijay Rai 17 Apr '15

17 Apr '15

Add support of 2 stage SD boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - Update tlb and ddr accordingly Add T1040QDS_SDCARD_defconfig Update t1040_pbi.cfg to support errata A-007662, A-008007 and LAW for CPC1 Signed-off-by: Vijay Rai <vijay.rai(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- changes from v2: - Updated Copyright to 2015 - Updated board_need_mem_reset, now it resets DDR by default, earlier it was disabling the reset for NOR boot which is wrong - tested NOR boot and SD boot arch/powerpc/cpu/mpc85xx/Kconfig | 1 + board/freescale/t1040qds/MAINTAINERS | 5 + board/freescale/t1040qds/Makefile | 10 +- board/freescale/t1040qds/ddr.c | 4 + board/freescale/t1040qds/spl.c | 160 ++++++++++++++++++++++++++++++++ board/freescale/t1040qds/t1040_pbi.cfg | 16 +++- board/freescale/t1040qds/tlb.c | 11 +++ configs/T1040QDS_SDCARD_defconfig | 5 + include/configs/T1040QDS.h | 88 ++++++++++++++---- 9 files changed, 277 insertions(+), 23 deletions(-) create mode 100644 board/freescale/t1040qds/spl.c create mode 100644 configs/T1040QDS_SDCARD_defconfig diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index adb5bd3..635f649 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -109,6 +109,7 @@ config TARGET_T102XRDB config TARGET_T1040QDS bool "Support T1040QDS" + select SUPPORT_SPL config TARGET_T104XRDB bool "Support T104xRDB" diff --git a/board/freescale/t1040qds/MAINTAINERS b/board/freescale/t1040qds/MAINTAINERS index 83f6b3c..44d56b6 100644 --- a/board/freescale/t1040qds/MAINTAINERS +++ b/board/freescale/t1040qds/MAINTAINERS @@ -6,6 +6,11 @@ F: include/configs/T1040QDS.h F: configs/T1040QDS_defconfig F: configs/T1040QDS_D4_defconfig +T1040QDS_SDCARD BOARD +M: Priyanka Jain <Priyanka.Jain(a)freescale.com> +S: Maintained +F: configs/T1040QDS_SDCARD_defconfig + T1040QDS_SECURE_BOOT BOARD M: Aneesh Bansal <aneesh.bansal(a)freescale.com> S: Maintained diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile index 19ed21b..27eed4c 100644 --- a/board/freescale/t1040qds/Makefile +++ b/board/freescale/t1040qds/Makefile @@ -4,10 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-y += t1040qds.o -obj-y += ddr.o +obj-y += eth.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_FSL_DIU_FB) += diu.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o -obj-y += eth.o -obj-y += diu.o diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 8240240..74ad109 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -118,6 +118,7 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); @@ -126,6 +127,9 @@ phys_size_t initdram(int board_type) dram_size *= 0x100000; puts(" DDR: "); +#else + dram_size = fsl_ddr_sdram_size(); +#endif #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); diff --git a/board/freescale/t1040qds/spl.c b/board/freescale/t1040qds/spl.c new file mode 100644 index 0000000..51c5fbd --- /dev/null +++ b/board/freescale/t1040qds/spl.c @@ -0,0 +1,160 @@ +/* Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> +#include "../common/qixis.h" +#include "t1040qds_qixis.h" +#include <asm/mpc85xx_gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; +#ifdef CONFIG_SPL_NAND_BOOT + u32 porsr1, pinctl; +#endif + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#ifdef CONFIG_SPL_NAND_BOOT + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg index 10b1a6d..f7d9a74 100644 --- a/board/freescale/t1040qds/t1040_pbi.cfg +++ b/board/freescale/t1040qds/t1040_pbi.cfg @@ -1,4 +1,14 @@ #PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 #Initialize CPC1 09010000 00200400 09138000 00000000 @@ -9,9 +19,9 @@ 09010f00 08000000 09010000 80000000 #Configure LAW for CPC1 -09000cf0 00000000 -09000cf4 fffc0000 -09000cf8 81000011 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 #Configure alternate space 09000010 00000000 09000014 ff000000 diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c index 412c591..0a7ceda 100644 --- a/board/freescale/t1040qds/tlb.c +++ b/board/freescale/t1040qds/tlb.c @@ -53,6 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -82,6 +83,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -103,6 +105,15 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 11, BOOKE_PAGESZ_4K, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/T1040QDS_SDCARD_defconfig b/configs/T1040QDS_SDCARD_defconfig new file mode 100644 index 0000000..fbee8c5 --- /dev/null +++ b/configs/T1040QDS_SDCARD_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T1040QDS=y diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 92f5f56..97843c0 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -31,16 +31,54 @@ #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_E500 /* BOOKE e500 family */ +#include <asm/config_mpc85xx.h> + #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x30001000 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 +#define CONFIG_SPL_PAD_TO 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x28000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_SKIP_RELOCATE +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#define CONFIG_SYS_NO_FLASH +#endif +#define RESET_VECTOR_OFFSET 0x27FFC +#define BOOT_PAGE_OFFSET 0x27000 + +#ifdef CONFIG_SDCARD +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC_MINIMAL +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif +#define CONFIG_SPL_MMC_BOOT +#endif + #endif /* High Level Configuration Options */ #define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ @@ -78,15 +116,12 @@ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_NOWHERE -#else +#ifndef CONFIG_SYS_NO_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #endif -#ifndef CONFIG_SYS_NO_FLASH #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH @@ -102,7 +137,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) +#define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND @@ -114,10 +149,6 @@ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#else /* CONFIG_SYS_NO_FLASH */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); @@ -155,6 +186,17 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CONFIG_SYS_L3_SIZE 256 << 10 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) +#endif +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) + #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -365,7 +407,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif #if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT @@ -413,7 +459,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ +#endif /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER @@ -653,15 +701,21 @@ unsigned long get_board_ddr_clk(void); * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif + +#if defined(CONFIG_SDCARD) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) +#else #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 #endif + #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */ -- 1.7.9.5

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[U-Boot] [PATCH] arm: implement find_next_zero_bit function
by Vitaly Andrianov 16 Apr '15

16 Apr '15

This commit copies implementation of the find_next_zero_bit() from git://git.denx.de/u-boot.git/arch/mips/include/asm/bitops.h. v2014.07 The function is required to enable MCAST_TFTP support for ARM platforms. Signed-off-by: Vitaly Andrianov <vitalya(a)ti.com> --- arch/arm/include/asm/bitops.h | 43 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 597dafb..9b78043 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -95,9 +95,6 @@ static inline int __test_and_change_bit(int nr, volatile void *addr) return (old & mask) != 0; } -extern int find_first_zero_bit(void * addr, unsigned size); -extern int find_next_zero_bit(void * addr, int size, int offset); - /* * This routine doesn't need to be atomic. */ @@ -129,6 +126,43 @@ static inline unsigned long ffz(unsigned long word) return k; } +static inline int find_next_zero_bit(void *addr, int size, int offset) +{ + unsigned long *p = ((unsigned long *)addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (32-offset); + if (size < 32) + goto found_first; + if (~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size & ~31UL) { + tmp = *(p++); + if (~tmp) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL >> size; +found_middle: + return result + ffz(tmp); +} + /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word @@ -138,6 +172,9 @@ static inline unsigned long ffz(unsigned long word) #define hweight16(x) generic_hweight16(x) #define hweight8(x) generic_hweight8(x) +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + #define ext2_set_bit test_and_set_bit #define ext2_clear_bit test_and_clear_bit #define ext2_test_bit test_bit -- 1.9.1

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[U-Boot] [UBOOT PATCH] f_thor: Dont perform reset at the end of thor
by Siva Durga Prasad Paladugu 15 Apr '15

15 Apr '15

Dont perform reset at the end of thor download if configured to do reset off. Reset may not be required in all cases and hence provided an option to do so. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- drivers/usb/gadget/f_thor.c | 7 +++++++ drivers/usb/gadget/f_thor.h | 3 +++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index c85b0fb..8cf0718 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -123,6 +123,9 @@ static int process_rqt_cmd(const struct rqt_box *rqt) send_rsp(rsp); g_dnl_unregister(); dfu_free_entities(); +#ifdef CONFIG_THOR_RESET_OFF + return RESET_DONE; +#endif run_command("reset", 0); break; case RQT_CMD_POWEROFF: @@ -726,6 +729,10 @@ int thor_handle(void) if (ret > 0) { ret = process_data(); +#ifdef CONFIG_THOR_RESET_OFF + if (ret == RESET_DONE) + break; +#endif if (ret < 0) return ret; } else { diff --git a/drivers/usb/gadget/f_thor.h b/drivers/usb/gadget/f_thor.h index 833a9d2..8341285 100644 --- a/drivers/usb/gadget/f_thor.h +++ b/drivers/usb/gadget/f_thor.h @@ -121,4 +121,7 @@ struct f_thor { #define F_NAME_BUF_SIZE 32 #define THOR_PACKET_SIZE SZ_1M /* 1 MiB */ #define THOR_STORE_UNIT_SIZE SZ_32M /* 32 MiB */ +#ifdef CONFIG_THOR_RESET_OFF +#define RESET_DONE 0xFFFFFFFF +#endif #endif /* _USB_THOR_H_ */ -- 1.7.4

2 2

[U-Boot] [UBOOT PATCH] usb: gadget: f_thor: Allocate request up to THOR_PACKET_SIZE
by Siva Durga Prasad Paladugu 15 Apr '15

15 Apr '15

Allocate request up to THOR_PACKET_SIZE not the ep0->maxpacket as the descriptors data depend on the number of descriptors and this 64 bytes were not enough and the buffer might overflow which results in memalign failures later. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- drivers/usb/gadget/f_thor.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index c85b0fb..98d2d8c 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -766,7 +766,7 @@ static int thor_func_bind(struct usb_configuration *c, struct usb_function *f) goto fail; } dev->req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, - gadget->ep0->maxpacket); + THOR_PACKET_SIZE); if (!dev->req->buf) { status = -ENOMEM; goto fail; -- 1.7.4

2 2

[U-Boot] [PATCH 0/2] ARMv8: driver model enable
by fenghua＠phytium.com.cn 15 Apr '15

15 Apr '15

From: David Feng <fenghua(a)phytium.com.cn> Currently serial_pl01x.c driver contain DM and non-DM mode, but it will access static varible in non-DM mode. So, u-boot using non-DM pl01x driver can not be placed in flash. This patch set enable pre-allocation malloc that is required by DM and enable DM in vexpress64 board. David Feng (2): ARMv8: enable pre-allocation malloc ARMv8: enable DM in vexpress64 board arch/arm/include/asm/config.h | 4 ---- arch/arm/lib/crt0_64.S | 13 +++++++++++-- board/armltd/vexpress64/vexpress64.c | 13 +++++++++++++ include/configs/vexpress_aemv8a.h | 14 ++++++++++++-- 4 files changed, 36 insertions(+), 8 deletions(-) -- 1.7.9.5

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