February 2015 - U-Boot

[U-Boot] [PATCH] drivers: usb: fsl: Workaround for Erratum A004477
by Nikhil Badola 05 May '15

05 May '15

Add a delay of 1 microsecond before issuing soft reset to the controller to let ongoing ULPI transaction complete. This prevents corruption of ULPI Function Control Register which eventually prevents phy clock from entering to low power mode Signed-off-by: Nikhil Badola <nikhil.badola(a)freescale.com> --- Depends on patch https://patchwork.ozlabs.org/patch/404879/ arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++++ drivers/usb/host/ehci-fsl.c | 10 ++++++++++ include/fsl_usb.h | 29 +++++++++++++++++++++++++++++ 4 files changed, 49 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index fe3eb06..bc59352 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -298,6 +298,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (has_erratum_a007798()) puts("Work-around for Erratum A007798 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004477 + if (has_erratum_a004477()) + puts("Work-around for Erratum A004477 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7860b40..fe9e9c1 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -161,6 +161,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 #define CONFIG_ESDHC_HC_BLK_ADDR @@ -292,6 +293,7 @@ #define CONFIG_FSL_SATA_ERRATUM_A001 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #elif defined(CONFIG_P1023) #define CONFIG_MAX_CPUS 2 @@ -372,6 +374,7 @@ #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ @@ -589,6 +592,7 @@ #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_ESDHC_HC_BLK_ADDR #elif defined(CONFIG_BSC9132) @@ -613,6 +617,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_A005434 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR @@ -712,6 +717,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006475 #define CONFIG_SYS_FSL_ERRATUM_A006384 #define CONFIG_SYS_FSL_ERRATUM_A007212 +#define CONFIG_SYS_FSL_ERRATUM_A004477 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 5d4288d..41ff1a7 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -138,6 +138,16 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (has_erratum_a007798()) set_txfifothresh(ehci, TXFIFOTHRESH); + if (has_erratum_a004477()) { + /* + * When reset is issued while any ULPI transaction is ongoing + * then it may result to corruption of ULPI Function Control + * Register which eventually causes phy clock to enter low + * power mode which stops the clock. Thus delay is required + * before reset to let ongoing ULPI transaction complete. + */ + udelay(1); + } return 0; } diff --git a/include/fsl_usb.h b/include/fsl_usb.h index d251f5d..88d8a8b 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -164,6 +164,30 @@ static inline bool has_erratum_a007792(void) return false; } +static inline bool has_erratum_a004477(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P1022: + case SVR_9131: + case SVR_9132: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + case SVR_P2020: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0) || + IS_SVR_REV(svr, 2, 1); + case SVR_B4860: + case SVR_B4420: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P4080: + return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); + } + + return false; +} #else static inline bool has_erratum_a006261(void) { @@ -184,5 +208,10 @@ static inline bool has_erratum_a007792(void) { return false; } + +static inline bool has_erratum_a004477(void) +{ + return false; +} #endif #endif /*_ASM_FSL_USB_H_ */ -- 1.7.11.7

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[U-Boot] [UBOOT PATCH] ci_udc: Update the ci_udc driver to support bulk transfers
by Siva Durga Prasad Paladugu 29 Apr '15

29 Apr '15

Update the ci_udc driver to support bulk transfer and also added capability of having multiple dtds if requested data is more thank 16K. These changes are tested for both the DFU and lthor. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- drivers/usb/gadget/ci_udc.c | 135 +++++++++++++++++++++++++++++++++++++------ drivers/usb/gadget/ci_udc.h | 1 + 2 files changed, 117 insertions(+), 19 deletions(-) diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 2572b34..d1d19dc 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -50,6 +50,8 @@ /* For each endpoint, we need 2 QTDs, one for each of IN and OUT */ #define ILIST_SZ (NUM_ENDPOINTS * 2 * ILIST_ENT_SZ) +#define EP_MAX_LENGTH_TRANSFER 0x4000 + #ifndef DEBUG #define DBG(x...) do {} while (0) #else @@ -102,13 +104,28 @@ static struct usb_ep_ops ci_ep_ops = { }; /* Init values for USB endpoints. */ -static const struct usb_ep ci_ep_init[2] = { +static const struct usb_ep ci_ep_init[5] = { [0] = { /* EP 0 */ .maxpacket = 64, .name = "ep0", .ops = &ci_ep_ops, }, - [1] = { /* EP 1..n */ + [1] = { + .maxpacket = 512, + .name = "ep1in-bulk", + .ops = &ci_ep_ops, + }, + [2] = { + .maxpacket = 512, + .name = "ep2out-bulk", + .ops = &ci_ep_ops, + }, + [3] = { + .maxpacket = 512, + .name = "ep3in-int", + .ops = &ci_ep_ops, + }, + [4] = { .maxpacket = 512, .name = "ep-", .ops = &ci_ep_ops, @@ -197,6 +214,19 @@ static void ci_flush_qtd(int ep_num) } /** + * ci_flush_td - flush cache over queue item + * @td: td pointer + * + * This function flushes cache for particular transfer descriptor. + */ +static void ci_flush_td(struct ept_queue_item *td) +{ + const uint32_t start = (uint32_t)td; + const uint32_t end = (uint32_t) td + ILIST_ENT_SZ; + flush_dcache_range(start, end); +} + +/** * ci_invalidate_qtd - invalidate cache over queue item * @ep_num: Endpoint number * @@ -211,6 +241,19 @@ static void ci_invalidate_qtd(int ep_num) invalidate_dcache_range(start, end); } +/** + * ci_invalidate_td - invalidate cache over queue item + * @td: td pointer + * + * This function invalidates cache for particular transfer descriptor. + */ +static void ci_invalidate_td(struct ept_queue_item *td) +{ + const uint32_t start = (uint32_t)td; + const uint32_t end = start + ILIST_ENT_SZ; + invalidate_dcache_range(start, end); +} + static struct usb_request * ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) { @@ -376,6 +419,9 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) struct ept_queue_head *head; int bit, num, len, in; struct ci_req *ci_req; + u8 *buf; + uint32_t length, actlen; + struct ept_queue_item *dtd, *qtd; ci_ep->req_primed = true; @@ -387,16 +433,41 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); len = ci_req->req.length; - item->info = INFO_BYTES(len) | INFO_ACTIVE; - item->page0 = (uint32_t)ci_req->hw_buf; - item->page1 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x1000; - item->page2 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x2000; - item->page3 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x3000; - item->page4 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x4000; - head->next = (unsigned) item; head->info = 0; + ci_req->dtd_count = 0; + buf = ci_req->hw_buf; + actlen = 0; + dtd = item; + + do { + length = min(ci_req->req.length - actlen, + (unsigned)EP_MAX_LENGTH_TRANSFER); + + dtd->info = INFO_BYTES(length) | INFO_ACTIVE; + dtd->page0 = (uint32_t)buf; + dtd->page1 = ((uint32_t)buf & 0xfffff000) + 0x1000; + dtd->page2 = ((uint32_t)buf & 0xfffff000) + 0x2000; + dtd->page3 = ((uint32_t)buf & 0xfffff000) + 0x3000; + dtd->page4 = ((uint32_t)buf & 0xfffff000) + 0x4000; + + len -= length; + actlen += length; + buf += length; + + if (len) { + qtd = (struct ept_queue_item *) + memalign(ILIST_ALIGN, ILIST_ENT_SZ); + dtd->next = (uint32_t)qtd; + dtd = qtd; + memset(dtd, 0, ILIST_ENT_SZ); + } + + ci_req->dtd_count++; + } while (len); + + item = dtd; /* * When sending the data for an IN transaction, the attached host * knows that all data for the IN is sent when one of the following @@ -432,6 +503,12 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep) ci_flush_qtd(num); + item = (struct ept_queue_item *)head->next; + while (item->next != TERMINATE) { + ci_flush_td((struct ept_queue_item *)item->next); + item = (struct ept_queue_item *)item->next; + } + DBG("ept%d %s queue len %x, req %p, buffer %p\n", num, in ? "in" : "out", len, ci_req, ci_req->hw_buf); ci_flush_qh(num); @@ -497,21 +574,31 @@ static void flip_ep0_direction(void) static void handle_ep_complete(struct ci_ep *ci_ep) { - struct ept_queue_item *item; - int num, in, len; + struct ept_queue_item *item, *next_td; + int num, in, len, j; struct ci_req *ci_req; num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; item = ci_get_qtd(num, in); ci_invalidate_qtd(num); + ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); - len = (item->info >> 16) & 0x7fff; - if (item->info & 0xff) - printf("EP%d/%s FAIL info=%x pg0=%x\n", - num, in ? "in" : "out", item->info, item->page0); + next_td = item; + len = 0; + for (j = 0; j < ci_req->dtd_count; j++) { + ci_invalidate_td(next_td); + item = next_td; + len += (item->info >> 16) & 0x7fff; + if (item->info & 0xff) + printf("EP%d/%s FAIL info=%x pg0=%x\n", + num, in ? "in" : "out", item->info, item->page0); + if (j != ci_req->dtd_count - 1) + next_td = (struct ept_queue_item *)item->next; + if (j != 0) + free(item); + } - ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue); list_del_init(&ci_req->queue); ci_ep->req_primed = false; @@ -847,9 +934,19 @@ static int ci_udc_probe(void) controller.gadget.ep0 = &controller.ep[0].ep; INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); - /* Init EP 1..n */ - for (i = 1; i < NUM_ENDPOINTS; i++) { - memcpy(&controller.ep[i].ep, &ci_ep_init[1], + /* Init EP 1..3 */ + for (i = 1; i < 4; i++) { + memcpy(&controller.ep[i].ep, &ci_ep_init[i], + sizeof(*ci_ep_init)); + INIT_LIST_HEAD(&controller.ep[i].queue); + controller.ep[i].req_primed = false; + list_add_tail(&controller.ep[i].ep.ep_list, + &controller.gadget.ep_list); + } + + /* Init EP 4..n */ + for (i = 4; i < NUM_ENDPOINTS; i++) { + memcpy(&controller.ep[i].ep, &ci_ep_init[4], sizeof(*ci_ep_init)); INIT_LIST_HEAD(&controller.ep[i].queue); controller.ep[i].req_primed = false; diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h index 346164a..95cc079 100644 --- a/drivers/usb/gadget/ci_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -86,6 +86,7 @@ struct ci_req { /* Buffer for the current transfer. Either req.buf/len or b_buf/len */ uint8_t *hw_buf; uint32_t hw_len; + uint32_t dtd_count; }; struct ci_ep { -- 1.7.4

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[U-Boot] [PATCH 0/29] dm: Introduce device tree support in SPL (for Rockchip)
by Simon Glass 28 Apr '15

28 Apr '15

With driver model SPL support in place the remaining driver difference between U-Boot proper and SPL is that SPL does not support device tree. This series adds this support, using a Rockchip board as an example. One problem with device tree is that U-Boot has no way of dropping features it does not need or use. For SPL this problem needs to be solved and this series uses the preprocessor for this. The 45KB Firefly device tree reduces to 693 bytes when unused material is removed. A better solution might involve the 'fdtgrep' tool but this has not made it into the device tree compiler as yet. This series includes some changes aimed at reduce code size in SPL, including: - dropping alias sequence support (the aliases node) since many boards just use a single UART in SPL - adding a smaller panic() function that does not support printf()-format strings - removing device unbind code which will never be used in SPL Overall the resulting SPL binary is 8829 bytes with my Linaro 4.8.2 compiler, including the device tree, using Thumb-2. Of this: 1768 bytes is driver model core code 1556 bytes is device tree code 693 bytes is the device tree itself 4756 is other code, including serial drivers, rodata and data The last figure includes rodata incorrectly added by the tool chain [1]. With a bug-fixed gcc 4.9.2 the total size is 6893 bytes including device tree. Approximately 750 bytes is used for strings and driver data (root device and serial) associated with driver model and device tree. This adds up an overhead of around 4750 bytes for driver model and device tree, including the code, rodata and device tree itself. It should therefore be possible to use driver model and device tree in SPL for board that have enough SRAM. Clearly 4KB is impossible without further work (perhaps removing some error strings). I suspect 8KB would be tricky, allowing only 3KB for stack and other code. But 16KB should work OK. SRAM sizes for recent SoCs I am aware of are: Rockchip RK3288: 96KB Tegra 124: 128KB Samsung Exynos 5420: 384KB The Rockchip Firefly was chosen for this work since it is a fairly recent board and is readily available. Rockchip engineers have been actively upstreaming code to Linux in the past year and there is a very full-featured U-Boot available. But it is invisible to most U-Boot people - mainline Rockchip support seems well overdue. This series does not make a serious start on that, since it only prints a message in SPL and then hangs, but additional work should get it booting to a prompt. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54303 Simon Glass (29): serial: ns16550: Add an option to specify the debug UART register shift dm: ns16550: Support non-byte register spacing with driver model dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver model serial: ns16550: Remove unnecessary init on UART setup fdt: arm: Drop device tree padding dm: core: Allow sequence alias support to be removed for SPL dm: core: Remove unbind operations when not required dm: Add a panic_str() function to reduce code size dm: core: Drop device removal error path when not supported fdt: sandbox: Move setup code from board_f to fdtdec fdt: Rename setup_fdt() and make it prepare also Move initf_malloc() to a common place Correct malloc_limit value for pre-relocation malloc() fdt: Add an option to disable device tree in SPL dts: Disable device tree for SPL on all boards fdt: Allow FDT functions to be built for SPL dm: core: Select device tree control correctly for SPL dm: Init device tree as well as driver model in SPL dm: serial: Don't support CONFIG_CONS_INDEX with device tree Remove SPL undefine of CONFIG_OF_CONTROL fdt: arm: Build device tree in SPL dm: rockchip: Add serial support rockchip: Bring in RK3288 device tree file includes and bindings rockchip: dts: Adjust device tree files for U-Boot SPL rockchip: Add base SoC files rockchip: Add basic support for firefly-rk3288 mkimage: Display a better list of available image types rockchip: Add the beginnings of an image tool rockchip: Add a simple README arch/arm/Kconfig | 11 + arch/arm/Makefile | 1 + arch/arm/cpu/armv7/exynos/Kconfig | 8 + arch/arm/cpu/armv7/s5pc1xx/Kconfig | 2 + arch/arm/cpu/u-boot-spl.lds | 2 +- arch/arm/dts/Makefile | 6 +- arch/arm/dts/rk3288-firefly.dts | 82 ++ arch/arm/dts/rk3288-firefly.dtsi | 496 +++++++ arch/arm/dts/rk3288-thermal.dtsi | 90 ++ arch/arm/dts/rk3288.dtsi | 1480 ++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/clock.h | 12 + arch/arm/include/asm/arch-rockchip/gpio.h | 5 + arch/arm/include/asm/arch-rockchip/grf.h | 181 +++ arch/arm/mach-rockchip/Kconfig | 44 + arch/arm/mach-rockchip/Makefile | 12 + arch/arm/mach-rockchip/board-spl.c | 54 + arch/arm/mach-rockchip/board.c | 17 + arch/arm/mach-rockchip/common.c | 11 + arch/arm/mach-rockchip/rk3288/Kconfig | 16 + arch/arm/mach-tegra/Kconfig | 3 + arch/sandbox/cpu/cpu.c | 41 + arch/sandbox/include/asm/u-boot-sandbox.h | 8 + board/firefly/firefly-rk3288/Kconfig | 15 + board/firefly/firefly-rk3288/MAINTAINERS | 6 + board/firefly/firefly-rk3288/Makefile | 7 + board/firefly/firefly-rk3288/firefly-rk3288.c | 7 + common/board_f.c | 84 +- common/dlmalloc.c | 11 + common/image.c | 55 +- common/spl/spl.c | 22 +- configs/Linksprite_pcDuino3_fdt_defconfig | 1 + configs/am335x_boneblack_vboot_defconfig | 1 + configs/arches_defconfig | 1 + configs/canyonlands_defconfig | 1 + configs/firefly-rk3288_defconfig | 11 + configs/galileo_defconfig | 1 + configs/microblaze-generic_defconfig | 1 + configs/odroid_defconfig | 1 + configs/origen_defconfig | 1 + configs/s5pc210_universal_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/trats2_defconfig | 1 + configs/trats_defconfig | 1 + configs/zynq_microzed_defconfig | 1 + configs/zynq_zc70x_defconfig | 1 + configs/zynq_zc770_xm010_defconfig | 1 + configs/zynq_zc770_xm012_defconfig | 1 + configs/zynq_zc770_xm013_defconfig | 1 + configs/zynq_zed_defconfig | 1 + configs/zynq_zybo_defconfig | 1 + doc/README.rockchip | 83 ++ .../clock/rockchip,rk3288-cru.txt | 61 + doc/device-tree-bindings/clock/rockchip.txt | 77 + .../pinctrl/rockchip,pinctrl.txt | 157 +++ .../thermal/rockchip-thermal.txt | 68 + drivers/core/Kconfig | 9 + drivers/core/Makefile | 2 + drivers/core/device.c | 54 +- drivers/core/root.c | 14 +- drivers/core/uclass.c | 4 + drivers/serial/Kconfig | 19 + drivers/serial/Makefile | 1 + drivers/serial/ns16550.c | 44 +- drivers/serial/serial-uclass.c | 69 +- drivers/serial/serial_rockchip.c | 41 + dts/Kconfig | 11 +- dts/Makefile | 9 +- include/config_uncmd_spl.h | 3 + include/configs/firefly-rk3288.h | 50 + include/dm/uclass-internal.h | 8 + include/dt-bindings/clock/rk3288-cru.h | 378 +++++ include/dt-bindings/clock/rockchip,rk808.h | 11 + include/dt-bindings/pinctrl/rockchip.h | 34 + include/dt-bindings/power-domain/rk3288.h | 11 + include/dt-bindings/thermal/thermal.h | 17 + include/fdtdec.h | 16 + include/image.h | 12 + include/malloc.h | 3 + include/vsprintf.h | 23 + lib/Makefile | 6 + lib/fdtdec.c | 39 +- lib/vsprintf.c | 23 +- scripts/Makefile.lib | 12 +- scripts/Makefile.spl | 35 + scripts/Makefile.uncmd_spl | 2 + tools/Makefile | 1 + tools/mkimage.c | 59 +- tools/rkimage.c | 63 + 88 files changed, 4136 insertions(+), 212 deletions(-) create mode 100644 arch/arm/dts/rk3288-firefly.dts create mode 100644 arch/arm/dts/rk3288-firefly.dtsi create mode 100644 arch/arm/dts/rk3288-thermal.dtsi create mode 100644 arch/arm/dts/rk3288.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/clock.h create mode 100644 arch/arm/include/asm/arch-rockchip/gpio.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf.h create mode 100644 arch/arm/mach-rockchip/Kconfig create mode 100644 arch/arm/mach-rockchip/Makefile create mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/board.c create mode 100644 arch/arm/mach-rockchip/common.c create mode 100644 arch/arm/mach-rockchip/rk3288/Kconfig create mode 100644 board/firefly/firefly-rk3288/Kconfig create mode 100644 board/firefly/firefly-rk3288/MAINTAINERS create mode 100644 board/firefly/firefly-rk3288/Makefile create mode 100644 board/firefly/firefly-rk3288/firefly-rk3288.c create mode 100644 configs/firefly-rk3288_defconfig create mode 100644 doc/README.rockchip create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt create mode 100644 doc/device-tree-bindings/clock/rockchip.txt create mode 100644 doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt create mode 100644 doc/device-tree-bindings/thermal/rockchip-thermal.txt create mode 100644 drivers/serial/serial_rockchip.c create mode 100644 include/configs/firefly-rk3288.h create mode 100644 include/dt-bindings/clock/rk3288-cru.h create mode 100644 include/dt-bindings/clock/rockchip,rk808.h create mode 100644 include/dt-bindings/pinctrl/rockchip.h create mode 100644 include/dt-bindings/power-domain/rk3288.h create mode 100644 include/dt-bindings/thermal/thermal.h create mode 100644 tools/rkimage.c -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] fatload from eMMC general purpose partition
by Andreas Naumann 24 Apr '15

24 Apr '15

Hi, using an eMMC I want to load uImage and dtb from a general purpose partition (since these can be configured as pSLC independent of the user data area). From the kernel I can format and access the GP-partition, in my case mkfs.vfat. However, U-Boots fatload/extload on the GP-partition do not work or maybe I just give the wrong parameters. Is this implemented at all, any hints? Regards Andreas

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[U-Boot] [PATCH 00/19] [RFC] Power(full) framework based on Driver Model
by Przemyslaw Marczak 24 Apr '15

24 Apr '15

Hello, This piece of code was a base for prepare my presentation talk for the U-Boot Mini Summit, which taking place at ELCE2014 conference, 13-th October 2014 Dusseldorf, Germany. The tittle of talk: "Power(full) framework based on Driver Model" The presentation will be shared after the Summit. This patchset introduces the new one PMIC framework for the U-Boot. It is still under the construction, but the basic functionality was achieved and tested. Please feel free to comment and share the opinion. I think that each patch is described full enough, but for some more design details, please look into the documentation file. It includes some basic examples for the PMIC drivers. Quick summary of: Framework: - The new approach - UCLASS_PMIC - simple and designed for device I/O only - Add new uclass types: UCLASS_PMIC and UCLASS_PMIC_REGULATOR - Two uclass drivers for above types - A common regulator operations - will easy cover the real devices design Drivers: - Introduce new PMIC API for drivers - now everything base on "struct udevice" - Introduce Regulator Voltage descriptors and Operation Mode descriptors which are usually taken from the device tree (board dependent data) - Two uclass device drivers for MAX77686(PMIC+REGULATOR) User Interface: - command pmic, unchanged functionality and ported to the driver model - command regulator(NEW) for safe regulator setup from commandline, - now can check output Voltage and operation mode of the regulators, - also can check the board Voltage limits and driver available modes The future plans: - Wait for the I2c Driver Model implementation - Introduce a common way to bind pmic devices - now done by alias "pmic" - Add additional uclass types: MUIC, CHARGER, BATTERY, MFD and maybe more. - Introduce optimal operations for new uclasses - Port all U-Boot drivers to the new Framework - Remove the old drivers and the old PMIC Framework code The assumptions of this work is: - Add new code to independent files - Keep two Frameworks as independent and without conflicts - Don't mix OLD/NEW Framework code - for the readability - Port all drivers using new API - Remove the old Framework and the old drivers A disadvantage: - some parts of the present code is duplicated Need help: - After merge this, it is welcome to help with driver porting. - Everything should be tested The extra feature: The first commit introduces errno_str() function. It is a common function which I hope will be usefull for commands and not only. If any visible error says: -19 or some other magic number, then it means that this function should be used. U-Boot Mini Summit members: This code is maybe not as good as it could be, but the time was limited, and the conference is comming soon. I don't expects a code review of this now, but it would be nice if you take a look of this piece of code before our U-Boot Mini Summit. Of course it depends on you. Best Regards and see you in Dusseldorf! Przemyslaw Marczak Przemyslaw Marczak (19): lib: errno: introduce errno_str(): returns errno related message exynos: config-common: enable errno_str() function exynos: config-common: enable generic fs command dm: pmic: add implementation of driver model pmic uclass dm: pmic: add implementation of driver model regulator uclass dm: common: board_r: add call and weak of power_init_dm() dm: pmic: add max77686 pmic driver dm: regulator: add max77686 regulator driver dm: pmic: new commands: pmic and regulator dm: board:samsung: power_init_board: add requirement of CONFIG_DM_PMIC doc: driver-model: pmic and regulator uclass documentation samsung: board: lcd menu: check if any power framework is enabled samsung: misc: power_key_pressed: add support to dm pmic framework trats2: board: add support to dm pmic api trats2: dts: max77686: add pmic alias and names cleanup trats2: config: enable dm pmic, dm regulator api, dm max77686 odroid: board: add support to dm pmic api odroid: dts: add 'voltage-regulators' description to max77686 node odroid: config: enable dm pmic, dm regulator and max77686 driver Makefile | 1 + arch/arm/dts/exynos4412-odroid.dts | 250 +++++++++- arch/arm/dts/exynos4412-trats2.dts | 17 +- board/samsung/common/board.c | 5 +- board/samsung/common/misc.c | 21 +- board/samsung/odroid/odroid.c | 31 +- board/samsung/trats2/trats2.c | 208 ++------ common/board_r.c | 8 + doc/driver-model/dm-pmic-framework.txt | 450 ++++++++++++++++++ drivers/power/Makefile | 6 +- drivers/power/cmd_pmic.c | 845 +++++++++++++++++++++++++++++++++ drivers/power/pmic-uclass.c | 255 ++++++++++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/max77686.c | 89 ++++ drivers/power/pmic_i2c.c | 136 ++++++ drivers/power/pmic_spi.c | 137 ++++++ drivers/power/regulator-uclass.c | 250 ++++++++++ drivers/power/regulator/Makefile | 8 + drivers/power/regulator/max77686.c | 749 +++++++++++++++++++++++++++++ include/configs/exynos-common.h | 3 + include/configs/odroid.h | 8 +- include/configs/trats2.h | 14 +- include/dm/uclass-id.h | 4 + include/errno.h | 3 + include/power/max77686_pmic.h | 28 +- include/power/pmic.h | 82 ++++ include/power/regulator.h | 267 +++++++++++ lib/Makefile | 1 + lib/errno_str.c | 147 ++++++ 29 files changed, 3823 insertions(+), 201 deletions(-) create mode 100644 doc/driver-model/dm-pmic-framework.txt create mode 100644 drivers/power/cmd_pmic.c create mode 100644 drivers/power/pmic-uclass.c create mode 100644 drivers/power/pmic/max77686.c create mode 100644 drivers/power/pmic_i2c.c create mode 100644 drivers/power/pmic_spi.c create mode 100644 drivers/power/regulator-uclass.c create mode 100644 drivers/power/regulator/Makefile create mode 100644 drivers/power/regulator/max77686.c create mode 100644 include/power/regulator.h create mode 100644 lib/errno_str.c -- 1.9.1

6 217

[U-Boot] [PATCH 1/2] gunzip: add gzwrite routine for extracting compresed images to block device
by Eric Nelson 23 Apr '15

23 Apr '15

Initial filesystem images are generally highly compressible. Add a routine gzwrite that allows gzip-compressed images to be written to block devices. Signed-off-by: Eric Nelson <eric.nelson(a)boundarydevices.com> --- include/common.h | 39 +++++++++++ lib/gunzip.c | 194 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 232 insertions(+), 1 deletion(-) diff --git a/include/common.h b/include/common.h index 9129454..f96baea 100644 --- a/include/common.h +++ b/include/common.h @@ -713,6 +713,45 @@ int gunzip(void *, int, unsigned char *, unsigned long *); int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, int stoponerr, int offset); +/** + * gzwrite progress indicators: defined weak to allow board-specific + * overrides: + * + * gzwrite_progress_init called on startup + * gzwrite_progress called during decompress/write loop + * gzwrite_progress_finish called at end of loop to + * indicate success (retcode=0) or failure + */ +void gzwrite_progress_init(u64 expected_size); + +void gzwrite_progress(int iteration, + u64 bytes_written, + u64 total_bytes); + +void gzwrite_progress_finish(int retcode, + u64 totalwritten, + u64 totalsize, + u32 expected_crc, + u32 calculated_crc); + +/** + * decompress and write gzipped image from memory to block device + * + * @param src compressed image address + * @param len compressed image length in bytes + * @param dev block device descriptor + * @param szwritebuf bytes per write (pad to erase size) + * @param startoffs offset in bytes of first write + * @param szexpected expected uncompressed length + * may be zero to use gzip trailer + * for files under 4GiB + */ +int gzwrite(unsigned char *src, int len, + struct block_dev_desc *dev, + unsigned long szwritebuf, + u64 startoffs, + u64 szexpected); + /* lib/qsort.c */ void qsort(void *base, size_t nmemb, size_t size, int(*compar)(const void *, const void *)); diff --git a/lib/gunzip.c b/lib/gunzip.c index f469fcb..d28fda8 100644 --- a/lib/gunzip.c +++ b/lib/gunzip.c @@ -12,6 +12,8 @@ #include <malloc.h> #include <u-boot/zlib.h> +#define HEADER0 '\x1f' +#define HEADER1 '\x8b' #define ZALLOC_ALIGNMENT 16 #define HEAD_CRC 2 #define EXTRA_FIELD 4 @@ -66,6 +68,196 @@ int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp) return zunzip(dst, dstlen, src, lenp, 1, i); } +__weak +void gzwrite_progress_init(u64 expectedsize) +{ + putc('\n'); +} + +__weak +void gzwrite_progress(int iteration, + u64 bytes_written, + u64 total_bytes) +{ + if (0 == (iteration & 3)) + printf("%llu/%llu\r", bytes_written, total_bytes); +} + +__weak +void gzwrite_progress_finish(int returnval, + u64 bytes_written, + u64 total_bytes, + u32 expected_crc, + u32 calculated_crc) +{ + if (0 == returnval) { + printf("\n\t%llu bytes, crc 0x%08x\n", + total_bytes, calculated_crc); + } else { + printf("\n\tuncompressed %llu of %llu\n" + "\tcrcs == 0x%08x/0x%08x\n", + bytes_written, total_bytes, + expected_crc, calculated_crc); + } +} + +int gzwrite(unsigned char *src, int len, + struct block_dev_desc *dev, + unsigned long szwritebuf, + u64 startoffs, + u64 szexpected) +{ + int i, flags; + z_stream s; + int r = 0; + unsigned char *writebuf; + unsigned crc = 0; + u64 totalfilled = 0; + lbaint_t blksperbuf, outblock; + u32 expected_crc; + u32 payload_size; + int iteration = 0; + + if (!szwritebuf || + (szwritebuf % dev->blksz) || + (szwritebuf < dev->blksz)) { + printf("%s: size %lu not a multiple of %lu\n", + __func__, szwritebuf, dev->blksz); + return -1; + } + + if (startoffs % dev->blksz) { + printf("%s: start offset %llu not a multiple of %lu\n", + __func__, startoffs, dev->blksz); + return -1; + } + + blksperbuf = szwritebuf / dev->blksz; + outblock = startoffs / dev->blksz; + + /* skip header */ + i = 10; + flags = src[3]; + if (src[2] != DEFLATED || (flags & RESERVED) != 0) { + puts("Error: Bad gzipped data\n"); + return -1; + } + if ((flags & EXTRA_FIELD) != 0) + i = 12 + src[10] + (src[11] << 8); + if ((flags & ORIG_NAME) != 0) + while (src[i++] != 0) + ; + if ((flags & COMMENT) != 0) + while (src[i++] != 0) + ; + if ((flags & HEAD_CRC) != 0) + i += 2; + + if (i >= len-8) { + puts("Error: gunzip out of data in header"); + return -1; + } + + payload_size = len - i - 8; + + memcpy(&expected_crc, src + len - 8, sizeof(expected_crc)); + expected_crc = le32_to_cpu(expected_crc); + u32 szuncompressed; + memcpy(&szuncompressed, src + len - 4, sizeof(szuncompressed)); + if (szexpected == 0) { + szexpected = le32_to_cpu(szuncompressed); + } else if (szuncompressed != (u32)szexpected) { + printf("size of %llx doesn't match trailer low bits %x\n", + szexpected, szuncompressed); + return -1; + } + if (szexpected / dev->blksz > (dev->lba - outblock)) { + printf("%s: uncompressed size %llu exceeds device size\n", + __func__, szexpected); + return -1; + } + + gzwrite_progress_init(szexpected); + + s.zalloc = gzalloc; + s.zfree = gzfree; + + r = inflateInit2(&s, -MAX_WBITS); + if (r != Z_OK) { + printf("Error: inflateInit2() returned %d\n", r); + return -1; + } + + s.next_in = src + i; + s.avail_in = payload_size+8; + writebuf = (unsigned char *)malloc(szwritebuf); + + /* decompress until deflate stream ends or end of file */ + do { + if (s.avail_in == 0) { + printf("%s: weird termination with result %d\n", + __func__, r); + break; + } + + /* run inflate() on input until output buffer not full */ + do { + unsigned long blocks_written; + int numfilled; + lbaint_t writeblocks; + + s.avail_out = szwritebuf; + s.next_out = writebuf; + r = inflate(&s, Z_SYNC_FLUSH); + if ((r != Z_OK) && + (r != Z_STREAM_END)) { + printf("Error: inflate() returned %d\n", r); + goto out; + } + numfilled = szwritebuf - s.avail_out; + crc = crc32(crc, writebuf, numfilled); + totalfilled += numfilled; + if (numfilled < szwritebuf) { + writeblocks = (numfilled+dev->blksz-1) + / dev->blksz; + memset(writebuf+numfilled, 0, + dev->blksz-(numfilled%dev->blksz)); + } else { + writeblocks = blksperbuf; + } + + gzwrite_progress(iteration++, + totalfilled, + szexpected); + blocks_written = dev->block_write(dev->dev, + outblock, + writeblocks, + writebuf); + outblock += blocks_written; + if (ctrlc()) { + puts("abort\n"); + goto out; + } + WATCHDOG_RESET(); + } while (s.avail_out == 0); + /* done when inflate() says it's done */ + } while (r != Z_STREAM_END); + + if ((szexpected != totalfilled) || + (crc != expected_crc)) + r = -1; + else + r = 0; + +out: + gzwrite_progress_finish(r, totalfilled, szexpected, + expected_crc, crc); + free(writebuf); + inflateEnd(&s); + + return r; +} + /* * Uncompress blocks compressed with zlib without headers */ @@ -81,7 +273,7 @@ int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, r = inflateInit2(&s, -MAX_WBITS); if (r != Z_OK) { - printf ("Error: inflateInit2() returned %d\n", r); + printf("Error: inflateInit2() returned %d\n", r); return -1; } s.next_in = src + offset; -- 1.9.1

4 11

[U-Boot] [PATCH] Revert "spi: add config option to enable the WP pin function on st micron flashes"
by Jagannadha Sutradharudu Teki 23 Apr '15

23 Apr '15

This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d. Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com> Cc: Heiko Schocher <hs(a)denx.de> --- README | 11 ----------- drivers/mtd/spi/sf_internal.h | 4 ---- drivers/mtd/spi/sf_probe.c | 30 ------------------------------ 3 files changed, 45 deletions(-) diff --git a/README b/README index 4ca04d0..908646f 100644 --- a/README +++ b/README @@ -3090,17 +3090,6 @@ CBFS (Coreboot Filesystem) support memories can be connected with a given cs line. currently Xilinx Zynq qspi support these type of connections. - CONFIG_SYS_SPI_ST_ENABLE_WP_PIN - enable the W#/Vpp signal to disable writing to the status - register on ST MICRON flashes like the N25Q128. - The status register write enable/disable bit, combined with - the W#/VPP signal provides hardware data protection for the - device as follows: When the enable/disable bit is set to 1, - and the W#/VPP signal is driven LOW, the status register - nonvolatile bits become read-only and the WRITE STATUS REGISTER - operation will not execute. The only way to exit this - hardware-protected mode is to drive W#/VPP HIGH. - - SystemACE Support: CONFIG_SYSTEMACE diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 785f7a9..bd834dc 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -97,10 +97,6 @@ enum { #define STATUS_QEB_MXIC (1 << 6) #define STATUS_PEC (1 << 7) -#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN -#define STATUS_SRWD (1 << 7) /* SR write protect */ -#endif - /* Flash timeout values */ #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index ce9987f..3b0e652 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -287,34 +287,6 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) } #endif /* CONFIG_OF_CONTROL */ -#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN -/* enable the W#/Vpp signal to disable writing to the status register */ -static int spi_enable_wp_pin(struct spi_flash *flash) -{ - u8 status; - int ret; - - ret = spi_flash_cmd_read_status(flash, &status); - if (ret < 0) - return ret; - - ret = spi_flash_cmd_write_status(flash, STATUS_SRWD); - if (ret < 0) - return ret; - - ret = spi_flash_cmd_write_disable(flash); - if (ret < 0) - return ret; - - return 0; -} -#else -static int spi_enable_wp_pin(struct spi_flash *flash) -{ - return 0; -} -#endif - /** * spi_flash_probe_slave() - Probe for a SPI flash device on a bus * @@ -393,8 +365,6 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash) puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); } #endif - if (spi_enable_wp_pin(flash)) - puts("Enable WP pin failed\n"); /* Release spi bus */ spi_release_bus(spi); -- 1.9.1

3 8

[U-Boot] [PATCH 1/3] sf: ops: Add spi_flash_copy_mmap function
by Tom Rini 22 Apr '15

22 Apr '15

When doing a memory mapped copy we may have DMA available and thus need to have this copy abstracted so that the driver can do it, rather than a simple memcpy. Cc: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> Signed-off-by: Tom Rini <trini(a)ti.com> --- drivers/mtd/spi/sf_ops.c | 8 +++++++- include/spi.h | 3 +++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index ef91b92..2c7b890 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -14,6 +14,7 @@ #include <spi.h> #include <spi_flash.h> #include <watchdog.h> +#include <linux/compiler.h> #include "sf_internal.h" @@ -359,6 +360,11 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, return ret; } +void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len) +{ + memcpy(data, offset, len); +} + int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data) { @@ -375,7 +381,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, return ret; } spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP); - memcpy(data, flash->memory_map + offset, len); + spi_flash_copy_mmap(data, flash->memory_map + offset, len); spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END); spi_release_bus(flash->spi); return 0; diff --git a/include/spi.h b/include/spi.h index ffd6647..eecb9ad 100644 --- a/include/spi.h +++ b/include/spi.h @@ -220,6 +220,9 @@ int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen); int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags); +/* Copy memory mapped data */ +void spi_flash_copy_mmap(void *data, void *offset, size_t len); + /** * Determine if a SPI chipselect is valid. * This function is provided by the board if the low-level SPI driver -- 1.7.9.5

3 7

[U-Boot] [PATCH] cmd_sf: Fix problem with "sf update" and unaligned length
by Stefan Roese 22 Apr '15

22 Apr '15

On SoCFPGA, using "sf update" with an non-4byte aligned length leads to a hangup (and reboot via watchdog). This is because of the unaligned access in the cadence QSPI driver which is hard to prevent since the data is written into a 4-byte wide FIFO. This patch fixes this problem by changing the behavior of the last sector write (not sector aligned). The new code is even simpler and copies the source data into the temp buffer and now uses the temp buffer to write the complete sector. So only one SPI sector write is used now instead of 2 in the old version. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Gerlando Falauto <gerlando.falauto(a)keymile.com> Cc: Valentin Longchamp <valentin.longchamp(a)keymile.com> Cc: Holger Brunck <holger.brunck(a)keymile.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com> --- common/cmd_sf.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 5c788e9..dd82290 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -163,6 +163,8 @@ static int do_spi_flash_probe(int argc, char * const argv[]) static const char *spi_flash_update_block(struct spi_flash *flash, u32 offset, size_t len, const char *buf, char *cmp_buf, size_t *skipped) { + char *ptr = (char *)buf; + debug("offset=%#x, sector_size=%#x, len=%#zx\n", offset, flash->sector_size, len); /* Read the entire sector so to allow for rewriting */ @@ -178,16 +180,14 @@ static const char *spi_flash_update_block(struct spi_flash *flash, u32 offset, /* Erase the entire sector */ if (spi_flash_erase(flash, offset, flash->sector_size)) return "erase"; - /* Write the initial part of the block from the source */ - if (spi_flash_write(flash, offset, len, buf)) - return "write"; - /* If it's a partial sector, rewrite the existing part */ + /* If it's a partial sector, copy the data into the temp-buffer */ if (len != flash->sector_size) { - /* Rewrite the original data to the end of the sector */ - if (spi_flash_write(flash, offset + len, - flash->sector_size - len, &cmp_buf[len])) - return "write"; + memcpy(cmp_buf, buf, len); + ptr = cmp_buf; } + /* Write one complete sector */ + if (spi_flash_write(flash, offset, flash->sector_size, ptr)) + return "write"; return NULL; } -- 2.2.1

4 12

[U-Boot] [PATCH v3 0/9] sf: Update flash params for supported read commands and sector size
by Bin Meng 22 Apr '15

22 Apr '15

This series update SPI flash supported read commands per datasheet in the flash params table, and change flash sector size to 4KiB as long as flash supports sector erase (20h) command, to ensure 'sf erase offset +len' work on 4KiB boundary instead of 64KiB when given SECT_4K. Changes in v3: - Rebase with Jagan's patch series @ http://patchwork.ozlabs.org/patch/419154/ Bin Meng (9): sf: Update SST flash params sf: Update Atmel flash params sf: Update EON flash params sf: Update GigaDevice flash params sf: Update Macronix flash params sf: Update Spansion flash params sf: Update Micron flash params sf: Update Winbond flash params sf: Give proper spacing between flash table params drivers/mtd/spi/sf_internal.h | 5 ++ drivers/mtd/spi/sf_params.c | 185 ++++++++++++++++++++++-------------------- drivers/mtd/spi/sf_probe.c | 4 + 3 files changed, 104 insertions(+), 90 deletions(-) -- 1.8.2.1

4 47