December 2015 - U-Boot

[U-Boot] [PATCH 0/4] ARM: at91: add UTMI PLL handle functions
by Wenyou Yang 09 Dec '15

09 Dec '15

To reduce the duplicated code, add UTMI PLL enable/disable functions, replace the UTMI PLL handle code with these functions. Wenyou Yang (4): ARM: at91: clock: add UTMI PLL enable/disable function ARM: at91: armv7: clean up UTMI PLL handle code drivers: usb: atmel: clean up the UTMI PLL code board: atmel: siemens: clean up UTMI PLL code arch/arm/mach-at91/armv7/sama5d2_devices.c | 5 +-- arch/arm/mach-at91/armv7/sama5d3_devices.c | 5 +-- arch/arm/mach-at91/armv7/sama5d4_devices.c | 5 +-- arch/arm/mach-at91/clock.c | 48 ++++++++++++++++++++++++++++ arch/arm/mach-at91/include/mach/clk.h | 3 ++ board/siemens/corvus/board.c | 4 +-- drivers/usb/host/ehci-atmel.c | 39 +++------------------- drivers/usb/host/ohci-at91.c | 20 ++++-------- 8 files changed, 66 insertions(+), 63 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH v2 1/4] x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE
by Bin Meng 09 Dec '15

09 Dec '15

NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - Remove NORTHBRIDGE_INTEL_SANDYBRIDGE in Makefile too. arch/x86/cpu/Makefile | 1 - arch/x86/cpu/ivybridge/Kconfig | 33 +-------------------------------- 2 files changed, 1 insertion(+), 33 deletions(-) diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index e797925..2ff2377 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -22,7 +22,6 @@ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_EFI_APP) += efi/ obj-$(CONFIG_QEMU) += qemu/ -obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 0e249a4..d20c038 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -5,37 +5,11 @@ # # SPDX-License-Identifier: GPL-2.0 - -config NORTHBRIDGE_INTEL_SANDYBRIDGE - bool - select CACHE_MRC_BIN - select CPU_INTEL_MODEL_206AX - config NORTHBRIDGE_INTEL_IVYBRIDGE bool select CACHE_MRC_BIN select CPU_INTEL_MODEL_306AX -if NORTHBRIDGE_INTEL_SANDYBRIDGE - -config VGA_BIOS_ID - string - default "8086,0106" - -config CACHE_MRC_SIZE_KB - int - default 256 - -config DCACHE_RAM_BASE - hex - default 0xff7f0000 - -config DCACHE_RAM_SIZE - hex - default 0x10000 - -endif - if NORTHBRIDGE_INTEL_IVYBRIDGE config VGA_BIOS_ID @@ -58,10 +32,6 @@ config DCACHE_RAM_SIZE hex default 0x20000 -endif - -if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE - config HAVE_MRC bool "Add a System Agent binary" help @@ -83,8 +53,7 @@ config DCACHE_RAM_MRC_VAR_SIZE config MRC_FILE string "Intel System Agent path and filename" depends on HAVE_MRC - default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE - default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE + default "systemagent-ivybridge.bin" help The path and filename of the file to use as System Agent binary. -- 1.8.2.1

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[U-Boot] [PATCH v2 1/2] x86: Move i8254_init() to x86_cpu_init_f()
by Bin Meng 09 Dec '15

09 Dec '15

Right now i8254_init() is called from timer_init() in the tsc timer driver. But actually i8254 and tsc are completely different things. Since tsc timer has been converted to driver model, we should find a new place that is appropriate for U-Boot to call i8254_init(), which is now x86_cpu_init_f(). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Rebase on top of u-boot/master - Reorder the patches so that patch#2 in v1 comes first in v2 arch/x86/cpu/cpu.c | 5 +++++ drivers/timer/tsc_timer.c | 10 ---------- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 1707993..381d835 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -399,6 +399,11 @@ int x86_cpu_init_f(void) } } +#ifdef CONFIG_I8254_TIMER + /* Set up the i8254 timer if required */ + i8254_init(); +#endif + return 0; } diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 6aa2437..5c4ec00 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -325,16 +325,6 @@ void __udelay(unsigned long usec) #endif } -int timer_init(void) -{ -#ifdef CONFIG_I8254_TIMER - /* Set up the i8254 timer if required */ - i8254_init(); -#endif - - return 0; -} - static int tsc_timer_get_count(struct udevice *dev, u64 *count) { u64 now_tick = rdtsc(); -- 1.8.2.1

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[U-Boot] [PATCH] x86: Fix PCI UART compatible string for crownbay and galileo
by Bin Meng 09 Dec '15

09 Dec '15

With recent ns16550 driver changes, we only changed the legacy UART (at I/O port 0x3f8) compatible string, but forgot to change the PCI UART compatible string. Now fix it. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/dts/crownbay.dts | 8 ++++---- arch/x86/dts/galileo.dts | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 8ee59f6..0850c86 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -121,7 +121,7 @@ "pci8086,8811", "pciclass,070002", "pciclass,0700", - "x86-uart"; + "ns16550"; u-boot,dm-pre-reloc; reg = <0x00025100 0x0 0x0 0x0 0x0 0x01025110 0x0 0x0 0x0 0x0>; @@ -135,7 +135,7 @@ "pci8086,8812", "pciclass,070002", "pciclass,0700", - "x86-uart"; + "ns16550"; u-boot,dm-pre-reloc; reg = <0x00025200 0x0 0x0 0x0 0x0 0x01025210 0x0 0x0 0x0 0x0>; @@ -149,7 +149,7 @@ "pci8086,8813", "pciclass,070002", "pciclass,0700", - "x86-uart"; + "ns16550"; u-boot,dm-pre-reloc; reg = <0x00025300 0x0 0x0 0x0 0x0 0x01025310 0x0 0x0 0x0 0x0>; @@ -163,7 +163,7 @@ "pci8086,8814", "pciclass,070002", "pciclass,0700", - "x86-uart"; + "ns16550"; u-boot,dm-pre-reloc; reg = <0x00025400 0x0 0x0 0x0 0x0 0x01025410 0x0 0x0 0x0 0x0>; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 2342de7..55165e1 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -70,7 +70,7 @@ "pci8086,0936", "pciclass,070002", "pciclass,0700", - "x86-uart"; + "ns16550"; u-boot,dm-pre-reloc; reg = <0x0000a500 0x0 0x0 0x0 0x0 0x0200a510 0x0 0x0 0x0 0x0>; -- 1.8.2.1

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[U-Boot] [PATCH] ARM: zynq: Enable u-boot,dm-pre-reloc for sdhci
by Michal Simek 08 Dec '15

08 Dec '15

Enable u-boot,dm-pre-reloc for sdhci for zc706, zed and zybo. And create alises for it. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynq-zc706.dts | 2 ++ arch/arm/dts/zynq-zed.dts | 2 ++ arch/arm/dts/zynq-zybo.dts | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 5088cfee3e74..1ba3a1c6e8dc 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -18,6 +18,7 @@ i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; + mmc0 = &sdhci0; }; memory { @@ -291,6 +292,7 @@ }; &sdhci0 { + u-boot,dm-pre-reloc; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 51d67d93f2dd..5ec59e2b4c6f 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -17,6 +17,7 @@ ethernet0 = &gem0; serial0 = &uart1; spi0 = &qspi; + mmc0 = &sdhci0; }; memory { @@ -50,6 +51,7 @@ }; &sdhci0 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index dcfc00e0967b..199264ac8e7f 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -16,6 +16,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + mmc0 = &sdhci0; }; memory { @@ -45,6 +46,7 @@ }; &sdhci0 { + u-boot,dm-pre-reloc; status = "okay"; }; -- 1.9.1

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[U-Boot] [PATCH 1/2] Kconfig: i2c: Fix typo Suport -> Support
by Michal Simek 08 Dec '15

08 Dec '15

Fix typo in command description. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/i2c/muxes/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index bd3e078d629e..4051923115a5 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -1,5 +1,5 @@ config I2C_MUX - bool "Suport I2C multiplexers" + bool "Support I2C multiplexers" depends on DM_I2C help This enables I2C buses to be multiplexed, so that you can select -- 1.9.1

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[U-Boot] Please pull ARC changes
by Alexey Brodkin 08 Dec '15

08 Dec '15

Hi Tom, The following changes since commit 8356431bf8df6d47255d6a74ca9dce53d75265c7: Prepare v2016.01-rc2 (2015-12-07 14:23:45 -0500) are available in the git repository at: git://git.denx.de/u-boot-arc.git for you to fetch changes up to 8555dd88cd1a7b5dd1e76c111fe635a92223b98b: axs10x: add support of generic EHCI USB 2.0 controller (2015-12-08 17:29:56 +0300) ---------------------------------------------------------------- Alexey Brodkin (1): axs10x: add support of generic EHCI USB 2.0 controller arch/arc/dts/axs10x.dts | 6 ++++++ configs/axs101_defconfig | 6 ++++++ configs/axs103_defconfig | 6 ++++++ 3 files changed, 18 insertions(+) Regards, Alexey

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[U-Boot] [PATCH v2] axs10x: add support of generic ECHI USB 2.0 controller
by Alexey Brodkin 08 Dec '15

08 Dec '15

This commit adds support of USB 2.0 storage media on AXS10x boards. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> --- Changes compared to v1: * Explicitly enable CONFIG_USB_EHCI_GENERIC arch/arc/dts/axs10x.dts | 6 ++++++ configs/axs101_defconfig | 6 ++++++ configs/axs103_defconfig | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/arch/arc/dts/axs10x.dts b/arch/arc/dts/axs10x.dts index 8fe1837..80e6d6b 100644 --- a/arch/arc/dts/axs10x.dts +++ b/arch/arc/dts/axs10x.dts @@ -42,4 +42,10 @@ clock-names = "stmmaceth"; max-speed = <100>; }; + + ehci@0xe0040000 { + compatible = "generic-ehci"; + reg = < 0xe0040000 0x100 >; + interrupts = < 8 >; + }; }; diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 52d5e2f..a541d9d 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="axs10x" CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y @@ -19,4 +20,9 @@ CONFIG_CLK=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index a7f3c38..3c65c83 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="axs10x" CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y @@ -18,4 +19,9 @@ CONFIG_CLK=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y -- 2.5.0

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[U-Boot] [PATCH v5] arm: Add sata support on Layerscape ARMv8 board
by Yuantian.Tang＠freescale.com 08 Dec '15

08 Dec '15

From: Tang Yuantian <Yuantian.Tang(a)freescale.com> Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- v5: - re-organize the code v4: - rebase to lastest git tree - add another ARMv8 platform which is ls1043aqds v3: - rename ls2085a to ls2080a - rebase to the latest git tree - replace the magic number with micro variable v2: - rebase to the latest git tree arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 31 ++++++++++++++++ include/configs/ls1043aqds.h | 17 +++++++++ include/configs/ls2080aqds.h | 18 +++++++++ include/configs/ls2080ardb.h | 18 +++++++++ 6 files changed, 131 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 8896b70..574ffc4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -6,6 +6,8 @@ #include <common.h> #include <fsl_ifc.h> +#include <ahci.h> +#include <scsi.h> #include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> @@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void) erratum_a009203(); } +#ifdef CONFIG_SCSI_AHCI_PLAT +int sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci; + + ccsr_ahci = (void *)CONFIG_SYS_SATA2; + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ccsr_ahci = (void *)CONFIG_SYS_SATA1; + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA1); + scsi_scan(0); + + return 0; +} +#endif + #elif defined(CONFIG_LS1043A) +#ifdef CONFIG_SCSI_AHCI_PLAT +int sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; + + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)CONFIG_SYS_SATA); + scsi_scan(0); + + return 0; +} +#endif + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -141,6 +180,10 @@ void fsl_lsch2_early_init_f(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { +#ifdef CONFIG_SCSI_AHCI_PLAT + sata_init(); +#endif + return 0; } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index cd96604..91f3ce8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -69,6 +69,10 @@ #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) +/* SATA */ +#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) +#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) + /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 504c1f9..83186d6 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -51,6 +51,37 @@ struct cpu_type { #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +/* ahci port register default value */ +#define AHCI_PORT_PHY_1_CFG 0xa003fffe +#define AHCI_PORT_PHY_2_CFG 0x28184d1f +#define AHCI_PORT_PHY_3_CFG 0x0e081509 +#define AHCI_PORT_TRANS_CFG 0x08000025 + +/* AHCI (sata) register map */ +struct ccsr_ahci { + u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ + u32 pcfg; /* port config */ + u32 ppcfg; /* port phy1 config */ + u32 pp2c; /* port phy2 config */ + u32 pp3c; /* port phy3 config */ + u32 pp4c; /* port phy4 config */ + u32 pp5c; /* port phy5 config */ + u32 axicc; /* AXI cache control */ + u32 paxic; /* port AXI config */ + u32 axipc; /* AXI PROT control */ + u32 ptc; /* port Trans Config */ + u32 pts; /* port Trans Status */ + u32 plc; /* port link config */ + u32 plc1; /* port link config1 */ + u32 plc2; /* port link config2 */ + u32 pls; /* port link status */ + u32 pls1; /* port link status1 */ + u32 pcmdc; /* port CMD config */ + u32 ppcs; /* port phy control status */ + u32 pberr; /* port 0/1 BIST error */ + u32 cmds; /* port 0/1 CMD status error */ +}; + #ifdef CONFIG_FSL_LSCH3 void fsl_lsch3_early_init_f(void); #elif defined(CONFIG_FSL_LSCH2) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 4aeb238..398f1c3 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -88,6 +88,23 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg #endif +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* * IFC Definitions */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index b8bdf62..100c0ee 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -40,6 +40,24 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 65d4f64..75d98dc 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -42,6 +42,24 @@ unsigned long get_board_sys_clk(void); #endif #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -- 2.1.0.27.g96db324

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[U-Boot] Would like to participate on the new U-Boot driver modele
by FALL OMAR 08 Dec '15

08 Dec '15

Hello Everyone, Hello Simon, Since your talk in Dublin, i am interested to participate on the development of U-Boot driver model. Therefore you have some tasks that you can assign to me, i would be great. Many thanks for everyone

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