December 2015 - U-Boot

[U-Boot] [PATCH] sunxi: Fix H3 DRAM DQ read delay configuration
by Jens Kuske 10 Dec '15

10 Dec '15

The read delays were set incorrectly, leading to reliability issues at higher DRAM clock speeds. This commit adjusts this to match the vendor boot0 behaviour. Signed-off-by: Jens Kuske <jenskuske(a)gmail.com> Tested-by: Siarhei Siamashka <siarhei.siamashka(a)gmail.com> --- arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c index b721d60..2020d75 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c @@ -73,10 +73,10 @@ static void mctl_dq_delay(u32 read, u32 write) for (i = 0; i < 4; i++) { val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) | - DATX_IOCR_READ_DELAY((read >> (i * 4)) & 0xf); + DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2); for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++) - setbits_le32(&mctl_ctl->datx[i].iocr[j], val); + writel(val, &mctl_ctl->datx[i].iocr[j]); } clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); @@ -85,8 +85,8 @@ static void mctl_dq_delay(u32 read, u32 write) val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) | DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf); - setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQS], val); - setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN], val); + writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]); + writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]); } setbits_le32(&mctl_ctl->pgcr[0], 1 << 26); @@ -436,8 +436,8 @@ unsigned long sunxi_dram_init(void) (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; struct dram_para para = { - .read_delays = 0x00007979, - .write_delays = 0x6aaa0000, + .read_delays = 0x00007979, /* dram_tpr12 */ + .write_delays = 0x6aaa0000, /* dram_tpr11 */ .dual_rank = 0, .bus_width = 32, .row_bits = 15, -- 2.6.3

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[U-Boot] [PATCH v2 0/4] ARM: at91: add UTMI PLL handle functions
by Wenyou Yang 10 Dec '15

10 Dec '15

To reduce the duplicated code, add UTMI PLL enable/disable functions, replace the UTMI PLL handle code with these functions. It is based on the following patch set. [PATCH v2 0/5] ARM: at91: improve peripheral and system clock handle functions Changes in v2: - remain asm/io.h include. Wenyou Yang (4): ARM: at91: clock: add UTMI PLL enable/disable function ARM: at91: armv7: clean up UTMI PLL handle code drivers: usb: atmel: clean up the UTMI PLL code board: atmel: siemens: clean up UTMI PLL code arch/arm/mach-at91/armv7/sama5d2_devices.c | 5 +-- arch/arm/mach-at91/armv7/sama5d3_devices.c | 5 +-- arch/arm/mach-at91/armv7/sama5d4_devices.c | 5 +-- arch/arm/mach-at91/clock.c | 48 ++++++++++++++++++++++++++++ arch/arm/mach-at91/include/mach/clk.h | 3 ++ board/siemens/corvus/board.c | 4 +-- drivers/usb/host/ehci-atmel.c | 38 +++------------------- drivers/usb/host/ohci-at91.c | 20 ++++-------- 8 files changed, 66 insertions(+), 62 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH v2 0/3] ARM: at91: add PMC_PLLICPR init function
by Wenyou Yang 10 Dec '15

10 Dec '15

To reduce the duplicated code, add PLLICPR init function, use the function to clean up the PMC_PLLICPR directly writing code. It is based on the following patch set. [PATCH 0/5] ARM: at91: improve peripheral and system clock handle functions [PATCH 0/4] ARM: at91: add UTMI PLL handle functions [PATCH 0/3] ARM: at91: add PLLB handle functions Changes in v2: - move at91_pllicpr_init() definition to the common file, clock.c. - fix checkpatch errors. Wenyou Yang (3): ARM: at91: clock: add PMC_PLLICPR init function ARM: at91: clean up the PMC_PLLICPR init code board: atmel: clean up the PMC_PLLICPR init code arch/arm/mach-at91/clock.c | 7 +++++++ arch/arm/mach-at91/include/mach/at91_pmc.h | 7 +++++++ arch/arm/mach-at91/include/mach/clk.h | 1 + arch/arm/mach-at91/spl_at91.c | 5 +---- board/atmel/sama5d3_xplained/sama5d3_xplained.c | 4 +--- board/atmel/sama5d3xek/sama5d3xek.c | 4 +--- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 4 +--- board/atmel/sama5d4ek/sama5d4ek.c | 4 +--- 8 files changed, 20 insertions(+), 16 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH] armv8: fsl-layerscape: fixes lsch2 serdes registers define
by shh.xie＠gmail.com 10 Dec '15

10 Dec '15

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 67 +++++++++++++++------- 1 file changed, 47 insertions(+), 20 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 83caa91..57cbef6 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -450,7 +450,8 @@ struct ccsr_serdes { u32 res_0c; /* 0x00c */ u32 pllcr3; u32 pllcr4; - u8 res_18[0x20-0x18]; + u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ + u8 res_1c[0x20-0x1c]; } bank[2]; u8 res_40[0x90-0x40]; u32 srdstcalcr; /* 0x90 TX Calibration Control */ @@ -458,25 +459,25 @@ struct ccsr_serdes { u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ u8 res_a4[0xb0-0xa4]; u32 srdsgr0; /* 0xb0 General Register 0 */ - u8 res_b4[0xe0-0xb4]; - u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ - u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ - u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ - u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ - u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ - u8 res_f4[0x100-0xf4]; + u8 res_b4[0x100-0xb4]; struct { - u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ + u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ u8 res_104[0x120-0x104]; - } srdslnpssr[4]; - u8 res_180[0x300-0x180]; - u32 srdspexeqcr; - u32 srdspexeqpcr[11]; - u8 res_330[0x400-0x330]; - u32 srdspexapcr; - u8 res_404[0x440-0x404]; - u32 srdspexbpcr; - u8 res_444[0x800-0x444]; + } lnpssr[4]; /* Lane A, B, C, D */ + u8 res_180[0x200-0x180]; + u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ + u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ + u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ + u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ + u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ + u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ + u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ + u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ + u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ + u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ + u32 srdspccra; /* 0x228 Protocol Configuration A */ + u32 srdspccrb; /* 0x22c Protocol Configuration B */ + u8 res_230[0x800-0x230]; struct { u32 gcr0; /* 0x800 General Control Register 0 */ u32 gcr1; /* 0x804 General Control Register 1 */ @@ -489,8 +490,34 @@ struct ccsr_serdes { u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ u8 res_824[0x83c-0x824]; u32 tcsr3; - } lane[4]; /* Lane A, B, C, D, E, F, G, H */ - u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ + } lane[4]; /* Lane A, B, C, D */ + u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ + struct { + u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ + u8 res_1004[0x1040-0x1004]; + } pcie[3]; + u8 res_10c0[0x1800-0x10c0]; + struct { + u8 res_1800[0x1804-0x1800]; + u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ + u8 res_1808[0x180c-0x1808]; + u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ + } sgmii[4]; /* Lane A, B, C, D */ + u8 res_1840[0x1880-0x1840]; + struct { + u8 res_1880[0x1884-0x1880]; + u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ + u8 res_1888[0x188c-0x1888]; + u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ + } qsgmii[2]; /* Lane A, B */ + u8 res_18a0[0x1980-0x18a0]; + struct { + u8 res_1980[0x1984-0x1980]; + u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ + u8 res_1988[0x198c-0x1988]; + u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ + } xfi[2]; /* Lane A, B */ + u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ }; #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2 0/5] ARM: at91: improve peripheral and system clock handle functions
by Wenyou Yang 10 Dec '15

10 Dec '15

To reduce the duplicated code, rework the peripheral's and system's clock handle functions, use these functions to replace the clock handle code. Changes in v2: - fix checkpatch warning. Wenyou Yang (5): ARM: at91: asm/at91_pmc.h: fix trival register offset ARM: at91: clock: add a new file to handle clock ARM: cpu: at91: clean up peripheral clock code board: atmel: clean up peripheral clock code drivers: at91: clean up peripheral clock code arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/arm920t/at91rm9200_devices.c | 13 +--- arch/arm/mach-at91/arm920t/timer.c | 4 +- arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c | 36 +++------- arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c | 28 ++------ arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c | 37 +++------- .../mach-at91/arm926ejs/at91sam9m10g45_devices.c | 33 +++------ arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c | 40 +++-------- arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c | 28 ++------ arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c | 38 +++-------- arch/arm/mach-at91/arm926ejs/clock.c | 7 -- arch/arm/mach-at91/arm926ejs/cpu.c | 1 - arch/arm/mach-at91/arm926ejs/timer.c | 5 +- arch/arm/mach-at91/armv7/clock.c | 26 ------- arch/arm/mach-at91/armv7/cpu.c | 1 - arch/arm/mach-at91/armv7/timer.c | 1 - arch/arm/mach-at91/clock.c | 72 ++++++++++++++++++++ arch/arm/mach-at91/include/mach/at91_pmc.h | 8 +-- arch/arm/mach-at91/include/mach/clk.h | 2 + arch/arm/mach-at91/phy.c | 1 - arch/arm/mach-at91/sdram.c | 1 - board/atmel/at91rm9200ek/at91rm9200ek.c | 1 - board/atmel/at91rm9200ek/led.c | 5 +- board/atmel/at91sam9260ek/at91sam9260ek.c | 15 ++-- board/atmel/at91sam9261ek/at91sam9261ek.c | 8 +-- board/atmel/at91sam9261ek/led.c | 6 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 23 ++----- board/atmel/at91sam9263ek/led.c | 9 +-- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 20 ++---- board/atmel/at91sam9m10g45ek/led.c | 7 +- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 6 +- board/atmel/at91sam9rlek/at91sam9rlek.c | 18 ++--- board/atmel/at91sam9rlek/led.c | 7 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 10 +-- board/atmel/sama5d2_xplained/sama5d2_xplained.c | 1 - board/atmel/sama5d3_xplained/sama5d3_xplained.c | 5 +- board/atmel/sama5d3xek/sama5d3xek.c | 5 +- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 5 +- board/atmel/sama5d4ek/sama5d4ek.c | 5 +- board/bluewater/snapper9260/snapper9260.c | 15 ++-- board/calao/usb_a9263/usb_a9263.c | 11 ++- board/egnite/ethernut5/ethernut5.c | 20 +++--- board/esd/meesc/meesc.c | 15 ++-- board/mini-box/picosam9g45/led.c | 7 +- board/mini-box/picosam9g45/picosam9g45.c | 17 ++--- board/ronetix/pm9261/led.c | 7 +- board/ronetix/pm9261/pm9261.c | 22 ++---- board/ronetix/pm9263/led.c | 7 +- board/ronetix/pm9263/pm9263.c | 19 ++---- board/ronetix/pm9g45/pm9g45.c | 20 ++---- board/siemens/corvus/board.c | 6 +- board/siemens/smartweb/smartweb.c | 3 +- board/siemens/taurus/taurus.c | 3 +- drivers/net/at91_emac.c | 9 ++- drivers/usb/host/ehci-atmel.c | 8 --- drivers/usb/host/ohci-at91.c | 20 ++---- 56 files changed, 252 insertions(+), 496 deletions(-) create mode 100644 arch/arm/mach-at91/clock.c -- 1.7.9.5

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[U-Boot] [PATCH] arm: Add and select CONFIG_ARMV7
by Marek Vasut 10 Dec '15

10 Dec '15

The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Simon Glass <sjg(a)chromium.org> --- arch/arm/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fb9176b..c0ab947 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -4,6 +4,9 @@ menu "ARM architecture" config SYS_ARCH default "arm" +config ARMV7 + bool + config ARM64 bool @@ -34,11 +37,13 @@ config CPU_ARM1176 config CPU_V7 bool + select ARMV7 select HAS_VBAR select HAS_THUMB2 config CPU_V7M bool + select ARMV7 select HAS_THUMB2 config CPU_PXA -- 2.1.4

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[U-Boot] [PATCH 00/19] device model bring-up of omap timer on dra72, dra74, am335x and am437x-sk evm
by Mugunthan V N 10 Dec '15

10 Dec '15

This patch series enables omap timer to adopt driver model. This has been tested on the following evms (logs [1]) by invoking 'sleep 10' command with minicom timestamps. * dra72 evm * dra74 evm * am335x evm * am335x bbb * am437x-sk evm * am437x-gp evm Also pushed a branch for testing [2] This patch series depends on [3] for chosen node in dra74 evm dts file. [1] - http://pastebin.ubuntu.com/13524650/ [2] - git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-timer [3] - https://www.mail-archive.com/u-boot@lists.denx.de/msg193763.html Mugunthan V N (19): arm: omap-common: do not build timer when CONFIG_TIMER defined dm: timer: uclass: add timer init to add timer device dm: timer: uclass: Add flag to control sequence numbering drivers: timer: omap_timer: add timer driver for omap devices based on dm am43xx_evm: timer: do not define CONFIG_TIMER for spl arm: dts: am437x-sk-evm: add tick-timer to chosen node defconfig: am437x_sk_evm: enable timer driver model arm: dts: am437x-gp-evm: add tick-timer to chosen node defconfig: am437x_gp_evm: enable timer driver model am335x_evm: timer: do not define CONFIG_TIMER for spl arm: dts: am335x-boneblack: add tick-timer to chosen node defconfig: am335x_boneblack_vboot: enable timer driver model arm: dts: am335x-evm: add tick-timer to chosen node defconfig: am335x_gp_evm: enable timer driver model ti_omap5_common: timer: do not define CONFIG_TIMER for spl arm: dts: dra72-evm: add tick-timer to chosen node defconfig: dra72_evm: enable timer driver model arm: dts: dra7-evm: add tick-timer to chosen node defconfig: dra74_evm: enable timer driver model arch/arm/cpu/armv7/omap-common/Makefile | 6 ++ arch/arm/dts/am335x-boneblack.dts | 1 + arch/arm/dts/am335x-evm.dts | 1 + arch/arm/dts/am437x-gp-evm.dts | 1 + arch/arm/dts/am437x-sk-evm.dts | 1 + arch/arm/dts/dra7-evm.dts | 1 + arch/arm/dts/dra72-evm.dts | 1 + configs/am335x_boneblack_vboot_defconfig | 2 + configs/am335x_gp_evm_defconfig | 2 + configs/am437x_gp_evm_defconfig | 2 + configs/am437x_sk_evm_defconfig | 2 + configs/dra72_evm_defconfig | 2 + configs/dra74_evm_defconfig | 2 + doc/device-tree-bindings/chosen.txt | 43 ++++++++++++ drivers/timer/Kconfig | 6 ++ drivers/timer/Makefile | 1 + drivers/timer/omap-timer.c | 108 +++++++++++++++++++++++++++++++ drivers/timer/timer-uclass.c | 35 ++++++++++ include/configs/am335x_evm.h | 1 + include/configs/am43xx_evm.h | 1 + include/configs/ti_omap5_common.h | 1 + lib/time.c | 5 ++ 22 files changed, 225 insertions(+) create mode 100644 doc/device-tree-bindings/chosen.txt create mode 100644 drivers/timer/omap-timer.c -- 2.6.3.368.gf34be46

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[U-Boot] [PATCH] ARM: mxs: allow boards to select DC-DC switching clock source
by Michael Heimpold 09 Dec '15

09 Dec '15

For some board designs, it might be useful to switch the DC-DC clock source to something else rather the default 24 MHz, e.g. for EMI reasons. For this, use something like this in your board configuration: Signed-off-by: Michael Heimpold <mhei(a)heimpold.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Otavio Salvador <otavio(a)ossystems.com.br> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> --- I'm not sure whether the position to set these bits is the best one. Regards, Michael arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 1972de8..410cf0b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -260,6 +260,15 @@ static void mxs_src_power_init(void) debug("SPL: Pre-Configuring power block\n"); +#ifdef CONFIG_SYS_MXS_DCDC_FREQSEL + /* Select clocksource for DC-DC converter */ + clrsetbits_le32(&power_regs->hw_power_misc, + POWER_MISC_FREQSEL_MASK, + CONFIG_SYS_MXS_DCDC_FREQSEL); + setbits_le32(&power_regs->hw_power_misc, + POWER_MISC_SEL_PLLCLK); +#endif + /* Improve efficieny and reduce transient ripple */ writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST | POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set); -- 2.5.0

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[U-Boot] Please pull u-boot-x86, take 2
by Bin Meng 09 Dec '15

09 Dec '15

Hi Tom, This includes fixes to PCI UART on CrownBay and Galileo, minor changes to x86 timer and some clean up to ivybridge support. The following changes since commit 8555dd88cd1a7b5dd1e76c111fe635a92223b98b: axs10x: add support of generic EHCI USB 2.0 controller (2015-12-08 17:29:56 +0300) are available in the git repository at: git://git.denx.de/u-boot-x86.git master for you to fetch changes up to 789fa275b3750e60c60cb3d18eabc9467892c257: x86: Remove HAVE_ACPI_RESUME (2015-12-09 17:44:56 +0800) ---------------------------------------------------------------- Bin Meng (8): fdt: Change OF_BAD_ADDR to FDT_ADDR_T_NONE x86: Fix PCI UART compatible string for crownbay and galileo x86: Move i8254_init() to x86_cpu_init_f() common: Remove timer_init() call for x86 x86: ivybridge: Remove NORTHBRIDGE_INTEL_SANDYBRIDGE x86: Clean up ivybridge/chrome Kconfig options x86: Remove CPU_INTEL_SOCKET_RPGA989 x86: Remove HAVE_ACPI_RESUME arch/x86/cpu/Makefile | 1 - arch/x86/cpu/cpu.c | 5 +++++ arch/x86/cpu/ivybridge/Kconfig | 70 +--------------------------------------------------------------------- arch/x86/cpu/ivybridge/cpu.c | 9 --------- arch/x86/cpu/ivybridge/lpc.c | 9 --------- arch/x86/cpu/ivybridge/northbridge.c | 16 ---------------- arch/x86/dts/crownbay.dts | 8 ++++---- arch/x86/dts/galileo.dts | 2 +- board/google/chromebook_link/Kconfig | 3 --- board/google/chromebox_panther/Kconfig | 3 --- common/board_f.c | 2 +- common/fdt_support.c | 3 ++- drivers/pci/pci_rom.c | 8 -------- drivers/timer/tsc_timer.c | 10 ---------- include/configs/x86-chromebook.h | 1 - 15 files changed, 14 insertions(+), 136 deletions(-) Regards, Bin

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[U-Boot] [PATCH] arm: socfpga: Fix cache configuration
by Stefan Roese 09 Dec '15

09 Dec '15

By not defining CONFIG_SYS_ARM_CACHE_WRITEALLOC, the WRITEBACK cache policy is selected. This leads to much better performance on the SoCFPGA. A quick network test shows this: Without this patch: => tftp 100000 big-40mb Speed: 1000, full duplex Using dwmac.ff702000 device TFTP from server 192.168.1.54; our IP address is 192.168.1.252 Filename 'big-40mb'. Load address: 0x100000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ########################## 2.5 MiB/s With this patch: => tftp 100000 big-40mb Speed: 1000, full duplex Using dwmac.ff702000 device TFTP from server 192.168.1.54; our IP address is 192.168.1.252 Filename 'big-40mb'. Load address: 0x100000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ########################## 7.6 MiB/s A performance improvement of factor ~3. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> --- include/configs/socfpga_common.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 38ae763..a2811ba 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -73,7 +73,6 @@ /* * Cache */ -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS -- 2.5.2

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