December 2015 - U-Boot

[U-Boot] [PATCH 1/6] arm: socfpga: de0_nano: Zap VIRTUAL_TARGET
by Marek Vasut 09 Dec '15

09 Dec '15

There is no VT for this board, so remove this incorrect macro. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- include/configs/socfpga_de0_nano_soc.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index d27aa9b..6007895 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -37,11 +37,7 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" -#else #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" -#endif #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- 2.1.4

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[U-Boot] [PATCH] ARM: imx: fsl_esdhc: fix usage of low 4 bits of sysctl register
by Eric Nelson 09 Dec '15

09 Dec '15

The low four bits of the SYSCTL register are reserved on the USDHC controller on i.MX6 and i.MX7 processors, but are used for clocking operations on earlier models. Guard against their usage by hiding the bit mask macros on those processors. These bits are used to prevent glitches when changing clocks on i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7. >From the i.MX6DQ RM: To prevent possible glitch on the card clock, clear the FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS or DVS in System Control Register) or setting RSTA bit. Signed-off-by: Eric Nelson <eric(a)nelint.com> --- drivers/mmc/fsl_esdhc.c | 15 +++++++++++++-- include/fsl_esdhc.h | 2 ++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c5054d6..1ccc576 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -502,15 +502,22 @@ static void set_sysctl(struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); +#ifdef CONFIG_FSL_USDHC + esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA); +#else esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); +#endif esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk); udelay(10000); - clk = SYSCTL_PEREN | SYSCTL_CKEN; +#ifdef CONFIG_FSL_USDHC + esdhc_clrbits32(&regs->sysctl, SYSCTL_RSTA); +#else + esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); +#endif - esdhc_setbits32(&regs->sysctl, clk); } #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK @@ -585,7 +592,9 @@ static int esdhc_init(struct mmc *mmc) esdhc_write32(&regs->scr, 0x00000040); #endif +#ifndef CONFIG_FSL_USDHC esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); +#endif /* Set the initial clock speed */ mmc_set_clock(mmc, 400000); @@ -657,8 +666,10 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) /* First reset the eSDHC controller */ esdhc_reset(regs); +#ifndef CONFIG_FSL_USDHC esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); +#endif writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten); memset(&cfg->cfg, 0, sizeof(cfg->cfg)); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index aa1b4cf..a4b87ce 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -25,10 +25,12 @@ #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 #define SYSCTL_CLOCK_MASK 0x0000fff0 +#if !defined(CONFIG_MX6) #define SYSCTL_CKEN 0x00000008 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 +#endif #define SYSCTL_RSTA 0x01000000 #define SYSCTL_RSTC 0x02000000 #define SYSCTL_RSTD 0x04000000 -- 2.6.2

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[U-Boot] [PATCH 0/3] ARM: at91: add PMC_PLLICPR init function
by Wenyou Yang 09 Dec '15

09 Dec '15

To reduce the duplicated code, add PLLICPR init function, use the function to clean up the PMC_PLLICPR directly writing code. It is based on the following patch set. [PATCH 0/5] ARM: at91: improve peripheral and system clock handle functions [PATCH 0/4] ARM: at91: add UTMI PLL handle functions [PATCH 0/3] ARM: at91: add PLLB handle functions Wenyou Yang (3): ARM: at91: clock: add PMC_PLLICPR init function ARM: at91: clean up the PMC_PLLICPR init code board: atmel: clean up the PMC_PLLICPR init code arch/arm/mach-at91/armv7/clock.c | 7 +++++++ arch/arm/mach-at91/include/mach/at91_pmc.h | 7 +++++++ arch/arm/mach-at91/include/mach/clk.h | 1 + arch/arm/mach-at91/spl_at91.c | 5 +---- board/atmel/sama5d3_xplained/sama5d3_xplained.c | 4 +--- board/atmel/sama5d3xek/sama5d3xek.c | 4 +--- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 4 +--- board/atmel/sama5d4ek/sama5d4ek.c | 4 +--- 8 files changed, 20 insertions(+), 16 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH] fdt: Change OF_BAD_ADDR to FDT_ADDR_T_NONE
by Bin Meng 09 Dec '15

09 Dec '15

Currently OF_BAD_ADDR is always -1ULL. When using OF_BAD_ADDR as the return value of dev_get_addr(), it creates potential size mismatch as dev_get_addr() uses FDT_ADDR_T_NONE as the return value which can be either -1U or -1ULL depending on CONFIG_PHYS_64BIT. Now we change OF_BAD_ADDR to FDT_ADDR_T_NONE to avoid such case. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- common/fdt_support.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index a7ff2df..66464db 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -16,6 +16,7 @@ #include <libfdt.h> #include <fdt_support.h> #include <exports.h> +#include <fdtdec.h> /** * fdt_getprop_u32_default_node - Return a node's property or a default @@ -950,7 +951,7 @@ void fdt_del_node_and_alias(void *blob, const char *alias) /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 -#define OF_BAD_ADDR ((u64)-1) +#define OF_BAD_ADDR FDT_ADDR_T_NONE #define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ (ns) > 0) -- 1.8.2.1

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[U-Boot] [PATCH] usb: udc: Fix warnings on 64-bit builds
by Michal Simek 09 Dec '15

09 Dec '15

Cast u32 bit value to 64bit before recasting to 64bit pointer to avoid pointer from integer cast size mismatch warnings. Warning log: +../drivers/usb/gadget/udc/udc-core.c: In function ‘usb_gadget_unmap_request’: +../drivers/usb/gadget/udc/udc-core.c:68:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/usb/gadget/udc/udc-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c index 875e998a82e3..326757b547fa 100644 --- a/drivers/usb/gadget/udc/udc-core.c +++ b/drivers/usb/gadget/udc/udc-core.c @@ -65,7 +65,7 @@ void usb_gadget_unmap_request(struct usb_gadget *gadget, if (req->length == 0) return; - dma_unmap_single((void *)req->dma, req->length, + dma_unmap_single((void *)(uintptr_t)req->dma, req->length, is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE); } EXPORT_SYMBOL_GPL(usb_gadget_unmap_request); -- 2.5.0

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[U-Boot] Please pull u-boot-x86
by Bin Meng 09 Dec '15

09 Dec '15

Hi Tom, This includes fixes to PCI UART on CrownBay and Galileo, and minor changes to x86 timer. The following changes since commit 8555dd88cd1a7b5dd1e76c111fe635a92223b98b: axs10x: add support of generic EHCI USB 2.0 controller (2015-12-08 17:29:56 +0300) are available in the git repository at: git://git.denx.de/u-boot-x86.git master for you to fetch changes up to 5436aebdef200f9e1e48fe1988e1582c2f6e996d: common: Remove timer_init() call for x86 (2015-12-09 09:49:39 +0800) ---------------------------------------------------------------- Bin Meng (4): fdt: Change OF_BAD_ADDR to FDT_ADDR_T_NONE x86: Fix PCI UART compatible string for crownbay and galileo x86: Move i8254_init() to x86_cpu_init_f() common: Remove timer_init() call for x86 arch/x86/cpu/cpu.c | 5 +++++ arch/x86/dts/crownbay.dts | 8 ++++---- arch/x86/dts/galileo.dts | 2 +- common/board_f.c | 2 +- common/fdt_support.c | 3 ++- drivers/timer/tsc_timer.c | 10 ---------- 6 files changed, 13 insertions(+), 17 deletions(-) Regards, Bin

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[U-Boot] [PATCH] defconfig: taurus_defconfig: disable SPL
by Wenyou Yang 09 Dec '15

09 Dec '15

Build SPL with taurus_defconfig defconfig file. It build fails with following log message: ---8< ---- $ make mrproper $ make taurus_defconfig $ make SPL [...] LD spl/lib/built-in.o LDS spl/u-boot-spl.lds LD spl/u-boot-spl arm-none-linux-gnueabi-ld: SPL image too big make[1]: *** [spl/u-boot-spl] Error 1 make: *** [spl/u-boot-spl] Error 2 --->8---- This board code is not ready for SPL for now, so disable CONFIG_SPL. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- configs/taurus_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index d59912c..557b066 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_TAURUS=y -CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS" CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set -- 1.7.9.5

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[U-Boot] Secure Boot Mode on rk3288 Radxa Rock2
by Geoff Cleary 09 Dec '15

09 Dec '15

We have successfully built u-boot loader for rk3288 from the rock_bsp repository here: https://github.com/radxa/rock-bsp.git We were able to create keys and sign the loader image using the secureBootConsole tool we found here: https://bitbucket.org/T-Firefly/firefly-rk3288/src/45fb49ab0f41/RKTools/lin… After using the "upgrade_tool" to flash the loader image to the rk3288, the new u-boot announces itself. It reports this rather than 0 and 0... SecureBootEn = 1, SecureBootLock = 1 : : Secure Boot Mode: 0x0 ==================== QUESTION ======== What is the process necessary to set the Efuse to the appropriate hash based on the public key, so that the loader will run in Secure Boot Mode? We assume this is the necessary step to be able to read the larger Efuse (available in Secure Mode only)? -- * Geoff Cleary* * Principal Software Engineer*

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[U-Boot] [PATCH] spi: zynq_qspi: Add configuration to disable LQSPI feature
by Nathan Rossi 09 Dec '15

09 Dec '15

When the Zynq Boot ROM code loads the payload from QSPI it uses the LQSPI feature of the QSPI device, however it does not clean up its configuration before handing over to the payload which leaves the device confgured to by-pass the standard non-linear operating mode. This ensures the Linear QSPI mode is disabled before re-enabling the device. Signed-off-by: Nathan Rossi <nathan(a)nathanrossi.com> Cc: Jagan Teki <jteki(a)openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Cc: Simon Glass <sjg(a)chromium.org> --- drivers/spi/zynq_qspi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 5825c6d..b98663c 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -30,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ +#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */ /* zynq qspi Transmit Data Register */ #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */ @@ -68,6 +69,9 @@ struct zynq_qspi_regs { u32 txd1r; /* 0x80 */ u32 txd2r; /* 0x84 */ u32 txd3r; /* 0x88 */ + u32 reserved1[5]; + u32 lqspicfg; /* 0xA0 */ + u32 lqspists; /* 0xA4 */ }; /* zynq qspi platform data */ @@ -143,6 +147,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) ZYNQ_QSPI_CR_MSTREN_MASK; writel(confr, &regs->cr); + /* Disable the LQSPI feature */ + confr = readl(&regs->lqspicfg); + confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK; + writel(confr, &regs->lqspicfg); + /* Enable SPI */ writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr); } -- 2.6.2

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[U-Boot] [PATCH 0/5] ARM: at91: improve peripheral and system clock handle functions
by Wenyou Yang 09 Dec '15

09 Dec '15

To reduce the duplicated code, rework the peripheral's and system's clock handle functions, use these functions to replace the clock handle code. Wenyou Yang (5): ARM: at91: asm/at91_pmc.h: fix trival register offset ARM: at91: clock: add a new file to handle clock ARM: cpu: at91: clean up peripheral clock code board: atmel: clean up peripheral clock code drivers: at91: clean up peripheral clock code arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/arm920t/at91rm9200_devices.c | 13 +--- arch/arm/mach-at91/arm920t/timer.c | 4 +- arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c | 36 +++------- arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c | 28 ++------ arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c | 37 +++------- .../mach-at91/arm926ejs/at91sam9m10g45_devices.c | 33 +++------ arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c | 40 +++-------- arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c | 28 ++------ arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c | 38 +++-------- arch/arm/mach-at91/arm926ejs/clock.c | 7 -- arch/arm/mach-at91/arm926ejs/cpu.c | 1 - arch/arm/mach-at91/arm926ejs/timer.c | 5 +- arch/arm/mach-at91/armv7/clock.c | 26 ------- arch/arm/mach-at91/armv7/cpu.c | 1 - arch/arm/mach-at91/armv7/timer.c | 1 - arch/arm/mach-at91/clock.c | 72 ++++++++++++++++++++ arch/arm/mach-at91/include/mach/at91_pmc.h | 8 +-- arch/arm/mach-at91/include/mach/clk.h | 2 + arch/arm/mach-at91/phy.c | 1 - arch/arm/mach-at91/sdram.c | 1 - board/atmel/at91rm9200ek/at91rm9200ek.c | 1 - board/atmel/at91rm9200ek/led.c | 5 +- board/atmel/at91sam9260ek/at91sam9260ek.c | 15 ++-- board/atmel/at91sam9261ek/at91sam9261ek.c | 8 +-- board/atmel/at91sam9261ek/led.c | 6 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 23 ++----- board/atmel/at91sam9263ek/led.c | 9 +-- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 20 ++---- board/atmel/at91sam9m10g45ek/led.c | 7 +- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 6 +- board/atmel/at91sam9rlek/at91sam9rlek.c | 18 ++--- board/atmel/at91sam9rlek/led.c | 7 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 10 +-- board/atmel/sama5d2_xplained/sama5d2_xplained.c | 1 - board/atmel/sama5d3_xplained/sama5d3_xplained.c | 5 +- board/atmel/sama5d3xek/sama5d3xek.c | 5 +- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 5 +- board/atmel/sama5d4ek/sama5d4ek.c | 5 +- board/bluewater/snapper9260/snapper9260.c | 15 ++-- board/calao/usb_a9263/usb_a9263.c | 11 ++- board/egnite/ethernut5/ethernut5.c | 20 +++--- board/esd/meesc/meesc.c | 15 ++-- board/mini-box/picosam9g45/led.c | 7 +- board/mini-box/picosam9g45/picosam9g45.c | 17 ++--- board/ronetix/pm9261/led.c | 7 +- board/ronetix/pm9261/pm9261.c | 22 ++---- board/ronetix/pm9263/led.c | 7 +- board/ronetix/pm9263/pm9263.c | 19 ++---- board/ronetix/pm9g45/pm9g45.c | 20 ++---- board/siemens/corvus/board.c | 6 +- board/siemens/smartweb/smartweb.c | 3 +- board/siemens/taurus/taurus.c | 3 +- drivers/net/at91_emac.c | 9 ++- drivers/usb/host/ehci-atmel.c | 8 --- drivers/usb/host/ohci-at91.c | 20 ++---- 56 files changed, 252 insertions(+), 496 deletions(-) create mode 100644 arch/arm/mach-at91/clock.c -- 1.7.9.5

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