December 2015 - U-Boot

[U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
by shengjiangwu 18 Dec '15

18 Dec '15

Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock. Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 ++++++------ board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 442b1e0..06783dc 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = { 2, /* MIXED1IO12 */ 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ 0, /* MIXED1IO21 */ 0, /* MIXED2IO0 */ 0, /* MIXED2IO1 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 42905f4..eccc705 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -14,7 +14,7 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 @@ -32,7 +32,7 @@ #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -- 1.7.9.5

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[U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
by shengjiangwu 18 Dec '15

18 Dec '15

Updated pinmux group MIXED1IO[0-13] for RGMII1. Updated EMAC1 clock. Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++------------ board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++-- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 33cf1fd..442b1e0 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = { 0, /* GENERALIO29 */ 0, /* GENERALIO30 */ 0, /* GENERALIO31 */ - 0, /* MIXED1IO0 */ - 1, /* MIXED1IO1 */ - 1, /* MIXED1IO2 */ - 1, /* MIXED1IO3 */ - 1, /* MIXED1IO4 */ - 0, /* MIXED1IO5 */ - 0, /* MIXED1IO6 */ - 0, /* MIXED1IO7 */ - 1, /* MIXED1IO8 */ - 1, /* MIXED1IO9 */ - 1, /* MIXED1IO10 */ - 1, /* MIXED1IO11 */ - 0, /* MIXED1IO12 */ - 0, /* MIXED1IO13 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ 1, /* MIXED1IO15 */ 1, /* MIXED1IO16 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 3d621ed..42905f4 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -31,7 +31,7 @@ #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 @@ -65,7 +65,7 @@ #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 50000000 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 #define CONFIG_HPS_CLK_NAND_HZ 50000000 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -- 1.7.9.5

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[U-Boot] who is official MAINTAINER for MPC83xx?
by Robert P. J. Day 18 Dec '15

18 Dec '15

i CCed alleged MPC83xx maintainer kim.phillips(a)freescale.com yesterday on my patch, but that CC bounced with "unknown user" error, is there a newer maintainer for that platform? rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH] ARM: uniphier: allow to run zImage rather than uImage
by Masahiro Yamada 18 Dec '15

18 Dec '15

UniPhier SoC family adopt ARM Multi-platform in Linux since the first upstreaming. Because CONFIG_ARM_PATCH_PHYS_VIRT is defined, the kernel image is completely position-independent. There is no reason to decide the load address on compile time, but it is up to the boot loader. Now, zImage is handier than uImage, also it allows to skip the relocation of the kernel image. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- include/configs/uniphier.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index b1106de..463c687 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -188,13 +188,14 @@ "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ "bootm $fit_addr_r\0" #else -#define CONFIG_BOOTFILE "uImage" +#define CONFIG_CMD_BOOTZ +#define CONFIG_BOOTFILE "zImage" #define LINUXBOOT_ENV_SETTINGS \ "fdt_addr=0x00100000\0" \ "fdt_addr_r=0x84100000\0" \ "fdt_size=0x00008000\0" \ "kernel_addr=0x00200000\0" \ - "kernel_addr_r=0x84200000\0" \ + "kernel_addr_r=0x80208000\0" \ "kernel_size=0x00800000\0" \ "ramdisk_addr=0x00a00000\0" \ "ramdisk_addr_r=0x84a00000\0" \ @@ -203,15 +204,15 @@ "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \ "setexpr fdt_addr $nor_base + $fdt_addr &&" \ - "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ + "bootz $kernel_addr $ramdisk_addr $fdt_addr\0" \ "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ - "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ + "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ "tftpboot $fdt_addr_r $fdt_file &&" \ - "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" + "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ -- 1.9.1

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[U-Boot] [PATCH 00/57] dm: x86: Convert ivybridge code to use driver model
by Simon Glass 18 Dec '15

18 Dec '15

At present ivybridge is the only x86 implementation that includes a reasonably full board init. This means there is a lot more code than with a board that uses FSP (even then we don't have memory init or graphics init code). This code does not use proper drivers for the devices and so its use of driver model is limited. This series refactors the code to improve this. In particular it drops use of the old x86_pci_...() API in favour of dm_pci_...(). The latter requires that each PCI device has a driver. A few very minor driver model improvements are added to support this. Also a Northbridge uclass is added - this could instead be done with the syscon, so comments are well as to which is best. A small amount of additional work will be needed to remove use of the x86_pci_...() in arch/x86, but this series represents the bulk of it. Simon Glass (57): dm: Add an init() method to the LPC uclass dm: core: Display the error number when driver binding fails dm: usb: Add a compatible string for PCI EHCI controller dm: syscon: Allow finding devices by driver data dm: pci: Convert bios_emu to use the driver model PCI API x86: ivybridge: Set up the LPC device using driver model x86: ivybridge: Move lpc_early_init() to probe() x86: ivybridge: Move more init to the probe() function x86: ivybridge: Set up the PCH init dm: x86: Add a northbridge uclass x86: ivybridge: Add a driver for the bd82x6x northbridge x86: ivybridge: Move northbridge init into the probe() method x86: ivybridge: Move LPC and PCH init into northbridge probe() x86: ivybridge: Rename lpc_init() to lpc_init_extra() x86: ivybridge: Add an init() method for the bd82x6x LPC x86: ivybridge: Move graphics init much later x86: ivybridge: Move sandybridge init to the lpc init() method x86: ivybridge: Move GPIO init to the LPC init() method x86: ivybridge: Use common CPU init code x86: ivybridge: Move CPU init code into the driver x86: ivybridge: Set up the thermal target correctly x86: ivybridge: Drop the dead MTRR code x86: ivybridge: Move early init code into northbridge.c x86: Make x86_init_cpus() static x86: Don't show an error when the MRC cache is up to date x86: Bring up northbridge, pch and lpc after the CPUs x86: ivybridge: Move northbridge and PCH init into drivers x86: ivybridge: Use driver model PCI API in bd82x6x_pci_init() x86: ivybridge: Use driver model PCI API in bd82x6x.c x86: ivybridge: Move northbridge setup to the northbridge driver ahci: Add an AHCI uclass x86: ivybridge: Do the SATA init before relocation x86: ivybridge: Drop the unused bd82x6x_init_extra() x86: ivybridge: Use the SATA driver to do the init x86: ivybridge: Use driver model PCI API in sata.c x86: ivybridge: Move lpc_enable() into gma.c x86: ivybridge: Move LPC init into LPC init() method x86: ivybridge: Drop the special PCI driver x86: ivybridge: Convert lpc init code to DM PCI API x86: Enable DM_USB for link and panther x86: i2c: Add a stub driver for Intel I2C/SMbus x86: ivybridge: Use the I2C driver to perform SMbus init x86: ivybridge: Convert enable_usb_bar() to use DM PCI API x86: ivybridge: Convert dram_init() to use DM PCI API x86: ivybridge: Convert sdram_initialise() to use DM PCI API x86: chromebook_link: Enable the syscon uclass x86: ivybridge: Convert SDRAM init to use driver model x86: ivybridge: Convert report_platform to DM PCI API x86: ivybridge: Convert pch.c to use DM PCI API x86: ivybridge: Move code from pch.c to bd82x6x.c x86: ivybridge: Sort out the calls to bridge_silicon_revision() x86: ivybridge: Convert EHCI init to use the DM PCI API x86: ivybridge: Drop XHCI support x86: ivybridge: Drop the SMM-locking code x86: Set up a shared syscon numbering schema x86: ivybridge: Use syscon for the GMA device x86: fdt: Drop the unused compatible strings in fdtdec arch/x86/cpu/cpu.c | 18 +- arch/x86/cpu/ivybridge/Makefile | 3 - arch/x86/cpu/ivybridge/bd82x6x.c | 247 +++++++++++------ arch/x86/cpu/ivybridge/cpu.c | 159 ++++------- arch/x86/cpu/ivybridge/early_init.c | 147 ---------- arch/x86/cpu/ivybridge/early_me.c | 70 +++-- arch/x86/cpu/ivybridge/gma.c | 114 ++++++-- arch/x86/cpu/ivybridge/lpc.c | 315 ++++++++++++---------- arch/x86/cpu/ivybridge/model_206ax.c | 126 ++++----- arch/x86/cpu/ivybridge/northbridge.c | 189 +++++++++++-- arch/x86/cpu/ivybridge/pch.c | 123 --------- arch/x86/cpu/ivybridge/pci.c | 67 ----- arch/x86/cpu/ivybridge/report_platform.c | 11 +- arch/x86/cpu/ivybridge/sata.c | 127 ++++++--- arch/x86/cpu/ivybridge/sdram.c | 64 +++-- arch/x86/cpu/ivybridge/usb_ehci.c | 29 -- arch/x86/cpu/ivybridge/usb_xhci.c | 32 --- arch/x86/dts/chromebook_link.dts | 83 +++++- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 23 +- arch/x86/include/asm/arch-ivybridge/me.h | 45 +++- arch/x86/include/asm/arch-ivybridge/pch.h | 27 +- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 13 +- arch/x86/include/asm/cpu.h | 11 + arch/x86/include/asm/u-boot-x86.h | 2 - arch/x86/lib/Makefile | 1 + arch/x86/lib/lpc-uclass.c | 11 + arch/x86/lib/mrccache.c | 6 +- arch/x86/lib/northbridge-uclass.c | 17 ++ board/google/chromebook_link/link.c | 8 - configs/chromebook_link_defconfig | 9 + configs/chromebox_panther_defconfig | 2 + drivers/bios_emulator/atibios.c | 107 +++++++- drivers/bios_emulator/bios.c | 39 +++ drivers/block/Makefile | 2 +- drivers/block/ahci-uclass.c | 14 + drivers/core/lists.c | 3 +- drivers/core/syscon-uclass.c | 31 ++- drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/intel_i2c.c | 75 ++++++ drivers/pci/pci_rom.c | 9 + drivers/usb/host/ehci-pci.c | 5 + include/bios_emul.h | 19 +- include/dm/uclass-id.h | 2 + include/fdtdec.h | 5 - include/lpc.h | 32 +++ include/syscon.h | 14 + lib/fdtdec.c | 5 - test/dm/syscon.c | 17 ++ 49 files changed, 1444 insertions(+), 1042 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/early_init.c delete mode 100644 arch/x86/cpu/ivybridge/pch.c delete mode 100644 arch/x86/cpu/ivybridge/pci.c delete mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c delete mode 100644 arch/x86/cpu/ivybridge/usb_xhci.c create mode 100644 arch/x86/lib/northbridge-uclass.c create mode 100644 drivers/block/ahci-uclass.c create mode 100644 drivers/i2c/intel_i2c.c create mode 100644 include/lpc.h -- 2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH] ARM: UniPhier: add initrd_high and fdt_high environments
by Masahiro Yamada 18 Dec '15

18 Dec '15

With FIT boot, U-boot puts a device tree and an initramdisk at the tail of the memory. Some UniPhier boards have a large amount of memory. For those boards, a device tree and an initramdisk are located out of reach of the Linux kernel causing a kernel panic if CONFIG_VMSPLIT_3G is defined in the kernel side. Add initrd_high and fdt_high to prevent them from going too high. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- include/configs/uniphier.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index d4688c5..dea340f 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -236,6 +236,8 @@ "netdev=eth0\0" \ "image_offset=0x00080000\0" \ "image_size=0x00f00000\0" \ + "initrd_high=0xa0000000\0" \ + "fdt_high=0xa0000000\0" \ "verify=n\0" \ "nandupdate=nand erase 0 0x100000 &&" \ "tftpboot u-boot-spl.bin &&" \ -- 1.9.1

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[U-Boot] Please pull u-boot-fsl-qoriq master
by York Sun 18 Dec '15

18 Dec '15

Tom, The following changes since commit 52bc7c7e2b31d6ba8d394f3d22b551abfa365363: eeprom: fix eeprom write procedure (2015-12-16 10:31:31 -0500) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git master for you to fetch changes up to ea1332ceb4698b199387b517e640705f93263161: net: fm: disables unused FM1-DTSEC1 MAC node in DTS (2015-12-17 08:52:19 +0800) ---------------------------------------------------------------- Mingkai Hu (5): armv8/ls1043a: remove print info armv8/fsl_lsch2: fix DCSR_DCFG address armv8/ls1043a: Implement workaround for PEX erratum A009929 armv8/ls1043ardb/rcw: change core frequency to 1600MHz armv8/ls1043aqds/rcw: change core frequency to 1600MHz Shaohui Xie (1): net: fm: disables unused FM1-DTSEC1 MAC node in DTS Stuart Yoder (1): driver: net: fsl-mc: remove MC firmware version check arch/arm/cpu/armv8/fsl-layerscape/soc.c | 16 ++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 ++- board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg | 4 ++-- .../freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg | 4 ++-- board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg | 4 ++-- board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg | 4 ++-- drivers/net/fm/init.c | 4 ++++ drivers/net/fm/ls1043.c | 9 +-------- drivers/net/fsl-mc/mc.c | 13 ------------- 10 files changed, 32 insertions(+), 30 deletions(-) Thanks. York

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[U-Boot] Please pull u-boot-rockchip
by Simon Glass 18 Dec '15

18 Dec '15

Hi Tom, This fixes the mkimage problem for Rockchip as previously discussed. I've also brought in the tiny printf() additions and patches to move Rockchip to use it. This reduces firefly's image size below the maximum even with the broken gcc. Finally, I've brought in another rk3036 board since it has very limited scope. The following changes since commit 5076c64a08d2083af5a7761b12a30116ef0da967: Merge branch 'master' of git://git.denx.de/u-boot-spi (2015-12-11 15:07:44 -0500) are available in the git repository at: git://git.denx.de/u-boot-rockchip.git for you to fetch changes up to 47b4c228b5ae72598dc38ca2764c11ea1c6693cc: rockchip: Add basic support for kylin board (2015-12-13 20:51:50 -0700) ---------------------------------------------------------------- Jeffy Chen (3): Revert "rockchip: Add max spl size & spl header configs" rockchip: mkimage: use imagename to select spl hdr & spl size rockchip: doc: add imagename Sjoerd Simons (6): spl: use panic_str instead of panic lib/tiny-printf.c: Implement vprintf lib: Split panic functions out of vsprintf.c lib: split out strtoxxxx functions out of vsprintf.c mmc: mmc: Don't use sprintf when using tiny-printf rockchip: firefly: Use tiny-printf huang lin (2): rockchip: rk3036 sdram setting cs1_row when rank larger than 1 rockchip: Add basic support for kylin board arch/arm/mach-rockchip/Kconfig | 15 ------ arch/arm/mach-rockchip/rk3036/Kconfig | 10 ++-- arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 6 ++- arch/arm/mach-rockchip/rk3288/Kconfig | 6 --- board/kylin/kylin_rk3036/Kconfig | 15 ++++++ board/kylin/kylin_rk3036/MAINTAINERS | 0 board/kylin/kylin_rk3036/Makefile | 7 +++ board/kylin/kylin_rk3036/kylin_rk3036.c | 49 +++++++++++++++++ common/spl/spl.c | 2 +- configs/firefly-rk3288_defconfig | 1 + configs/kylin-rk3036_defconfig | 26 +++++++++ doc/README.rockchip | 8 +-- drivers/mmc/mmc.c | 4 +- include/configs/kylin_rk3036.h | 12 +++++ lib/Makefile | 6 +-- lib/panic.c | 45 ++++++++++++++++ lib/strto.c | 174 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/tiny-printf.c | 18 +++++-- lib/vsprintf.c | 193 ------------------------------------------------------------------ tools/Makefile | 8 +-- tools/rkcommon.c | 72 ++++++++++++++++++++++++- tools/rkcommon.h | 32 ++++++++++- tools/rkimage.c | 4 +- tools/rksd.c | 26 +++------ tools/rkspi.c | 23 +++----- 25 files changed, 483 insertions(+), 279 deletions(-) create mode 100644 board/kylin/kylin_rk3036/Kconfig create mode 100644 board/kylin/kylin_rk3036/MAINTAINERS create mode 100644 board/kylin/kylin_rk3036/Makefile create mode 100644 board/kylin/kylin_rk3036/kylin_rk3036.c create mode 100644 configs/kylin-rk3036_defconfig create mode 100644 include/configs/kylin_rk3036.h create mode 100644 lib/panic.c create mode 100644 lib/strto.c Regards, Simon

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[U-Boot] [PATCH v1 05/18] drivers: serial: add driver for Microchip PIC32 UART controller.
by Purna Chandra Mandal 17 Dec '15

17 Dec '15

From: Paul Thacker <paul.thacker(a)microchip.com> Signed-off-by: Paul Thacker <paul.thacker(a)microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal(a)microchip.com> --- drivers/serial/Kconfig | 13 +++ drivers/serial/Makefile | 1 + drivers/serial/serial_pic32.c | 220 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 234 insertions(+) create mode 100644 drivers/serial/serial_pic32.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1fc287e..9763ea1 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -107,6 +107,14 @@ config DEBUG_UART_APBUART will need to provide parameters to make this work. The driver will be available until the real driver model serial is running. +config DEBUG_UART_PIC32 + bool "Microchip PIC32" + help + Select this to enable a debug UART using the serial_pic32 driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver model serial is running. + + endchoice config DEBUG_UART_BASE @@ -223,4 +231,9 @@ config UNIPHIER_SERIAL If you have a UniPhier based board and want to use the on-chip serial ports, say Y to this option. If unsure, say N. +config PIC32_SERIAL + bool "Support for Microchip PIC32 on-chip UART" + help + Support for the UART found on Microchip PIC32 SoC's. + endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dd87147..57cd38b 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o +obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c new file mode 100644 index 0000000..01c62e7 --- /dev/null +++ b/drivers/serial/serial_pic32.c @@ -0,0 +1,220 @@ +/* + * (c) 2015 Paul Thacker <paul.thacker(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include <common.h> +#include <dm.h> +#include <clk.h> +#include <errno.h> +#include <config.h> +#include <serial.h> +#include <linux/bitops.h> +#include <common.h> +#include <asm/io.h> +#include <asm/arch-pic32/pic32.h> +#include <asm/arch-pic32/clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_ENABLE BIT(15) +#define UART_ENABLE_RX BIT(12) +#define UART_ENABLE_TX BIT(10) +#define UART_RX_DATA_AVAIL BIT(0) +#define UART_RX_OERR BIT(1) +#define UART_TX_FULL BIT(9) + +/* UART Control */ +#define U_BASE(x) (x) +#define U_MODE(x) U_BASE(x) +#define U_MODECLR(x) (U_MODE(x) + _CLR_OFFSET) +#define U_MODESET(x) (U_MODE(x) + _SET_OFFSET) +#define U_STA(x) (U_BASE(x) + 0x10) +#define U_STACLR(x) (U_STA(x) + _CLR_OFFSET) +#define U_STASET(x) (U_STA(x) + _SET_OFFSET) +#define U_TXREG(x) (U_BASE(x) + 0x20) +#define U_RXREG(x) (U_BASE(x) + 0x30) +#define U_BRG(x) (U_BASE(x) + 0x40) + +struct pic32_uart_priv { + void __iomem *regs; + ulong uartclk; +}; + +static void pic32_serial_setbrg(void __iomem *regs, ulong uart_clk, u32 baud) +{ + writel(0, U_BRG(regs)); + writel((uart_clk / baud / 16) - 1, U_BRG(regs)); + udelay(100); +} + +/* + * Initialize the serial port with the given baudrate. + * The settings are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +static int pic32_serial_init(void __iomem *regs, ulong clk, u32 baudrate) +{ + /* disable and clear mode */ + writel(0, U_MODE(regs)); + writel(0, U_STA(regs)); + + /* set baud rate generator */ + pic32_serial_setbrg(regs, clk, baudrate); + + /* enable the UART for TX and RX */ + writel(UART_ENABLE_TX | UART_ENABLE_RX, U_STASET(regs)); + + /* enable the UART */ + writel(UART_ENABLE, U_MODESET(regs)); + return 0; +} + +/* Output a single byte to the serial port */ +static void pic32_serial_putc(void __iomem *regs, const char c) +{ + /* if \n, then add a \r */ + if (c == '\n') + pic32_serial_putc(regs, '\r'); + + /* Wait for Tx FIFO not full */ + while (readl(U_STA(regs)) & UART_TX_FULL) + ; + + /* stuff the tx buffer with the character */ + writel(c, U_TXREG(regs)); +} + +/* Test whether a character is in the RX buffer */ +static int pic32_serial_tstc(void __iomem *regs) +{ + /* check if rcv buf overrun error has occurred */ + if (readl(U_STA(regs)) & UART_RX_OERR) { + readl(U_RXREG(regs)); + + /* clear OERR to keep receiving */ + writel(UART_RX_OERR, U_STACLR(regs)); + } + + if (readl(U_STA(regs)) & UART_RX_DATA_AVAIL) + return 1; /* yes, there is data in rcv buffer */ + else + return 0; /* no data in rcv buffer */ +} + +/* + * Read a single byte from the rx buffer. + * Blocking: waits until a character is received, then returns. + * Return the character read directly from the UART's receive register. + * + */ +static int pic32_serial_getc(void __iomem *regs) +{ + /* wait here until data is available */ + while (!pic32_serial_tstc(regs)) + ; + + /* read the character from the rcv buffer */ + return readl(U_RXREG(regs)); +} + +static int pic32_uart_pending(struct udevice *dev, bool input) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + return pic32_serial_tstc(priv->regs); +} + +static int pic32_uart_setbrg(struct udevice *dev, int baudrate) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + pic32_serial_init(priv->regs, priv->uartclk, baudrate); + return 0; +} + +static int pic32_uart_putc(struct udevice *dev, const char ch) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + pic32_serial_putc(priv->regs, ch); + return 0; +} + +static int pic32_uart_getc(struct udevice *dev) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + return pic32_serial_getc(priv->regs); +} + +static int pic32_uart_probe(struct udevice *dev) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + pic32_serial_init(priv->regs, priv->uartclk, CONFIG_BAUDRATE); + return 0; +} + +static int pic32_uart_ofdata_to_platdata(struct udevice *dev) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + struct udevice *clkdev; + int ret; + + priv->regs = map_physmem(dev_get_addr(dev), + 0x100, + MAP_NOCACHE); + + /* get clock rate */ + ret = uclass_get_device(UCLASS_CLK, 0, &clkdev); + if (ret) { + printf("clk class not found, %d\n", ret); + return ret; + } + priv->uartclk = clk_get_periph_rate(clkdev, PB2CLK); + + return 0; +} + +static const struct dm_serial_ops pic32_uart_ops = { + .putc = pic32_uart_putc, + .pending = pic32_uart_pending, + .getc = pic32_uart_getc, + .setbrg = pic32_uart_setbrg, +}; + +static const struct udevice_id pic32_uart_ids[] = { + { .compatible = "microchip,pic32mzda-uart" }, + {} +}; + +U_BOOT_DRIVER(pic32_serial) = { + .name = "pic32-uart", + .id = UCLASS_SERIAL, + .of_match = pic32_uart_ids, + .probe = pic32_uart_probe, + .ops = &pic32_uart_ops, + .flags = DM_FLAG_PRE_RELOC, + .ofdata_to_platdata = pic32_uart_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct pic32_uart_priv), +}; + +#ifdef CONFIG_DEBUG_UART_PIC32 +#include <debug_uart.h> + +static inline void _debug_uart_init(void) +{ + void __iomem *regs = (void __iomem *)CONFIG_DEBUG_UART_BASE; + + pic32_serial_init(regs, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); +} + +static inline void _debug_uart_putc(int ch) +{ + writel(ch, U_TXREG(CONFIG_DEBUG_UART_BASE)); +} + +DEBUG_UART_FUNCS + +#endif -- 1.8.3.1

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[U-Boot] [PATCH v1 18/18] board: pic32mzdask: Customize default environments for OS boot.
by Purna Chandra Mandal 17 Dec '15

17 Dec '15

Add custom environment variables and commands to help boot from micro-SD card and/or from network (TFTP protocol). Signed-off-by: Purna Chandra Mandal <purna.mandal(a)microchip.com> --- include/configs/pic32mzdask.h | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 94e73e3..c903113 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -169,5 +169,48 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after X seconds */ #undef CONFIG_BOOTARGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ + "uenvfile=uEnv.txt\0" \ + "uenvaddr="__stringify(CONFIG_SYS_ENV_ADDR)"\0" \ + "scriptfile=boot.scr\0" \ + "ubootfile=u-boot.bin\0" \ + "importbootenv= " \ + "env import -t -r ${uenvaddr} ${filesize};\0" \ + \ + "tftploadenv=tftp ${uenvaddr} ${uenvfile} \0" \ + "tftploadscr=tftp ${uenvaddr} ${scriptfile} \0" \ + "tftploadub=tftp ${loadaddr} ${ubootfile} \0" \ + \ + "mmcloadenv=fatload mmc 0 ${uenvaddr} ${uenvfile}\0" \ + "mmcloadscr=fatload mmc 0 ${uenvaddr} ${scriptfile}\0" \ + "mmcloadub=fatload mmc 0 ${loadaddr} ${ubootfile}\0" \ + \ + "flashub=protect off bank 1; " \ + "erase.b 0x9d004000 0x9d0f3fff; " \ + "cp.b ${loadaddr} 0x9d004000 ${filesize}; " \ + "cmp.b ${loadaddr} 0x9d004000 ${filesize}; " \ + "protect on bank 1; \0" \ + \ + "loadbootenv=run mmcloadenv || run tftploadenv\0" \ + "loadbootscr=run mmcloadscr || run tftploadscr\0" \ + "bootcmd_root= " \ + "if run loadbootenv; then " \ + "echo Loaded environment ${uenvfile}; " \ + "run importbootenv; " \ + "fi; " \ + "if test -n \"${bootcmd_uenv}\" ; then " \ + "echo Running bootcmd_uenv ...; " \ + "run bootcmd_uenv; " \ + "fi; " \ + "if run loadbootscr; then " \ + "echo Jumping to ${scriptfile}; " \ + "source ${uenvaddr}; " \ + "fi; " \ + "echo Custom environment or script not found. " \ + "Aborting auto booting...; \0" \ + "" + +#define CONFIG_BOOTCOMMAND "run bootcmd_root" #define CONFIG_MEMSIZE_IN_BYTES /* pass 'memsize=' in bytes */ #endif /* __PIC32MZDASK_CONFIG_H */ -- 1.8.3.1

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