December 2015 - U-Boot

[U-Boot] [PATCH v3 0/3] Moving Uartlite to DM
by Michal Simek 18 Dec '15

18 Dec '15

Hi, This patch series depends on microblaze cleanup series. All these patches will be available in git://git.denx.de/u-boot-microblaze.git also with patches which I am going to send now. Thanks, Michal Changes in v3: - Use BIT macros - Fix logic in pending() for output direction - Add static inline to _debug_uart_init Changes in v2: - Remove unneeded headers - Use get_dev_addr instead of fdtdec_get_addr - Use platdata instead of private data - Add opb compatible string to be in sync with Linux - Add binding documentation - Add needed header from the first patch - Remove WATCHDOG_RESET call - Extend commit description Michal Simek (3): serial: uartlite: Move driver to DM serial: uartlite: Add support for debug console serial: uartlite: Add uartlite to Kconfig arch/microblaze/Kconfig | 1 + board/xilinx/microblaze-generic/xparameters.h | 4 - configs/microblaze-generic_defconfig | 3 + .../serial/xilinx_uartlite.txt | 13 ++ doc/driver-model/serial-howto.txt | 1 - drivers/serial/Kconfig | 14 ++ drivers/serial/serial_xuartlite.c | 194 +++++++++------------ include/configs/microblaze-generic.h | 7 +- 8 files changed, 119 insertions(+), 118 deletions(-) create mode 100644 doc/device-tree-bindings/serial/xilinx_uartlite.txt -- 1.9.1

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[U-Boot] about to do some tidying up of the top-level README file
by Robert P. J. Day 18 Dec '15

18 Dec '15

for an embedded linux course i'm teaching soon, i'm going to hand out an exercise to read parts of the u-boot README file and i notice there are some historical anachronisms in there i can submit patches for -- things like references to boards.cfg, and referring to a single MAINTAINERS file, that sort of thing. i'm about to start reading and tweaking; if anyone wants to point out any other things which could be brought up to date, let me know and i can add them to the patch. no sense doing this with more than one patch. rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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Re: [U-Boot] [PATCH v2] arm: socfpga: Fix QSPI doesn't work on socdk board
by 圣江吴 18 Dec '15

18 Dec '15

On Dec 18, 2015, at 12:47 AM, Chin Liang See <clsee(a)altera.com> wrote: Hi Shangjiang On Fri, 2015-12-18 at 16:43 +0800, shengjiangwu wrote: Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock. Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- Changes for v2: - fixed wrong perpll for QSPI --- board/altera/cyclone5-socdk/qts/pll_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) I believe you forget to put back the pinmux change here. Thanks Chin Liang Understand, I need to generate the whole patch. diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 5b754ac..4abd2e0 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -32,7 +32,7 @@ #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511

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[U-Boot] [Patch V2] i2c: mxc: add a condition in case the parameter is NULL
by Gong Qianyu 18 Dec '15

18 Dec '15

This could avoid executing the code that only applies to i.MX platforms. The bus_i2c_init() is called before relocation and will assgin value to a static variable. If U-Boot is then still running in a flash device, it's theoretically not allowed to write data to flash without an erasing operation. For i.MX platforms, the U-Boot is always running in DDR. Actually it causes asynchronous error when the ARM64 system error report is enabled and the flash write protect is set. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)freescale.com> --- V2: - Modified the commit title and message. - Used a condition to avoid executing the code. board/freescale/ls1043ardb/ls1043ardb.c | 1 + drivers/i2c/mxc_i2c.c | 12 ++++++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index cdd50d6..ba4ef1e 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -12,6 +12,7 @@ #include <asm/arch/soc.h> #include <hwconfig.h> #include <ahci.h> +#include <environment.h> #include <mmc.h> #include <scsi.h> #include <fm_eth.h> diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index fa4c82f..b2d15c9 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -581,8 +581,16 @@ void bus_i2c_init(int index, int speed, int unused, return; } - mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; - mxc_i2c_buses[index].idle_bus_data = idle_bus_data; + /* + * Warning: Be careful to allow the assignment to a static + * variable here. This function could be called while U-Boot is + * still running in flash memory. So such assignment is equal + * to write data to flash without erasing. + */ + if (idle_bus_fn) + mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; + if (idle_bus_data) + mxc_i2c_buses[index].idle_bus_data = idle_bus_data; ret = enable_i2c_clk(1, index); if (ret < 0) { -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2] arm: socfpga: Fix QSPI doesn't work on socdk board
by shengjiangwu 18 Dec '15

18 Dec '15

Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock. Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- Changes for v2: - fixed wrong perpll for QSPI --- board/altera/cyclone5-socdk/qts/pll_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 5b754ac..4abd2e0 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -32,7 +32,7 @@ #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -- 1.7.9.5

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[U-Boot] [PATCH v2] arm: socfpga: Fix emac1 doesn't work on socdk board
by shengjiangwu 18 Dec '15

18 Dec '15

Updated pinmux group MIXED1IO[0-13] for RGMII1. Updated EMAC1 clock. Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- Changes for v2: - fixed wrong perpll for emac1 --- board/altera/cyclone5-socdk/qts/pll_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index eccc705..5b754ac 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -65,7 +65,7 @@ #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 50000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 #define CONFIG_HPS_CLK_NAND_HZ 50000000 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -- 1.7.9.5

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[U-Boot] [PATCH] serial-howto: remove altera_jtag_uart and altera_uart from the list
by Thomas Chou 18 Dec '15

18 Dec '15

Since both altera_jtag_uart and altera_uart are converted to driver model, remove them from the list of drivers remaining to convert. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- doc/driver-model/serial-howto.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/doc/driver-model/serial-howto.txt b/doc/driver-model/serial-howto.txt index 76ad629..4706d56 100644 --- a/doc/driver-model/serial-howto.txt +++ b/doc/driver-model/serial-howto.txt @@ -4,8 +4,6 @@ How to port a serial driver to driver model About 16 of 33 serial drivers have been converted as at September 2015. It is time for maintainers to start converting over the remaining serial drivers: - altera_jtag_uart.c - altera_uart.c arm_dcc.c lpc32xx_hsuart.c mcfuart.c -- 2.5.0

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[U-Boot] [PATCH v2 0/3] Moving Uartlite to DM
by Michal Simek 18 Dec '15

18 Dec '15

Hi, This patch series depends on microblaze cleanup series. All these patches will be available in git://git.denx.de/u-boot-microblaze.git also with patches which I am going to send now. Thanks, Michal Changes in v2: - Remove unneeded headers - Use get_dev_addr instead of fdtdec_get_addr - Use platdata instead of private data - Add opb compatible string to be in sync with Linux - Add binding documentation - Add needed header from the first patch - Remove WATCHDOG_RESET call - Extend commit description Michal Simek (3): serial: uartlite: Move driver to DM serial: uartlite: Add support for debug console serial: uartlite: Add uartlite to Kconfig arch/microblaze/Kconfig | 1 + board/xilinx/microblaze-generic/xparameters.h | 4 - configs/microblaze-generic_defconfig | 3 + .../serial/xilinx_uartlite.txt | 13 ++ doc/driver-model/serial-howto.txt | 1 - drivers/serial/Kconfig | 14 ++ drivers/serial/serial_xuartlite.c | 188 +++++++++------------ include/configs/microblaze-generic.h | 7 +- 8 files changed, 116 insertions(+), 115 deletions(-) create mode 100644 doc/device-tree-bindings/serial/xilinx_uartlite.txt -- 1.9.1

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Re: [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
by 圣江吴 18 Dec '15

18 Dec '15

On Dec 17, 2015, at 11:28 PM, Chin Liang See <clsee(a)altera.com> wrote: Hi Shengjiang, On Fri, 2015-12-18 at 15:13 +0800, shengjiangwu wrote: Updated pinmux group MIXED1IO[0-13] for RGMII1. Updated EMAC1 clock. Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Thanks for the patch. --- board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++-- ---------- board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++-- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 33cf1fd..442b1e0 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = { 0, /* GENERALIO29 */ 0, /* GENERALIO30 */ 0, /* GENERALIO31 */ - 0, /* MIXED1IO0 */ - 1, /* MIXED1IO1 */ - 1, /* MIXED1IO2 */ - 1, /* MIXED1IO3 */ - 1, /* MIXED1IO4 */ - 0, /* MIXED1IO5 */ - 0, /* MIXED1IO6 */ - 0, /* MIXED1IO7 */ - 1, /* MIXED1IO8 */ - 1, /* MIXED1IO9 */ - 1, /* MIXED1IO10 */ - 1, /* MIXED1IO11 */ - 0, /* MIXED1IO12 */ - 0, /* MIXED1IO13 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ 1, /* MIXED1IO15 */ 1, /* MIXED1IO16 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 3d621ed..42905f4 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -31,7 +31,7 @@ #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 @@ -65,7 +65,7 @@ #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 50000000 I believe the EMAC1 clock is still 250MHz which result of 25MHz * (79+1) / (1+1) / (3+1). Thanks Chin Liang Thanks for your comments, then I will restore it CONFIG_HPS_CLK_EMAC1_HZ as 250000000 Shengjiangwu #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 #define CONFIG_HPS_CLK_NAND_HZ 50000000 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000

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Re: [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
by 圣江吴 18 Dec '15

18 Dec '15

Hi Chin, I will check it. Best Regards ShengjiangWu On Dec 17, 2015, at 11:28 PM, Chin Liang See <clsee(a)altera.com> wrote: Hi Shengjiang, On Fri, 2015-12-18 at 15:13 +0800, shengjiangwu wrote: Updated pinmux group MIXED1IO[0-13] for RGMII1. Updated EMAC1 clock. Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Thanks for the patch. --- board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 +++++++++++-- ---------- board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++-- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 33cf1fd..442b1e0 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = { 0, /* GENERALIO29 */ 0, /* GENERALIO30 */ 0, /* GENERALIO31 */ - 0, /* MIXED1IO0 */ - 1, /* MIXED1IO1 */ - 1, /* MIXED1IO2 */ - 1, /* MIXED1IO3 */ - 1, /* MIXED1IO4 */ - 0, /* MIXED1IO5 */ - 0, /* MIXED1IO6 */ - 0, /* MIXED1IO7 */ - 1, /* MIXED1IO8 */ - 1, /* MIXED1IO9 */ - 1, /* MIXED1IO10 */ - 1, /* MIXED1IO11 */ - 0, /* MIXED1IO12 */ - 0, /* MIXED1IO13 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ 1, /* MIXED1IO15 */ 1, /* MIXED1IO16 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 3d621ed..42905f4 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -31,7 +31,7 @@ #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 @@ -65,7 +65,7 @@ #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 50000000 I believe the EMAC1 clock is still 250MHz which result of 25MHz * (79+1) / (1+1) / (3+1). Thanks Chin Liang #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 #define CONFIG_HPS_CLK_NAND_HZ 50000000 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000

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