December 2015 - U-Boot

[U-Boot] [PATCH v1 00/18] Initial Microchip PIC32MZ[DA] Support
by Purna Chandra Mandal 17 Dec '15

17 Dec '15

This patch series adds support for Microchip PIC32MZ[DA] MIPS microcontroller platform. All drivers required to boot from MMC micro-SD card and network are included in it; pinctrl, clock, serial, SDHCI, gpio, ethernet. This series been tested on PIC32MZ[DA] Starter Kit. A tree with these changes are available at [0]. [0] https://github.com/purna-mandal/u-boot/tree/pic32-upstream-v1 Cristian Birsan (1): MIPS: pic32: Add driver for Microchip PIC32 internal flash controller. Paul Thacker (1): drivers: serial: add driver for Microchip PIC32 UART controller. Purna Chandra Mandal (14): MIPS: Prepare device-tree support. MIPS: initial infrastructure for Microchip PIC32 architecture. drivers: pinctrl: Add pinctrl driver for Microchip PIC32. drivers: clk: Add clock driver for Microchip PIC32 Microcontroller. MIPS: Add support for Microchip PIC32MZ[DA] SoC family. board: Add Microchip PIC32MZ[DA]-Starter-Kit board. board: pic32mzdask: add flash support for environments. MIPS: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO. drivers: gpio: add driver for Microchip PIC32 GPIO controller. drivers: net: phy: add SMSC LAN8740 Phy support. drivers: net: add Microchip PIC32 ethernet controller driver. board: Add gpio and ethernet support to pic32mzdask board. board: add SDHCI support for PIC32MZDASK board. board: pic32mzdask: Customize U-Boot environments for OS boot. Sandeep Sheriker Mallikarjun (1): drivers: mmc: PIC32MZ[DA] SDHCI errata fix when JTAG is not connected. Andrei Pistirica (1): drivers: mmc: add driver for Microchip PIC32 SDHCI controller. arch/Kconfig | 1 + arch/mips/Kconfig | 5 + arch/mips/Makefile | 1 + arch/mips/config.mk | 3 + arch/mips/dts/.gitignore | 1 + arch/mips/dts/Makefile | 16 + arch/mips/dts/include/dt-bindings | 1 + arch/mips/dts/pic32mzda.dtsi | 162 ++++++++ arch/mips/dts/pic32mzda_sk.dts | 50 +++ arch/mips/dts/skeleton.dtsi | 21 + arch/mips/include/asm/arch-pic32/clock.h | 31 ++ arch/mips/include/asm/arch-pic32/pic32.h | 148 +++++++ arch/mips/include/asm/gpio.h | 1 + arch/mips/mach-pic32/Kconfig | 41 ++ arch/mips/mach-pic32/Makefile | 10 + arch/mips/mach-pic32/config.mk | 8 + arch/mips/mach-pic32/cpu.c | 132 +++++++ arch/mips/mach-pic32/flash.c | 471 ++++++++++++++++++++++ arch/mips/mach-pic32/lowlevel_init.S | 41 ++ arch/mips/mach-pic32/reset.c | 22 ++ board/microchip/pic32mzda/Kconfig | 13 + board/microchip/pic32mzda/MAINTAINERS | 6 + board/microchip/pic32mzda/Makefile | 7 + board/microchip/pic32mzda/README | 22 ++ board/microchip/pic32mzda/config.mk | 4 + board/microchip/pic32mzda/ddr.c | 389 +++++++++++++++++++ board/microchip/pic32mzda/ddr.h | 46 +++ board/microchip/pic32mzda/pic32mzda.c | 41 ++ configs/pic32mzdask_defconfig | 33 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-pic32.c | 413 ++++++++++++++++++++ drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 2 +- drivers/gpio/pic32_gpio.c | 164 ++++++++ drivers/mmc/Kconfig | 6 + drivers/mmc/Makefile | 2 +- drivers/mmc/pic32_sdhci.c | 110 ++++++ drivers/mmc/sdhci.c | 12 + drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/phy/smsc.c | 10 + drivers/net/pic32_eth.c | 648 +++++++++++++++++++++++++++++++ drivers/net/pic32_eth.h | 184 +++++++++ drivers/net/pic32_mdio.c | 143 +++++++ drivers/pinctrl/Kconfig | 6 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl_pic32.c | 173 +++++++++ drivers/serial/Kconfig | 13 + drivers/serial/Makefile | 1 + drivers/serial/serial_pic32.c | 220 +++++++++++ dts/Makefile | 2 +- include/configs/pic32mzdask.h | 216 +++++++++++ include/flash.h | 5 +- 53 files changed, 4070 insertions(+), 4 deletions(-) create mode 100644 arch/mips/dts/.gitignore create mode 100644 arch/mips/dts/Makefile create mode 120000 arch/mips/dts/include/dt-bindings create mode 100644 arch/mips/dts/pic32mzda.dtsi create mode 100644 arch/mips/dts/pic32mzda_sk.dts create mode 100644 arch/mips/dts/skeleton.dtsi create mode 100644 arch/mips/include/asm/arch-pic32/clock.h create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h create mode 100644 arch/mips/include/asm/gpio.h create mode 100644 arch/mips/mach-pic32/Kconfig create mode 100644 arch/mips/mach-pic32/Makefile create mode 100644 arch/mips/mach-pic32/config.mk create mode 100644 arch/mips/mach-pic32/cpu.c create mode 100644 arch/mips/mach-pic32/flash.c create mode 100644 arch/mips/mach-pic32/lowlevel_init.S create mode 100644 arch/mips/mach-pic32/reset.c create mode 100644 board/microchip/pic32mzda/Kconfig create mode 100644 board/microchip/pic32mzda/MAINTAINERS create mode 100644 board/microchip/pic32mzda/Makefile create mode 100644 board/microchip/pic32mzda/README create mode 100644 board/microchip/pic32mzda/config.mk create mode 100644 board/microchip/pic32mzda/ddr.c create mode 100644 board/microchip/pic32mzda/ddr.h create mode 100644 board/microchip/pic32mzda/pic32mzda.c create mode 100644 configs/pic32mzdask_defconfig create mode 100644 drivers/clk/clk-pic32.c create mode 100644 drivers/gpio/pic32_gpio.c create mode 100644 drivers/mmc/pic32_sdhci.c create mode 100644 drivers/net/pic32_eth.c create mode 100644 drivers/net/pic32_eth.h create mode 100644 drivers/net/pic32_mdio.c create mode 100644 drivers/pinctrl/pinctrl_pic32.c create mode 100644 drivers/serial/serial_pic32.c create mode 100644 include/configs/pic32mzdask.h -- 1.8.3.1

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[U-Boot] [PATCH v1 01/14] drivers: clk: Add clock driver for Microchip PIC32 microcontroller
by Purna Chandra Mandal 17 Dec '15

17 Dec '15

This driver implements basic clock modules available in PIC32MZ[DA] platforms. Signed-off-by: Purna Chandra Mandal <purna.mandal(a)microchip.com> --- drivers/clk/Makefile | 1 + drivers/clk/clk-pic32.c | 413 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 414 insertions(+) create mode 100644 drivers/clk/clk-pic32.c diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 4a6a4a8..3c84e08 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o +obj-$(CONFIG_MACH_PIC32) += clk-pic32.o diff --git a/drivers/clk/clk-pic32.c b/drivers/clk/clk-pic32.c new file mode 100644 index 0000000..4ebeee1 --- /dev/null +++ b/drivers/clk/clk-pic32.c @@ -0,0 +1,413 @@ +/* + * Copyright (C) 2015 Purna Chandra Mandal <purna.mandal(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <dm.h> +#include <clk.h> +#include <div64.h> +#include <dm/lists.h> +#include <asm/io.h> +#include <asm/arch-pic32/pic32.h> +#include <asm/arch-pic32/clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Primary oscillator */ +#define SYS_POSC_CLK_HZ 24000000 + +/* Fixed clk rate */ +#define SYS_FRC_CLK_HZ 8000000 + +/* PLL */ +#define ICLK_MASK 0x00000080 +#define PLLIDIV_MASK 0x00000007 +#define PLLODIV_MASK 0x00000007 +#define CUROSC_MASK 0x00000007 +#define PLLMUL_MASK 0x0000007F +#define FRCDIV_MASK 0x00000007 + +/* PBCLK */ +#define PBDIV_MASK 0x00000007 + +/* SYSCLK MUX */ +#define SCLK_SRC_FRC1 0 +#define SCLK_SRC_SPLL 1 +#define SCLK_SRC_POSC 2 +#define SCLK_SRC_FRC2 7 + +/* Reference Oscillator Control Reg fields */ +#define REFO_SEL_MASK 0x0f +#define REFO_SEL_SHIFT 0 +#define REFO_ACTIVE 0x0100 +#define REFO_DIVSW_EN 0x0200 +#define REFO_OE 0x1000 +#define REFO_ON 0x8000 +#define REFO_DIV_SHIFT 16 +#define REFO_DIV_MASK 0x7fff + +/* Reference Oscillator Trim Register Fields */ +#define REFO_TRIM_REG 0x10 +#define REFO_TRIM_MASK 0x1ff +#define REFO_TRIM_SHIFT 23 +#define REFO_TRIM_MAX 511 + +#define ROCLK_SRC_SCLK 0x0 +#define ROCLK_SRC_SPLL 0x7 +#define ROCLK_SRC_ROCLKI 0x8 + +/* Memory PLL */ +#define MPLL_IDIV 0x03 +#define MPLL_MULT 0x32 +#define MPLL_ODIV1 0x02 +#define MPLL_ODIV2 0x01 +#define MPLL_VREG_RDY 0x00800000 +#define MPLL_RDY 0x80000000 +#define MPLL_IDIV_SHIFT 0 +#define MPLL_MULT_SHIFT 8 +#define MPLL_ODIV1_SHIFT 24 +#define MPLL_ODIV2_SHIFT 27 + +static ulong pic32_get_pll_rate(void) +{ + ulong plliclk, v; + u32 iclk, idiv, odiv, mult; + + v = readl(SPLLCON); + iclk = (v & ICLK_MASK); + idiv = ((v >> 8) & PLLIDIV_MASK) + 1; + odiv = ((v >> 24) & PLLODIV_MASK); + mult = ((v >> 16) & PLLMUL_MASK) + 1; + + plliclk = iclk ? SYS_FRC_CLK_HZ : SYS_POSC_CLK_HZ; + + if (odiv < 2) + odiv = 2; + else if (odiv < 5) + odiv = (1 << odiv); + else + odiv = 32; + + return ((plliclk / idiv) * mult) / odiv; +} + +static ulong pic32_get_sysclk(void) +{ + ulong hz; + ulong div, frcdiv; + ulong v = readl(OSCCON); + ulong curr_osc; + + /* get clk source */ + v = readl(OSCCON); + curr_osc = (v >> 12) & CUROSC_MASK; + switch (curr_osc) { + case SCLK_SRC_FRC1: + case SCLK_SRC_FRC2: + frcdiv = ((v >> 24) & FRCDIV_MASK); + div = ((1 << frcdiv) + 1) + (128 * (frcdiv == 7)); + hz = SYS_FRC_CLK_HZ / div; + break; + + case SCLK_SRC_SPLL: + hz = pic32_get_pll_rate(); + break; + + case SCLK_SRC_POSC: + hz = SYS_POSC_CLK_HZ; + break; + + default: + hz = 0; + printf("clk: unknown sclk_src.\n"); + break; + } + + return hz; +} + +static ulong pic32_get_pbclk(int bus) +{ + ulong div, clk_freq; + void __iomem *reg; + + clk_freq = pic32_get_sysclk(); + + reg = (void __iomem *)PB1DIV + (bus * 0x10); + div = (readl(reg) & PBDIV_MASK) + 1; + + return clk_freq / div; +} + +static ulong pic32_get_cpuclk(void) +{ + return pic32_get_pbclk(6); +} + +static ulong pic32_set_refclk(int bus, int parent_rate, int rate, int parent_id) +{ + void __iomem *reg; + u32 div, trim, v; + u64 frac; + ulong base; + + /* calculate dividers, + * rate = parent_rate / [2 * (div + (trim / 512))] + */ + if (parent_rate <= rate) { + div = 0; + trim = 0; + } else { + div = parent_rate / (rate << 1); + frac = parent_rate; + frac <<= 8; + do_div(frac, rate); + frac -= (u64)(div << 9); + trim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : (u32)frac; + } + + reg = (void __iomem *)(REFO1CON + bus * 0x20); + + /* disable clk */ + writel(REFO_ON | REFO_OE, reg + _CLR_OFFSET); + + /* wait till previous src change is active */ + base = get_timer(0); + for (;;) { + v = readl(reg); + if ((v & (REFO_DIVSW_EN | REFO_ACTIVE)) == 0) + break; + if (get_timer(base) >= get_tbclk()) { + printf("refclk: tmout while active\n"); + break; + } + } + + /* parent_id */ + v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT); + v |= (parent_id << REFO_SEL_SHIFT); + + /* apply rodiv */ + v &= ~(REFO_DIV_MASK << REFO_DIV_SHIFT); + v |= (div << REFO_DIV_SHIFT); + writel(v, reg); + + /* apply trim */ + v = readl(reg + REFO_TRIM_REG); + v &= ~(REFO_TRIM_MASK << REFO_TRIM_SHIFT); + v |= (trim << REFO_TRIM_SHIFT); + writel(v, reg + REFO_TRIM_REG); + + /* enable clk */ + writel(REFO_ON | REFO_OE, reg + _SET_OFFSET); + + /* switch divider */ + writel(REFO_DIVSW_EN, reg + _SET_OFFSET); + + base = get_timer(0); + for (;;) { + if (!(readl(reg) & REFO_DIVSW_EN)) + break; + + if (get_timer(base) >= get_tbclk()) { + printf("refclk: tmout while switching.\n"); + break; + } + } + + return 0; +} + +static ulong pic32_get_refclk(int bus) +{ + void __iomem *reg; + u32 rodiv, rotrim, rosel, v, parent_rate; + u64 rate64; + + reg = (void __iomem *)(REFO1CON + bus * 0x20); + v = readl(reg); + + /* get rosel */ + rosel = (v >> REFO_SEL_SHIFT) & REFO_SEL_MASK; + /* get div */ + rodiv = (v >> REFO_DIV_SHIFT) & REFO_DIV_MASK; + /* get trim */ + v = readl(reg + REFO_TRIM_REG); + rotrim = (v >> REFO_TRIM_SHIFT) & REFO_TRIM_MASK; + + if (!rodiv) + return 0; + + /* calc rate */ + switch (rosel) { + default: + case ROCLK_SRC_SCLK: + parent_rate = pic32_get_cpuclk(); + break; + case ROCLK_SRC_SPLL: + parent_rate = pic32_get_pll_rate(); + break; + } + + /* Calculation + * rate = parent_rate / [2 * (div + (trim / 512))] + */ + if (rotrim) { + rodiv <<= 9; + rodiv += rotrim; + rate64 = parent_rate; + rate64 <<= 8; + do_div(rate64, rodiv); + v = (u32)rate64; + } else { + v = parent_rate / (rodiv << 1); + } + return v; +} + +static void mpll_init(void) +{ + u32 v, mask; + ulong base; + + /* initialize */ + v = (MPLL_IDIV << MPLL_IDIV_SHIFT) | + (MPLL_MULT << MPLL_MULT_SHIFT) | + (MPLL_ODIV1 << MPLL_ODIV1_SHIFT) | + (MPLL_ODIV2 << MPLL_ODIV2_SHIFT); + + writel(v, (void __iomem *)CFGMPLL); + + /* Wait for ready */ + mask = MPLL_RDY | MPLL_VREG_RDY; + base = get_timer(0); + for (;;) { + v = readl((void __iomem *)CFGMPLL); + if ((v & mask) == mask) + break; + + if (get_timer(base) >= get_tbclk()) { + printf("refclk: tmout while waiting MPLL ready.\n"); + break; + } + } +} + +static void pic32_clk_init(struct udevice *dev) +{ + ulong rate, pll_hz = pic32_get_pll_rate(); + const void *blob = gd->fdt_blob; + char propname[] = "microchip,refo%d-frequency12345"; + int i; + + /* Initialize REFOs as not initialized and enabled on reset. */ + for (i = 0; i < 5; i++) { + snprintf(propname, sizeof(propname), + "microchip,refo%d-frequency", i + 1); + + rate = fdtdec_get_int(blob, dev->of_offset, propname, 0); + if (rate) + pic32_set_refclk(i, pll_hz, rate, ROCLK_SRC_SPLL); + } + + /* Memory PLL */ + mpll_init(); +} + +struct pic32_clk_platdata { + u32 clk_id; +}; + +static ulong pic32_clk_get_rate(struct udevice *dev) +{ + return pic32_get_cpuclk(); +} + +static ulong pic32_get_periph_rate(struct udevice *dev, int periph) +{ + ulong rate; + + switch (periph) { + case PB1CLK ... PB7CLK: + rate = pic32_get_pbclk(periph - PB1CLK); + break; + case REF1CLK ... REF5CLK: + rate = pic32_get_refclk(periph - REF1CLK); + break; + case PLLCLK: + rate = pic32_get_pll_rate(); + break; + default: + rate = 0; + break; + } + + return rate; +} + +static ulong pic32_set_periph_rate(struct udevice *dev, int periph, ulong rate) +{ + ulong pll_hz; + + switch (periph) { + case REF1CLK ... REF5CLK: + pll_hz = pic32_get_pll_rate(); + pic32_set_refclk(periph - REF1CLK, + pll_hz, rate, ROCLK_SRC_SPLL); + break; + default: + break; + } + + return rate; +} + +static struct clk_ops pic32_pic32_clk_ops = { + .get_rate = pic32_clk_get_rate, + .set_periph_rate = pic32_set_periph_rate, + .get_periph_rate = pic32_get_periph_rate, +}; + +static int pic32_clk_probe(struct udevice *dev) +{ + struct pic32_clk_platdata *plat = dev_get_platdata(dev); + + if (plat->clk_id != BASECLK) + goto out; + + /* initialize only once */ + plat->clk_id |= 0xd0ae0000; + pic32_clk_init(dev); +out: + return 0; +} + +static int pic32_clk_bind(struct udevice *dev) +{ + struct pic32_clk_platdata *plat = dev_get_platdata(dev); + + if (dev->of_offset == -1) { + plat->clk_id = BASECLK; + return 0; + } + + return 0; +} + +static const struct udevice_id pic32_clk_ids[] = { + { .compatible = "microchip,pic32mzda_clk"}, + {} +}; + +U_BOOT_DRIVER(pic32_clk) = { + .name = "pic32_clk", + .id = UCLASS_CLK, + .of_match = pic32_clk_ids, + .platdata_auto_alloc_size = sizeof(struct pic32_clk_platdata), + .ops = &pic32_pic32_clk_ops, + .bind = pic32_clk_bind, + .probe = pic32_clk_probe, +}; -- 1.8.3.1

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[U-Boot] [PATCH v1 00/14] Initial Microchip PIC32MZ[DA] Support
by Purna Chandra Mandal 17 Dec '15

17 Dec '15

This patch series adds support for Microchip PIC32MZ[DA] MIPS micro-controller platform. All drivers required to boot from MMC micro-SD card and network are included in it; pinctrl, clock, serial, SDHCI, gpio, Ethernet. This series been tested on PIC32MZ[DA] Starter Kit. A tree with these changes are available at [0]. [0] https://github.com/purna-mandal/u-boot/tree/pic32-upstream-v1 Cristian Birsan (1): MIPS: pic32: Add driver for Microchip PIC32 internal flash controller. Purna Chandra Mandal (11): drivers: clk: Add clock driver for Microchip PIC32 Microcontroller. MIPS: Add support for Microchip PIC32MZ[DA] SoC family. board: Add Microchip PIC32MZ[DA]-Starter-Kit board. board: pic32mzdask: add flash support for environments. MIPS: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO. drivers: gpio: add driver for Microchip PIC32 GPIO controller. drivers: net: phy: add SMSC LAN8740 Phy support. drivers: net: add Microchip PIC32 ethernet controller driver. board: Add gpio and ethernet support to pic32mzdask board. board: add SDHCI support for PIC32MZDASK board. board: pic32mzdask: Customize U-Boot environments for OS boot. Sandeep Sheriker Mallikarjun (1): drivers: mmc: PIC32MZ[DA] SDHCI workaround when JTAG is not connected. Sorin-Andrei Pistirica (1): drivers: mmc: add driver for Microchip PIC32 SDHCI controller. arch/mips/dts/Makefile | 2 +- arch/mips/dts/pic32mzda.dtsi | 162 ++++++++ arch/mips/dts/pic32mzda_sk.dts | 50 +++ arch/mips/include/asm/arch-pic32/pic32.h | 3 + arch/mips/include/asm/gpio.h | 1 + arch/mips/mach-pic32/Kconfig | 23 +- arch/mips/mach-pic32/Makefile | 5 +- arch/mips/mach-pic32/cpu.c | 121 +++++- arch/mips/mach-pic32/flash.c | 471 ++++++++++++++++++++++ arch/mips/mach-pic32/lowlevel_init.S | 41 ++ arch/mips/mach-pic32/reset.c | 22 ++ board/microchip/pic32mzda/Kconfig | 13 + board/microchip/pic32mzda/MAINTAINERS | 6 + board/microchip/pic32mzda/Makefile | 7 + board/microchip/pic32mzda/README | 22 ++ board/microchip/pic32mzda/config.mk | 4 + board/microchip/pic32mzda/ddr.c | 389 +++++++++++++++++++ board/microchip/pic32mzda/ddr.h | 46 +++ board/microchip/pic32mzda/pic32mzda.c | 41 ++ configs/pic32mzdask_defconfig | 33 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-pic32.c | 413 ++++++++++++++++++++ drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 2 +- drivers/gpio/pic32_gpio.c | 164 ++++++++ drivers/mmc/Kconfig | 6 + drivers/mmc/Makefile | 2 +- drivers/mmc/pic32_sdhci.c | 110 ++++++ drivers/mmc/sdhci.c | 12 + drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/phy/smsc.c | 10 + drivers/net/pic32_eth.c | 648 +++++++++++++++++++++++++++++++ drivers/net/pic32_eth.h | 184 +++++++++ drivers/net/pic32_mdio.c | 143 +++++++ include/configs/pic32mzdask.h | 216 +++++++++++ include/flash.h | 5 +- 37 files changed, 3386 insertions(+), 7 deletions(-) create mode 100644 arch/mips/dts/pic32mzda.dtsi create mode 100644 arch/mips/dts/pic32mzda_sk.dts create mode 100644 arch/mips/include/asm/gpio.h create mode 100644 arch/mips/mach-pic32/flash.c create mode 100644 arch/mips/mach-pic32/lowlevel_init.S create mode 100644 arch/mips/mach-pic32/reset.c create mode 100644 board/microchip/pic32mzda/Kconfig create mode 100644 board/microchip/pic32mzda/MAINTAINERS create mode 100644 board/microchip/pic32mzda/Makefile create mode 100644 board/microchip/pic32mzda/README create mode 100644 board/microchip/pic32mzda/config.mk create mode 100644 board/microchip/pic32mzda/ddr.c create mode 100644 board/microchip/pic32mzda/ddr.h create mode 100644 board/microchip/pic32mzda/pic32mzda.c create mode 100644 configs/pic32mzdask_defconfig create mode 100644 drivers/clk/clk-pic32.c create mode 100644 drivers/gpio/pic32_gpio.c create mode 100644 drivers/mmc/pic32_sdhci.c create mode 100644 drivers/net/pic32_eth.c create mode 100644 drivers/net/pic32_eth.h create mode 100644 drivers/net/pic32_mdio.c create mode 100644 include/configs/pic32mzdask.h -- 1.8.3.1

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[U-Boot] [PATCH] common: usb: Adding delay after set configuration to support legacy devices
by Sriram Dash 17 Dec '15

17 Dec '15

We faced random enumeration failure issue for USB sticks on XHCI driver, specifically the legacy i.e. USB 2.0 storage devices. It seems they do not respond to a USB string descriptor submission within the allowed U-Boot timeout, which is just after sending set configuration. USB stick where this this problem has been noticed are: SanDisk U3 Cruzer Micro 0875530C9FC38749 (Vendor: 0x0781, Product 0x5406) This problem has been reproduced on the Freescale LS2080A, and expected to be hit for any platform with XHCI controller using legacy USB 2.0 devices. This patch solves the above problem by: Adding 10 ms delay after set configuration and let the device to settle down Signed-off-by: Sriram Dash <sriram.dash(a)freescale.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat(a)freescale.com> --- common/usb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/common/usb.c b/common/usb.c index 700bfc3..c624a88 100644 --- a/common/usb.c +++ b/common/usb.c @@ -1104,6 +1104,7 @@ int usb_select_config(struct usb_device *dev) "len %d, status %lX\n", dev->act_len, dev->status); return err; } + mdelay(10); /* Let the SET_CONFIGURATION settle */ debug("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n", dev->descriptor.iManufacturer, dev->descriptor.iProduct, dev->descriptor.iSerialNumber); -- 2.1.0

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Re: [U-Boot] [PATCH] arm: socfpga: Fixed Phy not found error. Fixed QSPI flash not found error Disabled Hardware watch dog by default. Updated MMC clock.
by Marek Vasut 17 Dec '15

17 Dec '15

On Thursday, December 17, 2015 at 07:59:34 AM, ShengjiangWu wrote: > Hi Marek Vasut, Hi, > I will submit it later, thanks for your reminder. Thanks. Also, please do not top-post and please keep the entire Cc list intact. Also keep the ML in the list. > Best Regards > Shengjiang Wu > > > > > ------------------ Original ------------------ > From: "marex";<marex(a)denx.de>; > Date: Thu, Dec 17, 2015 11:46 AM > To: "ShengjiangWu"<shengjiangwu(a)qq.com>; > Cc: "u-boot"<u-boot(a)lists.denx.de>; > "shengjiangwu"<shengjiangwu(a)gmail.com>; "clsee"<clsee(a)altera.com>; > "dinguyen"<dinguyen(a)opensource.altera.com>; > "dinh.linux"<dinh.linux(a)gmail.com>; "pavel"<pavel(a)denx.de>; > "sr"<sr(a)denx.de>; Subject: Re: [PATCH] arm: socfpga: Fixed Phy not found > error. Fixed QSPI flash not found error > Disabled Hardware watch dog by default. Updated MMC clock. > > On Thursday, December 17, 2015 at 04:25:28 AM, ShengjiangWu wrote: > > arm: socfpga: Fixed Phy not found error. > > > > Fixed QSPI flash not found error > > Disabled Hardware watch dog by default. > > Updated MMC clock. > > Fix your mailer please. > > > Updated pinmux and clock for EMAC1 and QSPI flash. > > U-BOOT-2015-10 can run on Cyclone V SoC Development > > Kit (SoCDK) with this fix. > > > > Signed-off-by: swu <shengjiangwu(a)gmail.com> > > Cc: Chin Liang See <clsee(a)altera.com> > > Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> > > Cc: Dinh Nguyen <dinh.linux(a)gmail.com> > > Cc: Pavel Machek <pavel(a)denx.de> > > Cc: Marek Vasut <marex(a)denx.de> > > Cc: Stefan Roese <sr(a)denx.de> > > Please repost the patch using git send-email , details are at [1] and the > process is very similar to Linux. > > I briefly skimmed across the patch. I don't understand why do you replace > almost the entire pinmux just to fix ethernet issue. (ethernet works on > SoCDK I believe, which is another odd thing). > > Furthermore, if you're fixing multiple things, split them into multiple > patches. > > Finally, do not disable HW watchdog. > > [1] www.denx.de/wiki/U-Boot/Patches > > Best regards, > Marek Vasut Best regards, Marek Vasut

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[U-Boot] U boot 2016 rc2 in a Q8 A13 tablet not recognize keyboard.
by far5893 17 Dec '15

17 Dec '15

2016 rc2 version compiled against q8 A13 tablet configuration. SD boot. Usb detect give: failed,-96 error when a keyboard is connected. But recognize mass storage (an empty key memory). IBM Usb Keyboard model SK-8809-2D full working with original android. Silviop

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Re: [U-Boot] ATAGS for Tegra, Sunxi, etc.
by Ian Campbell 17 Dec '15

17 Dec '15

On Thu, 2015-12-17 at 07:40 +0100, Karsten Merker wrote: > On Thu, Dec 17, 2015 at 01:59:57PM +0900, Masahiro Yamada wrote: > > 2015-12-17 13:58 GMT+09:00 Masahiro Yamada <yamada.masahiro(a)socionext.c > > om>: > > > Hi, > > > > > > I noticed some well-maintained new SoC families still > > > define CONFIG_CMDLINE_TAG. > > > > > > > > > For example, > [...] > > > include/configs/sunxi-common.h > > > > > > #define CONFIG_SETUP_MEMORY_TAGS > > > #define CONFIG_CMDLINE_TAG > > > #define CONFIG_INITRD_TAG > > > #define CONFIG_SERIAL_TAG > > > > Do they still use ATAGS, not device tree? > > Sunxi uses devicetree for mainline kernels, but AFAIK ATAG > support is necessary to enable booting legacy vendor kernels. > There is still new sunxi-based hardware sold today that comes > with legacy 3.4-based kernels. That legacy kernel is FEX (allwinners own description blob) based, I don't know to what extent that involves ATAGs in some way though. There are also people who use the 3.4 based fork from linux-sunxi.org, but I don't know if that is DT or ATAGS or FEX. A dependency on CONFIG_OLD_SUNXI_KERNEL_COMPAT might be an option depending on what the kernels need, Hans probably knows better than I do. Ian. > CCing Hans de Goede and Ian Cambell (sunxi maintainers). > > Regards, > Karsten

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[U-Boot] is some old content in arch/arm/include/asm/{memory, setup}.h removable?
by Robert P. J. Day 17 Dec '15

17 Dec '15

poking around in arm header files and it seems that some stuff there is old enough to be removed. first, entire content of arch/arm/include/asm/memory.h is enclosed in "#if 0"; git blame tells me it's been like that since 2003. also, arch/arm/include/asm/setup.h still contains structure for the old, deprecated way to pass parameters to the kernel -- does anyone still use/need that? just curious. rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH v2 0/9] Various microblaze cleanups
by Michal Simek 17 Dec '15

17 Dec '15

Hi, This patch series depends on all previous series. All these patches will be available in git://git.denx.de/u-boot-microblaze.git also with patches which I am going to send now. Thanks, Michal Changes in v2: - Remove also from xparameters.h - new patch in this series - new patch in this series - new patch in this series Michal Simek (9): microblaze: Enable axi emac via Kconfig microblaze: Move eth configuration to Kconfig microblaze: Remove systemace from board file microblaze: Remove CONFIG_FIT from board file microblaze: Move CONFIG_NETCONSOLE to Kconfig microblaze: Remove empty file - cpu.c microblaze: Read information about RAM from DT microblaze: Enable HUSH via Kconfig microblaze: Fix board_init calling sequence arch/microblaze/cpu/Makefile | 2 +- arch/microblaze/cpu/cpu.c | 9 ---- .../xilinx/microblaze-generic/microblaze-generic.c | 15 ++----- board/xilinx/microblaze-generic/xparameters.h | 9 ---- configs/microblaze-generic_defconfig | 8 ++++ include/configs/microblaze-generic.h | 48 +--------------------- 6 files changed, 15 insertions(+), 76 deletions(-) delete mode 100644 arch/microblaze/cpu/cpu.c -- 1.9.1

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[U-Boot] [PATCH v2 00/14] Moving Emaclite to DM + MDIO support
by Michal Simek 17 Dec '15

17 Dec '15

Hi, The first part of this series is about adding MDIO support to driver which was out of mainline and it was much easier to merge it before move to DM. Then driver didn't use indirect register access. In the middle of moving this driver I have fixed logic in some functions which doesn't affect performance of this driver. All these changes were tested on HW design with emaclite with and without pong buffers. This patch series depends on microblaze cleanup series. All these patches will be available in git://git.denx.de/u-boot-microblaze.git also with patches which I am going to send now. Thanks, Michal Changes in v2: - Fix subject to point to rx instead of tx - Fix commit message - Joe - rename nextrxbuffertouse to use_rx_pong_buffer_next - Joe - fix type in immediatelly - Joe - Redesign packet lenght size to two subsequent reads - Remove additional blankline - new patch in this series - Joe Michal Simek (14): net: emaclite: Remove ancient OF probe function net: emaclite: Add MDIO support to driver net: emaclite: Convert MDIO to use register offset net: emaclite: Use indirect register access for tx_ping/pong net: emaclite: Use indirect register access for rx_ping/pong net: emaclite: Use indirect register access for TX reset net: emaclite: Fix logic around available TX buffers net: emaclite: Remove XEL_TSR_XMIT_ACTIVE_MASK flag net: emaclite: Use indirect reg access in send net: emaclite: Use indirect access in emaclite_recv net: emaclite: Move driver to DM net: emaclite: Rename start and stop functions net: emaclite: Let core to handle received packet net: emaclite: Move emaclite to Kconfig .../xilinx/microblaze-generic/microblaze-generic.c | 21 - board/xilinx/microblaze-generic/xparameters.h | 3 - board/xilinx/zynq/board.c | 20 - configs/microblaze-generic_defconfig | 3 +- drivers/net/Kconfig | 8 + drivers/net/xilinx_emaclite.c | 610 ++++++++++++++------- include/configs/microblaze-generic.h | 3 +- include/netdev.h | 3 - 8 files changed, 436 insertions(+), 235 deletions(-) -- 1.9.1

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