December 2015 - U-Boot

[U-Boot] [PATCH] arm: socfpga: Unreset NAND in SPL
by Marek Vasut 19 Dec '15

19 Dec '15

If the system boots from NAND, make sure to de-assert the NAND IP reset, otherwise the system will get stuck. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- arch/arm/mach-socfpga/spl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 775a827..98c16a0 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -40,6 +40,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ case 0x3: /* NAND Flash (3.0V) */ + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); return BOOT_DEVICE_NAND; case 0x4: /* SD/MMC External Transceiver (1.8V) */ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ -- 2.1.4

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[U-Boot] [PATCH] arm: socfpga: Define NAND reset bit
by Marek Vasut 19 Dec '15

19 Dec '15

Define the NAND reset bit and fix the ordering of the macros. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index e50fbd8..2f070f2 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -65,12 +65,13 @@ struct socfpga_reset_manager { */ #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 4) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) #define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) -- 2.1.4

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[U-Boot] [PATCH 1/2] ns16550: update compatible and reg-shift binding
by Thomas Chou 19 Dec '15

19 Dec '15

Update compatible and reg-shift in device tree binding. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- doc/device-tree-bindings/serial/ns16550.txt | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/doc/device-tree-bindings/serial/ns16550.txt b/doc/device-tree-bindings/serial/ns16550.txt index ef0b9ae..2b3904b 100644 --- a/doc/device-tree-bindings/serial/ns16550.txt +++ b/doc/device-tree-bindings/serial/ns16550.txt @@ -3,8 +3,21 @@ NS16550 UART This UART driver supports many chip variants and is used in mamy SoCs. Required properties: -- compatible: "ns16550" or "nvidia,tegra20-uart" +- compatible: one of: + - "ns16550" + - "ns16550a" + - "nvidia,tegra20-uart" + - "snps,dw-apb-uart" + - "ti,omap2-uart" + - "ti,omap3-uart" + - "ti,omap4-uart" + - "ti,am3352-uart" + - "ti,am4372-uart" + - "ti,dra742-uart" - reg: start address and size of registers -- reg-shift: shift value indicating register size: 0=byte, 1=16bit,2=32bit etc. - clock-frequency: input clock frequency for the UART (used to calculate the baud rate divisor) + +Optional properties: +- reg-shift: shift value indicating register size: 0=byte, 1=16bit, 2=32bit etc. + default to 0 if not given. -- 2.5.0

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[U-Boot] [PATCH 0/7] dm: x86: Convert ICH driver fully to driver model PCI API
by Simon Glass 19 Dec '15

19 Dec '15

This is a small series to move the ICH driver over to use the driver model PCI API. It involves creating PCH drivers which the ICH driver can use to find out its base address. At present irq-router is the 'PCH' node in most device tree files. This is not really correct since the router is just one of the functions of the PCH. Another is the SPI bus. So this series also moves irq-router down a level. This still works with the same irq-router driver, since it just searches for the first compatible node it can find. A driver-model-compatible irq-router driver should be written but that is left for later. This series unfortunately needs testing on each board since each has a separate change. I have tested minnowmax and chromebook_link so far. Simon Glass (7): dm: pci: Move pci_bus_to_hose() to compatibility dm: pci: Add a function to write a BAR dm: pci: Avoid using pci_bus_to_hose() in the uclass dm: Expand the uclass for Peripheral Controller Hubs (PCH) dm: x86: Add a driver for Intel PCH7 dm: x86: Add a driver for Intel PCH9 dm: x86: spi: Convert ICH SPI driver to driver model PCI API arch/x86/cpu/irq.c | 7 +- arch/x86/cpu/ivybridge/bd82x6x.c | 11 ++ arch/x86/dts/bayleybay.dts | 160 +++++++++++++++-------------- arch/x86/dts/broadwell_som-6896.dts | 23 +++-- arch/x86/dts/chromebook_link.dts | 3 +- arch/x86/dts/chromebox_panther.dts | 33 +++--- arch/x86/dts/crownbay.dts | 150 ++++++++++++++------------- arch/x86/dts/galileo.dts | 98 +++++++++--------- arch/x86/dts/minnowmax.dts | 158 ++++++++++++++-------------- arch/x86/dts/qemu-x86_i440fx.dts | 26 +++-- arch/x86/dts/qemu-x86_q35.dts | 38 ++++--- arch/x86/lib/Makefile | 1 - drivers/Makefile | 1 + drivers/pch/Makefile | 7 ++ {arch/x86/lib => drivers/pch}/pch-uclass.c | 32 ++++++ drivers/pch/pch7.c | 30 ++++++ drivers/pch/pch9.c | 41 ++++++++ drivers/pci/pci-uclass.c | 24 ++--- drivers/pci/pci_auto.c | 14 +-- drivers/pci/pci_compat.c | 15 +++ drivers/pci/pci_internal.h | 11 ++ drivers/spi/ich.c | 115 +++++---------------- include/pch.h | 66 ++++++++++++ include/pci.h | 11 ++ 24 files changed, 639 insertions(+), 436 deletions(-) create mode 100644 drivers/pch/Makefile rename {arch/x86/lib => drivers/pch}/pch-uclass.c (53%) create mode 100644 drivers/pch/pch7.c create mode 100644 drivers/pch/pch9.c create mode 100644 include/pch.h -- 2.6.0.rc2.230.g3dd15c0

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[U-Boot] [GIT PULL] Xilinx changes for Zynq and Microblaze
by Michal Simek 18 Dec '15

18 Dec '15

Hi Tom, here are fixes which I have in my queue for 2016.1. Moving Microblaze drivers to DM will be send after 2016.1 because there are some stuff which are not fully reviewed yet. This patchset contain fixes for zybo, mkimage, gem and microblaze. There is also one generic fix for MANUAL_RELOC for net DM. Thanks, Michal The following changes since commit 9cddb4fe0266484aab9babdd2ebe650021644ea9: Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq (2015-12-17 07:52:56 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master for you to fetch changes up to b5e9b9a9a1bb231e35e206f8f3e2becee1dd06ab: microblaze: Do not handle watchdog and gpio in SPL (2015-12-18 13:15:58 +0100) ---------------------------------------------------------------- Michal Simek (13): ARM: zynq: Enable u-boot,dm-pre-reloc for sdhci net: gem: Setup default phy address to -1 net: gem: Fix return value from recv net: gem: Separate recv and free_pkt functions net: gem: Fix typo in Kconfig entry net: gem: Add driver dependencies to PHYLIB dm: net: Fix DM for targets which use MANUAL_RELOC microblaze: Make room for malloc before ELF microblaze: Use malloc setting via Kconfig microblaze: Remove support for LL_TEMAC microblaze: Enable OF_CONTROL by default microblaze: Enable DM by default microblaze: Do not handle watchdog and gpio in SPL Nathan Rossi (4): ARM: zynq: Add default ps7_init_gpl.c/h for ZYBO tools: zynqimage: Clean up check_params spi: zynq_qspi: Add configuration to disable LQSPI feature arm: zynq: Update ZYBO config options arch/arm/dts/zynq-zc706.dts | 2 + arch/arm/dts/zynq-zed.dts | 2 + arch/arm/dts/zynq-zybo.dts | 18 + arch/arm/mach-zynq/Kconfig | 1 - arch/microblaze/Kconfig | 2 + board/xilinx/microblaze-generic/microblaze-generic.c | 38 +- board/xilinx/microblaze-generic/xparameters.h | 6 - board/xilinx/zynq/Makefile | 1 + board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c | 11948 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h | 97 ++ configs/microblaze-generic_defconfig | 2 +- configs/zynq_microzed_defconfig | 1 - configs/zynq_picozed_defconfig | 1 - configs/zynq_zc702_defconfig | 1 - configs/zynq_zc706_defconfig | 1 - configs/zynq_zc770_xm010_defconfig | 1 - configs/zynq_zc770_xm011_defconfig | 1 - configs/zynq_zc770_xm012_defconfig | 1 - configs/zynq_zc770_xm013_defconfig | 1 - configs/zynq_zed_defconfig | 1 - configs/zynq_zybo_defconfig | 4 +- drivers/net/Kconfig | 3 +- drivers/net/zynq_gem.c | 61 +- drivers/spi/zynq_qspi.c | 9 + include/configs/microblaze-generic.h | 21 +- include/configs/xilinx_zynqmp.h | 1 - include/configs/zynq_zybo.h | 1 + net/eth.c | 28 + tools/zynqimage.c | 3 +- 29 files changed, 12159 insertions(+), 98 deletions(-) create mode 100644 board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c create mode 100644 board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 18 Dec '15

18 Dec '15

The following changes since commit 52bc7c7e2b31d6ba8d394f3d22b551abfa365363: eeprom: fix eeprom write procedure (2015-12-16 10:31:31 -0500) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to e4b70d80350c1238fa07872d71c19e3ddbf53b76: usb: kbd: don't use int xfers when polling via ctrl xfers (2015-12-17 21:54:41 +0100) ---------------------------------------------------------------- Alexey Brodkin (1): usb: add support of generic OHCI devices Marek Vasut (24): usb: s3c-otg: Rename regs-otg.h to s3c_udc_otg_regs.h usb: s3c-otg: Rename struct s3c_udc to dwc2_udc usb: s3c-otg: Rename struct s3c_usbotg_reg to dwc2_usbotg_reg usb: s3c-otg: Split private bits from s3c_udc.h usb: s3c-otg: Rename struct s3c_usbotg_phy to dwc2_usbotg_phy usb: s3c-otg: Rename struct s3c_dev_*_ep usb: s3c-otg: Rename struct s3c_ep usb: s3c-otg: Rename struct s3c_request usb: s3c-otg: Staticize s3c_udc_ep_set_stall usb: s3c-otg: Staticize functions in s3c_udc_otg_xfer_dma.c usb: s3c-otg: Rename s3c_ep0_*() functions usb: s3c-otg: Rename s3c_ep_*() functions usb: s3c-otg: Rename s3c_udc_*() functions usb: s3c-otg: Rename remaining local s3c_*() functions usb: s3c-otg: Zap useless externs usb: s3c-otg: Change the driver name to dwc2-udc usb: s3c-otg: Rename local headers to dwc2_*h usb: s3c-otg: Rename sources to dwc2_*c usb: s3c-otg: Rename remaining macros usb: s3c-otg: Tweak the comments usb: s3c-otg: Rename USB_GADGET_S3C_UDC_OTG* to USB_GADGET_DWC2_OTG* usb: s3c-otg: Rename struct s3c_plat_otg_data usb: s3c-otg: Rename s3c_udc_probe() function usb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.h Stephen Warren (1): usb: kbd: don't use int xfers when polling via ctrl xfers Łukasz Majewski (1): usb: host: ehci: samsung: Move hcor initialization after usb phy setup board/altera/arria5-socdk/socfpga.c | 6 +- board/altera/cyclone5-socdk/socfpga.c | 6 +- board/broadcom/bcm28155_ap/bcm28155_ap.c | 8 +-- board/denx/mcvevk/socfpga.c | 6 +- board/ebv/socrates/socfpga.c | 6 +- board/samsung/goni/goni.c | 6 +- board/samsung/odroid/odroid.c | 6 +- board/samsung/trats/trats.c | 8 +-- board/samsung/trats2/trats2.c | 6 +- board/samsung/universal_c210/universal.c | 6 +- board/terasic/sockit/socfpga.c | 6 +- common/usb_kbd.c | 3 + drivers/usb/gadget/Makefile | 4 +- drivers/usb/gadget/bcm_udc_otg_phy.c | 6 +- drivers/usb/gadget/{s3c_udc_otg.c => dwc2_udc_otg.c} | 205 ++++++++++++++++++++++++++++++++++--------------------------------- drivers/usb/gadget/{s3c_udc_otg_phy.c => dwc2_udc_otg_phy.c} | 21 +++---- include/usb/s3c_udc.h => drivers/usb/gadget/dwc2_udc_otg_priv.h | 45 +++++---------- drivers/usb/gadget/{regs-otg.h => dwc2_udc_otg_regs.h} | 32 +++++------ drivers/usb/gadget/{s3c_udc_otg_xfer_dma.c => dwc2_udc_otg_xfer_dma.c} | 202 +++++++++++++++++++++++++++++++++--------------------------------- drivers/usb/host/Kconfig | 8 +++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-exynos.c | 4 +- drivers/usb/host/ohci-generic.c | 45 +++++++++++++++ include/configs/bcm28155_ap.h | 2 +- include/configs/exynos4-common.h | 4 +- include/configs/s5p_goni.h | 4 +- include/configs/s5pc210_universal.h | 4 +- include/configs/smdkv310.h | 4 +- include/configs/socfpga_common.h | 2 +- include/usb/dwc2_udc.h | 25 +++++++++ 30 files changed, 380 insertions(+), 311 deletions(-) rename drivers/usb/gadget/{s3c_udc_otg.c => dwc2_udc_otg.c} (77%) rename drivers/usb/gadget/{s3c_udc_otg_phy.c => dwc2_udc_otg_phy.c} (83%) rename include/usb/s3c_udc.h => drivers/usb/gadget/dwc2_udc_otg_priv.h (67%) rename drivers/usb/gadget/{regs-otg.h => dwc2_udc_otg_regs.h} (92%) rename drivers/usb/gadget/{s3c_udc_otg_xfer_dma.c => dwc2_udc_otg_xfer_dma.c} (88%) create mode 100644 drivers/usb/host/ohci-generic.c create mode 100644 include/usb/dwc2_udc.h

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[U-Boot] [PATCH] altera_qspi: initialize instr.mtd in flash_erase
by Thomas Chou 18 Dec '15

18 Dec '15

Initialize instr.mtd in flash_erase(). This fixes the system hang issue when CONFIG_MTD_PARTITIONS is selected. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- drivers/mtd/altera_qspi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c index 617bf5d..c7e37ad 100644 --- a/drivers/mtd/altera_qspi.c +++ b/drivers/mtd/altera_qspi.c @@ -81,6 +81,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) int ret; memset(&instr, 0, sizeof(instr)); + instr.mtd = mtd; instr.addr = mtd->erasesize * s_first; instr.len = mtd->erasesize * (s_last + 1 - s_first); ret = mtd_erase(mtd, &instr); -- 2.5.0

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Re: [U-Boot] [PATCH v2] arm: socfpga: Fix emac1 doesn't work on socdk board
by 圣江吴 18 Dec '15

18 Dec '15

On Dec 18, 2015, at 12:46 AM, Chin Liang See <clsee(a)altera.com> wrote: Hi Shengjiang, On Fri, 2015-12-18 at 16:43 +0800, shengjiangwu wrote: Updated pinmux group MIXED1IO[0-13] for RGMII1. Updated EMAC1 clock. Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- Changes for v2: - fixed wrong perpll for emac1 --- board/altera/cyclone5-socdk/qts/pll_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index eccc705..5b754ac 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -65,7 +65,7 @@ #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 50000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 This is good. But I believe you miss the pinmux change here. You just need to take the previous patch and made the change. Thanks Chin Liang Sorry for not familiar with re-patch process. Best Regards Shengjiangwu #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 #define CONFIG_HPS_CLK_NAND_HZ 50000000 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000

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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
by 圣江吴 18 Dec '15

18 Dec '15

Hi Chin, The PLL settings are copied from previous version http://git.rocketboards.org/u-boot-socfpga.git, On Dec 17, 2015, at 11:45 PM, Chin Liang See <clsee(a)altera.com> wrote: Hi Shengjiang, On Fri, 2015-12-18 at 15:21 +0800, shengjiangwu wrote: Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock. Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 ++++++------ board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 442b1e0..06783dc 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = { 2, /* MIXED1IO12 */ 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ 0, /* MIXED1IO21 */ 0, /* MIXED2IO0 */ 0, /* MIXED2IO1 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 42905f4..eccc705 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -14,7 +14,7 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 @@ -32,7 +32,7 @@ #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1 Let's not change this as we are using mainpll for QSPI clock. Besides that, the QSPI perpll will yield 500MHz which exceed the 400MHz max clock. Thanks Chin Liang OK, I will restore CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT as 511 Thanks ShengjiangWu #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511

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Re: [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board
by Marek Vasut 18 Dec '15

18 Dec '15

On Friday, December 18, 2015 at 07:36:28 AM, 圣江吴 wrote: > Hi Marek Vasut, Hi, > I'm not sure if the format is correct, I don't know why patch is plain text > instead of a .patch file. Could you please help to review? Thanks. please keep the list on Cc and do not top-post. It seems your mailer is corrupting patches, it replaces tabs with spaces. The established procedure is to submit patches inline, so they can be reviewed ; patch file does not allow that. > Best Regards > ShengjiangWu > > On Dec 17, 2015, at 10:18 PM, shengjiangwu <shengjiangwu(a)icloud.com> wrote: > > Updated pinmux group MIXED1IO[0-13] for RGMII1. > Updated EMAC1 clock. > > Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> > Cc: Chin Liang See <clsee(a)altera.com> > Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> > Cc: Dinh Nguyen <dinh.linux(a)gmail.com> > Cc: Pavel Machek <pavel(a)denx.de> > Cc: Marek Vasut <marex(a)denx.de> > Cc: Stefan Roese <sr(a)denx.de> > --- > board/altera/cyclone5-socdk/qts/pinmux_config.h | 28 > +++++++++++------------ board/altera/cyclone5-socdk/qts/pll_config.h | 4 > ++-- > 2 files changed, 16 insertions(+), 16 deletions(-) > > diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h > b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 33cf1fd..442b1e0 > 100644 > --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h > +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h > @@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = { > 0, /* GENERALIO29 */ > 0, /* GENERALIO30 */ > 0, /* GENERALIO31 */ > - 0, /* MIXED1IO0 */ > - 1, /* MIXED1IO1 */ > - 1, /* MIXED1IO2 */ > - 1, /* MIXED1IO3 */ > - 1, /* MIXED1IO4 */ > - 0, /* MIXED1IO5 */ > - 0, /* MIXED1IO6 */ > - 0, /* MIXED1IO7 */ > - 1, /* MIXED1IO8 */ > - 1, /* MIXED1IO9 */ > - 1, /* MIXED1IO10 */ > - 1, /* MIXED1IO11 */ > - 0, /* MIXED1IO12 */ > - 0, /* MIXED1IO13 */ > + 2, /* MIXED1IO0 */ > + 2, /* MIXED1IO1 */ > + 2, /* MIXED1IO2 */ > + 2, /* MIXED1IO3 */ > + 2, /* MIXED1IO4 */ > + 2, /* MIXED1IO5 */ > + 2, /* MIXED1IO6 */ > + 2, /* MIXED1IO7 */ > + 2, /* MIXED1IO8 */ > + 2, /* MIXED1IO9 */ > + 2, /* MIXED1IO10 */ > + 2, /* MIXED1IO11 */ > + 2, /* MIXED1IO12 */ > + 2, /* MIXED1IO13 */ > 0, /* MIXED1IO14 */ > 1, /* MIXED1IO15 */ > 1, /* MIXED1IO16 */ > diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h > b/board/altera/cyclone5-socdk/qts/pll_config.h index 3d621ed..42905f4 > 100644 > --- a/board/altera/cyclone5-socdk/qts/pll_config.h > +++ b/board/altera/cyclone5-socdk/qts/pll_config.h > @@ -31,7 +31,7 @@ > #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 > #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 > #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 > -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 > +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 > #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 > #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 > #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 > @@ -65,7 +65,7 @@ > #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 > #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 > #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 > -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 > +#define CONFIG_HPS_CLK_EMAC1_HZ 50000000 > #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 > #define CONFIG_HPS_CLK_NAND_HZ 50000000 > #define CONFIG_HPS_CLK_SDMMC_HZ 200000000

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