December 2015 - U-Boot

[U-Boot] [PATCH] net: eth_designware: select PHYLIB in Kconfig
by Thomas Chou 21 Dec '15

21 Dec '15

Select PHYLIB in drivers/net/Kconfig. And remove CONFIG_PHYLIB from legacy board header files. This fixed the warnings when both ALTERA_TSE and ETH_DESIGNWARE are selected. Reported-by: Pavel Machek <pavel(a)denx.de> Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- drivers/net/Kconfig | 1 + include/configs/axs101.h | 1 - include/configs/bf609-ezkit.h | 1 - include/configs/galileo.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/spear-common.h | 1 - include/configs/stv0991.h | 1 - include/configs/sunxi-common.h | 1 - include/configs/tb100.h | 1 - include/configs/x600.h | 1 - 10 files changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index a03a95d..4b04d09 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -88,6 +88,7 @@ config ETH_SANDBOX_RAW config ETH_DESIGNWARE bool "Synopsys Designware Ethernet MAC" + select PHYLIB help This MAC is present in SoCs from various vendors. It supports 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 650d97d..eeb2ae6 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -95,7 +95,6 @@ /* * Ethernet PHY configuration */ -#define CONFIG_PHYLIB #define CONFIG_MII #define CONFIG_PHY_GIGE diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 0e353b9..b5d4847 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -75,7 +75,6 @@ #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_CMD_MII #define CONFIG_MII -#define CONFIG_PHYLIB /* i2c Settings */ #define CONFIG_SYS_I2C diff --git a/include/configs/galileo.h b/include/configs/galileo.h index eb16a5e..14a42b1 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -45,7 +45,6 @@ /* 10/100M Ethernet support */ #define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_PHYLIB /* Environment configuration */ #define CONFIG_ENV_SECT_SIZE 0x1000 diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index b3f65b6..86eccba 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -105,7 +105,6 @@ #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_MII #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) -#define CONFIG_PHYLIB #define CONFIG_PHY_GIGE #endif diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 1d69477..d2630f4 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -17,7 +17,6 @@ /* Ethernet driver configuration */ #define CONFIG_MII -#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 14c6a9e..f421321 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -53,7 +53,6 @@ /* GMAC related configs */ #define CONFIG_MII -#define CONFIG_PHYLIB #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_PHY_MICREL diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 98a2c74..31a68ac 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -312,7 +312,6 @@ extern int soft_i2c_gpio_scl; #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ #define CONFIG_PHY_ADDR 1 #define CONFIG_MII /* MII PHY management */ -#define CONFIG_PHYLIB #endif #ifdef CONFIG_USB_EHCI_HCD diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 8660ed4..e06484f 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -42,7 +42,6 @@ /* * Ethernet PHY configuration */ -#define CONFIG_PHYLIB #define CONFIG_PHY_GIGE /* diff --git a/include/configs/x600.h b/include/configs/x600.h index 58f1aca..0263c50 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -77,7 +77,6 @@ /* Ethernet config options */ #define CONFIG_MII -#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ -- 2.5.0

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[U-Boot] [PATCH v2] arm: mvebu: Print CPU and SDRAM frequency upon startup
by Stefan Roese 21 Dec '15

21 Dec '15

With this patch, the CPU and the DDR frequencies will get printed in the U-Boot startup messages. Resulting in such a log: U-Boot 2016.01-rc2-00188-gb8eeaec-dirty (Dec 21 2015 - 12:32:35 +0100) SoC: MV78460-B0 at 1600 MHz I2C: ready DRAM: 4 GiB (800 MHz, ECC not enabled) ... Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- v2: - Only support board_add_ram_info() for AXP / A38x (Kirkwood does not support it - yet) arch/arm/mach-mvebu/cpu.c | 100 +++++++++++++++++++++++++++++++-- arch/arm/mach-mvebu/dram.c | 11 +++- arch/arm/mach-mvebu/include/mach/cpu.h | 10 ++++ 3 files changed, 113 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index c9b9c77..6ea558c 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -60,10 +60,95 @@ int mvebu_soc_family(void) } #if defined(CONFIG_DISPLAY_CPUINFO) + +#if defined(CONFIG_ARMADA_38X) +/* SAR values for Armada 38x */ +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) +#define SAR_CPU_FREQ_OFFS 10 +#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) + +struct sar_freq_modes sar_freq_tab[] = { + { 0x0, 0x0, 666, 333, 333 }, + { 0x2, 0x0, 800, 400, 400 }, + { 0x4, 0x0, 1066, 533, 533 }, + { 0x6, 0x0, 1200, 600, 600 }, + { 0x8, 0x0, 1332, 666, 666 }, + { 0xc, 0x0, 1600, 800, 800 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ +}; +#else +/* SAR values for Armada XP */ +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) +#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) +#define SAR_CPU_FREQ_OFFS 21 +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) +#define SAR_FFC_FREQ_OFFS 24 +#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) +#define SAR2_CPU_FREQ_OFFS 20 +#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) + +struct sar_freq_modes sar_freq_tab[] = { + { 0xa, 0x5, 800, 400, 400 }, + { 0x1, 0x5, 1066, 533, 533 }, + { 0x2, 0x5, 1200, 600, 600 }, + { 0x2, 0x9, 1200, 600, 400 }, + { 0x3, 0x5, 1333, 667, 667 }, + { 0x4, 0x5, 1500, 750, 750 }, + { 0x4, 0x9, 1500, 750, 500 }, + { 0xb, 0x9, 1600, 800, 533 }, + { 0xb, 0xa, 1600, 800, 640 }, + { 0xb, 0x5, 1600, 800, 800 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ +}; +#endif + +void get_sar_freq(struct sar_freq_modes *sar_freq) +{ + u32 val; + u32 freq; + int i; + + val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS; +#if !defined(CONFIG_ARMADA_38X) + /* + * Shift CPU0 clock frequency select bit from SAR2 register + * into correct position + */ + freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK) + >> SAR2_CPU_FREQ_OFFS) << 3; +#endif + for (i = 0; sar_freq_tab[i].val != 0xff; i++) { + if (sar_freq_tab[i].val == freq) { +#if defined(CONFIG_ARMADA_38X) + *sar_freq = sar_freq_tab[i]; + return; +#else + int k; + u8 ffc; + + ffc = (val & SAR_FFC_FREQ_MASK) >> + SAR_FFC_FREQ_OFFS; + for (k = i; sar_freq_tab[k].ffc != 0xff; k++) { + if (sar_freq_tab[k].ffc == ffc) { + *sar_freq = sar_freq_tab[k]; + return; + } + } + i = k; +#endif + } + } + + /* SAR value not found, return 0 for frequencies */ + *sar_freq = sar_freq_tab[i - 1]; +} + int print_cpuinfo(void) { u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; + struct sar_freq_modes sar_freq; puts("SoC: "); @@ -91,13 +176,13 @@ int print_cpuinfo(void) if (mvebu_soc_family() == MVEBU_SOC_AXP) { switch (revid) { case 1: - puts("A0\n"); + puts("A0"); break; case 2: - puts("B0\n"); + puts("B0"); break; default: - printf("?? (%x)\n", revid); + printf("?? (%x)", revid); break; } } @@ -105,17 +190,20 @@ int print_cpuinfo(void) if (mvebu_soc_family() == MVEBU_SOC_A38X) { switch (revid) { case MV_88F68XX_Z1_ID: - puts("Z1\n"); + puts("Z1"); break; case MV_88F68XX_A0_ID: - puts("A0\n"); + puts("A0"); break; default: - printf("?? (%x)\n", revid); + printf("?? (%x)", revid); break; } } + get_sar_freq(&sar_freq); + printf(" at %d MHz\n", sar_freq.p_clk); + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index ddc5b7e..059151a 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -292,11 +292,18 @@ void dram_init_banksize(void) } } +#if defined(CONFIG_ARMADA_XP) void board_add_ram_info(int use_default) { + struct sar_freq_modes sar_freq; + + get_sar_freq(&sar_freq); + printf(" (%d MHz, ", sar_freq.d_clk); + if (ecc_enabled()) - printf(" (ECC"); + printf("ECC"); else - printf(" (ECC not"); + printf("ECC not"); printf(" enabled)"); } +#endif diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 5e8bf0c..47f45c1 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -106,6 +106,14 @@ struct kwgpio_registers { u32 irq_level; }; +struct sar_freq_modes { + u8 val; + u8 ffc; /* Fabric Frequency Configuration */ + u32 p_clk; + u32 nb_clk; + u32 d_clk; +}; + /* Needed for dynamic (board-specific) mbus configuration */ extern struct mvebu_mbus_state mbus_state; @@ -123,6 +131,8 @@ void return_to_bootrom(void); int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); +void get_sar_freq(struct sar_freq_modes *sar_freq); + /* * Highspeed SERDES PHY config init, ported from bin_hdr * to mainline U-Boot -- 2.6.4

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[U-Boot] [PATCH] arm: mvebu: Print CPU and SDRAM frequency upon startup
by Stefan Roese 21 Dec '15

21 Dec '15

With this patch, the CPU and the DDR frequencies will get printed in the U-Boot startup messages. Resulting in such a log: U-Boot 2016.01-rc2-00188-gb8eeaec-dirty (Dec 21 2015 - 12:32:35 +0100) SoC: MV78460-B0 at 1600 MHz I2C: ready DRAM: 4 GiB (800 MHz, ECC not enabled) ... Signed-off-by: Stefan Roese <sr(a)denx.de> --- arch/arm/mach-mvebu/cpu.c | 100 +++++++++++++++++++++++++++++++-- arch/arm/mach-mvebu/dram.c | 9 ++- arch/arm/mach-mvebu/include/mach/cpu.h | 10 ++++ 3 files changed, 111 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index c9b9c77..473b8f7 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -60,10 +60,95 @@ int mvebu_soc_family(void) } #if defined(CONFIG_DISPLAY_CPUINFO) + +#if defined(CONFIG_ARMADA_38X) +/* SAR values for Armada 38x */ +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) +#define SAR_CPU_FREQ_OFFS 10 +#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) + +static const struct sar_freq_modes sar_freq_tab[] = { + { 0x0, 0x0, 666, 333, 333 }, + { 0x2, 0x0, 800, 400, 400 }, + { 0x4, 0x0, 1066, 533, 533 }, + { 0x6, 0x0, 1200, 600, 600 }, + { 0x8, 0x0, 1332, 666, 666 }, + { 0xc, 0x0, 1600, 800, 800 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ +}; +#else +/* SAR values for Armada XP */ +#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) +#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) +#define SAR_CPU_FREQ_OFFS 21 +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) +#define SAR_FFC_FREQ_OFFS 24 +#define SAR_FFC_FREQ_MASK (0xf << SAR_FFC_FREQ_OFFS) +#define SAR2_CPU_FREQ_OFFS 20 +#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS) + +static const struct sar_freq_modes sar_freq_tab[] = { + { 0xa, 0x5, 800, 400, 400 }, + { 0x1, 0x5, 1066, 533, 533 }, + { 0x2, 0x5, 1200, 600, 600 }, + { 0x2, 0x9, 1200, 600, 400 }, + { 0x3, 0x5, 1333, 667, 667 }, + { 0x4, 0x5, 1500, 750, 750 }, + { 0x4, 0x9, 1500, 750, 500 }, + { 0xb, 0x9, 1600, 800, 533 }, + { 0xb, 0xa, 1600, 800, 640 }, + { 0xb, 0x5, 1600, 800, 800 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ +}; +#endif + +void get_sar_freq(struct sar_freq_modes *sar_freq) +{ + u32 val; + u32 freq; + int i; + + val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS; +#if !defined(CONFIG_ARMADA_38X) + /* + * Shift CPU0 clock frequency select bit from SAR2 register + * into correct position + */ + freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK) + >> SAR2_CPU_FREQ_OFFS) << 3; +#endif + for (i = 0; sar_freq_tab[i].val != 0xff; i++) { + if (sar_freq_tab[i].val == freq) { +#if defined(CONFIG_ARMADA_38X) + *sar_freq = sar_freq_tab[i]; + return; +#else + int k; + u8 ffc; + + ffc = (val & SAR_FFC_FREQ_MASK) >> + SAR_FFC_FREQ_OFFS; + for (k = i; sar_freq_tab[k].ffc != 0xff; k++) { + if (sar_freq_tab[k].ffc == ffc) { + *sar_freq = sar_freq_tab[k]; + return; + } + } + i = k; +#endif + } + } + + /* SAR value not found, return 0 for frequencies */ + *sar_freq = sar_freq_tab[i - 1]; +} + int print_cpuinfo(void) { u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff; + struct sar_freq_modes sar_freq; puts("SoC: "); @@ -91,13 +176,13 @@ int print_cpuinfo(void) if (mvebu_soc_family() == MVEBU_SOC_AXP) { switch (revid) { case 1: - puts("A0\n"); + puts("A0"); break; case 2: - puts("B0\n"); + puts("B0"); break; default: - printf("?? (%x)\n", revid); + printf("?? (%x)", revid); break; } } @@ -105,17 +190,20 @@ int print_cpuinfo(void) if (mvebu_soc_family() == MVEBU_SOC_A38X) { switch (revid) { case MV_88F68XX_Z1_ID: - puts("Z1\n"); + puts("Z1"); break; case MV_88F68XX_A0_ID: - puts("A0\n"); + puts("A0"); break; default: - printf("?? (%x)\n", revid); + printf("?? (%x)", revid); break; } } + get_sar_freq(&sar_freq); + printf(" at %d MHz\n", sar_freq.p_clk); + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index ddc5b7e..bfa21a1 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -294,9 +294,14 @@ void dram_init_banksize(void) void board_add_ram_info(int use_default) { + struct sar_freq_modes sar_freq; + + get_sar_freq(&sar_freq); + printf(" (%d MHz, ", sar_freq.d_clk); + if (ecc_enabled()) - printf(" (ECC"); + printf("ECC"); else - printf(" (ECC not"); + printf("ECC not"); printf(" enabled)"); } diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 3df86f9..017d55f 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -106,6 +106,14 @@ struct kwgpio_registers { u32 irq_level; }; +struct sar_freq_modes { + u8 val; + u8 ffc; /* Fabric Frequency Configuration */ + u32 p_clk; + u32 nb_clk; + u32 d_clk; +}; + /* Needed for dynamic (board-specific) mbus configuration */ extern struct mvebu_mbus_state mbus_state; @@ -123,6 +131,8 @@ void return_to_bootrom(void); int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); +void get_sar_freq(struct sar_freq_modes *sar_freq); + /* * Highspeed SERDES PHY config init, ported from bin_hdr * to mainline U-Boot -- 1.9.1

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[U-Boot] [PATCH 0/2] Rockchip: USB: added usb phy control to support fastboot
by Frank Wang 21 Dec '15

21 Dec '15

This series adds support for fastboot related to USB. [PATCH 1/2] fixed max packet size check error for ep_in in high speed condition [PATCH 2/2] add usb phy control to support fastboot for rk3036 Tested on RK3036 SDK board, it works Okay. board/evb_rk3036/evb_rk3036/evb_rk3036.c | 27 ++++++++++++++++++++++ drivers/usb/gadget/Makefile | 1 + drivers/usb/gadget/rk_udc_otg_phy.c | 36 ++++++++++++++++++++++++++++++ drivers/usb/gadget/s3c_udc_otg.c | 4 ++-- include/configs/rk3036_common.h | 19 ++++++++++++++++ 5 files changed, 85 insertions(+), 2 deletions(-) create mode 100644 drivers/usb/gadget/rk_udc_otg_phy.c -- 1.7.9.5

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[U-Boot] [PATCH] mtd: nand: denali_spl: Program spare area skip bytes
by Marek Vasut 21 Dec '15

21 Dec '15

This register is not configured on Altera SoCFPGA incarnation of the Denali NAND flash block. Unless this register is initialized, the IP will return corrupted data upon any read attempt from the NAND. Initialize the register to the same value is the one used in full U-Boot to fix this issue. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> Cc: Scott Wood <scottwood(a)freescale.com> --- drivers/mtd/nand/denali_spl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c index 1587413..8c707d2 100644 --- a/drivers/mtd/nand/denali_spl.c +++ b/drivers/mtd/nand/denali_spl.c @@ -168,6 +168,10 @@ void nand_init(void) page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE); oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE); pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK); + + /* Spare area skip bytes is NOT programmed by hardware %^( */ + writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES, + denali_flash_reg + SPARE_AREA_SKIP_BYTES); } int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) -- 2.1.4

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[U-Boot] [PATCH] net: e1000: use correct hepler to do endianess conversion
by Miao Yan 21 Dec '15

21 Dec '15

In struct e1000_rx_desc, field 'length' is declared as uint16_t, so use le16_to_cpu() to do endianess conversion. Also drop conversion on 'status' which is declared as uint8_t. Signed-off-by: Miao Yan <yanmiaobest(a)gmail.com> --- drivers/net/e1000.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 2ba03ed..6124bf0 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -5165,11 +5165,11 @@ _e1000_poll(struct e1000_hw *hw) inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN); invalidate_dcache_range(inval_start, inval_end); - if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) + if (!(rd->status & E1000_RXD_STAT_DD)) return 0; /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ /* Packet received, make sure the data are re-loaded from RAM. */ - len = le32_to_cpu(rd->length); + len = le16_to_cpu(rd->length); invalidate_dcache_range((unsigned long)packet, (unsigned long)packet + roundup(len, ARCH_DMA_MINALIGN)); -- 1.9.1

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[U-Boot] help - u-boot on powerpc qemu
by 吴红青 21 Dec '15

21 Dec '15

hello,i am using u-boot on powerpc qemu,my u-boot version is u-boot-2016.01-rc2,i make uboot as below: cd u-boot-2016.01-rc2 make clean make ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- qemu-ppce500_defconfig make ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- then ,t execute u-boot bay qemu as below: qemu-system-ppc -M ppce500 -serial stdio -kernel u-boot -m 1024 uboot show some msg as below: U-Boot 2016.01-rc2 (Dec 13 2015 - 19:54:13 +0800) CPU: Unknown, Version: 0.0, (0x00000000) Core: e500, Version: 3.0, (0x80210030) Clock Configuration: CPU0:400 MHz, CCB:400 MHz, DDR:200 MHz (400 MT/s data rate), LBC: unknown (LCRR[CLKDIV] = 0x00) L1: D-cache 32 KiB enabled I-cache 32 KiB enabled DRAM: 1 GiB L2: disabled Using default environment PCI: base address e0008000 00:01.0 - 1af4:1000 - Network controller PCI1: Bus 00 - 00 In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 WARNING: adjusting available memory to 30000000 Wrong Image Format for bootm command ERROR: can't get kernel image! => why no net card? can you help me? thanks you!!!

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[U-Boot] [PATCH v2 0/9] x86: fsp: Move platform-specific config to chipset directory
by Bin Meng 21 Dec '15

21 Dec '15

All FSP spec v1.0 complaint FSP binary uses struct fspinit_rtbuf as defined by the 1.0 spec, however there are FSPs that do not follow 1.0 spec, like Intel FSP for 3rd generation Intel Core and Intel Celeron processors with mobile Intel HM76 and QM77 chipsets platform (formerly Chief River Platform: Ivy Bridge and Panther Point). Although Intel website says this FSP conforms to FSP v1.0 specification which defines the UPD usage, it is not really the case. This might possible due to that FSP predates the 1.0 spec. Also future FSP binary that is complaint to v1.1 spec defines an optional paltform-specific runtime data in the struct fspinit_rtbuf. Besides this fspinit_rtbuf, the IvyBridge FSP does not support UPD either, so that current codes in arch/x86/lib/fsp/fsp_support.c won't work for that FSP. We need some flexibility, hence move those platform-specific config to chipset directory. Right now we still use hardcoded 'const struct' table (in flash) to pass the Azalia (Intel HD Audio) verb table to FSP, because different FSP may use different verb table format (at least for Queensbay and BayTrail), we cannot handle this in the common FSP support codes. But with this series, we are now able to get Azalia verb table from device tree, just like what we did for overriding UPD data configuration. This can be done in future patch set. Changes in v2: - Include a common struct fsp_cfg_common in the struct fsp_config_data. - New patch to introduce CONFIG_FSP_USE_UPD Kconfig option - split this patch from v1 patch#7 Bin Meng (9): x86: fsp: Simplify fsp_continue() x86: fsp: Avoid cast stack_top in struct shared_data x86: fsp: Add boot_mode as a member of struct shared_data x86: fsp: Rename shared_data to fsp_config_data x86: fsp: Rename update_fsp_upd() and change its signature x86: fsp: Introduce CONFIG_FSP_USE_UPD Kconfig option x86: queensbay: Remove invalid comments in update_fsp_configs() x86: fsp: Move struct fspinit_rtbuf definition to chipset header x86: fsp: Set up init runtime buffer in update_fsp_configs() arch/x86/Kconfig | 9 ++++ arch/x86/cpu/baytrail/fsp_configs.c | 11 +++- arch/x86/cpu/queensbay/fsp_configs.c | 14 +++--- .../include/asm/arch-baytrail/fsp/fsp_configs.h | 19 +++++++ .../include/asm/arch-queensbay/fsp/fsp_configs.h | 19 +++++++ arch/x86/include/asm/fsp/fsp_api.h | 12 ++++- arch/x86/include/asm/fsp/fsp_platform.h | 15 ------ arch/x86/include/asm/fsp/fsp_support.h | 20 +++----- arch/x86/lib/fsp/fsp_support.c | 58 ++++++++-------------- 9 files changed, 102 insertions(+), 75 deletions(-) create mode 100644 arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h delete mode 100644 arch/x86/include/asm/fsp/fsp_platform.h -- 1.8.2.1

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[U-Boot] [PATCH] spi: sf: add support for throughput mesurement of sf read/write
by Mugunthan V N 21 Dec '15

21 Dec '15

This patch adds time measurement and throughput calculation for sf read/write commands. The output of sf read changes from ---8<--- SF: 4096 bytes @ 0x0 Read: OK --->8--- to ---8<--- SF: 4096 bytes @ 0x0 Read: OK in 6 ms (666 KiB/s) --->8--- Signed-off-by: Mugunthan V N <mugunthanvnm(a)ti.com> --- common/cmd_sf.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/common/cmd_sf.c b/common/cmd_sf.c index ac7f5df..8687f3a 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -15,6 +15,7 @@ #include <spi_flash.h> #include <jffs2/jffs2.h> #include <linux/mtd/mtd.h> +#include <linux/math64.h> #include <asm/io.h> #include <dm/device-internal.h> @@ -266,6 +267,7 @@ static int do_spi_flash_read_write(int argc, char * const argv[]) int ret = 1; int dev = 0; loff_t offset, len, maxsize; + unsigned long time; if (argc < 3) return -1; @@ -298,17 +300,27 @@ static int do_spi_flash_read_write(int argc, char * const argv[]) int read; read = strncmp(argv[0], "read", 4) == 0; + + time = get_timer(0); if (read) ret = spi_flash_read(flash, offset, len, buf); else ret = spi_flash_write(flash, offset, len, buf); + time = get_timer(time); printf("SF: %zu bytes @ %#x %s: ", (size_t)len, (u32)offset, read ? "Read" : "Written"); - if (ret) + if (ret) { printf("ERROR %d\n", ret); - else - printf("OK\n"); + } else { + printf("OK in %lu ms", time); + if (time > 0) { + puts(" ("); + print_size(div_u64(len, time) * 1000, "/s"); + puts(")"); + } + puts("\n"); + } } unmap_physmem(buf, len); -- 2.6.2.280.g74301d6

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[U-Boot] [PATCH v1 01/18] MIPS: Prepare device-tree support.
by Purna Chandra Mandal 21 Dec '15

21 Dec '15

Signed-off-by: Purna Chandra Mandal <purna.mandal(a)microchip.com> --- arch/Kconfig | 1 + arch/mips/config.mk | 3 +++ arch/mips/dts/.gitignore | 1 + arch/mips/dts/Makefile | 16 ++++++++++++++++ arch/mips/dts/include/dt-bindings | 1 + arch/mips/dts/skeleton.dtsi | 21 +++++++++++++++++++++ dts/Makefile | 2 +- 7 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/.gitignore create mode 100644 arch/mips/dts/Makefile create mode 120000 arch/mips/dts/include/dt-bindings create mode 100644 arch/mips/dts/skeleton.dtsi diff --git a/arch/Kconfig b/arch/Kconfig index 6489cc9..589fc47 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -54,6 +54,7 @@ config MIPS select HAVE_PRIVATE_LIBGCC select HAVE_GENERIC_BOARD select SYS_GENERIC_BOARD + select SUPPORT_OF_CONTROL config NDS32 bool "NDS32 architecture" diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 52e28f2..d4d688e 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -70,3 +70,6 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections -pie OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn -j .padding +ifdef CONFIG_OF_EMBED +OBJCOPYFLAGS += -j .dtb.init.rodata +endif diff --git a/arch/mips/dts/.gitignore b/arch/mips/dts/.gitignore new file mode 100644 index 0000000..b60ed20 --- /dev/null +++ b/arch/mips/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile new file mode 100644 index 0000000..724b5d2 --- /dev/null +++ b/arch/mips/dts/Makefile @@ -0,0 +1,16 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +#dtb-$(CONFIG_XXX) += xxx.dtb + +targets += $(dtb-y) + +# Add any required device tree compiler flags here +DTC_FLAGS += + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/mips/dts/include/dt-bindings b/arch/mips/dts/include/dt-bindings new file mode 120000 index 0000000..0cecb3d --- /dev/null +++ b/arch/mips/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../include/dt-bindings \ No newline at end of file diff --git a/arch/mips/dts/skeleton.dtsi b/arch/mips/dts/skeleton.dtsi new file mode 100644 index 0000000..ad41546 --- /dev/null +++ b/arch/mips/dts/skeleton.dtsi @@ -0,0 +1,21 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + + chosen { + }; + + aliases { + }; + + memory { + device_type = "memory"; + reg = <0 0>; + }; +}; diff --git a/dts/Makefile b/dts/Makefile index d3122aa..5c3a01f 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -45,4 +45,4 @@ dtbs: $(obj)/dt.dtb clean-files := dt.dtb.S # Let clean descend into dts directories -subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts ../arch/x86/dts +subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts ../arch/x86/dts ../arch/mips/dts -- 1.8.3.1

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