December 2015 - U-Boot

[U-Boot] [PULL] u-boot-socfpga/master
by Marek Vasut 27 Dec '15

27 Dec '15

The following changes since commit 3721208fa7fdb2af6ac13300d5d81433742c6ba1: x86: Remove Graeme Russ from the git alias file (2015-12-21 09:37:46 -0500) are available in the git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to f464a631426a30ffcbf2d7f732e678df1b684be8: arm: socfpga: Fix USB doesn't work on socdk board (2015-12-23 04:04:46 +0100) ---------------------------------------------------------------- Chin Liang See (24): arm: socfpga: Consolidate SDMMC environment arm: socfpga: cyclone5_socdk: Consolidate SDMMC environment arm: socfpga: arria5_socdk: Consolidate SDMMC environment arm: socfpga: de0_nano_soc: Consolidate SDMMC environment arm: socfpga: mcvevk: Consolidate SDMMC environment arm: socfpga: sockit: Consolidate SDMMC environment arm: socfpga: socrates: Consolidate SDMMC environment arm: socfpga: Enabling MTD default partitions arm: socfpga: Enable ubi and ubifs support arm: socfpga: cyclone5: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS arm: socfpga: arria5: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS arm: socfpga: sr1500: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS arm: socfpga: cyclone5_socdk: Enable ubiload console command arm: socfpga: arria5_socdk: Enable ubiload console command arm: socfpga: sockit: Enable ubiload console command arm: socfpga: sr1500: Enable ubiload console command arm: socfpga: cyclone5_socdk: Enable qspiload console command arm: socfpga: arria5_socdk: Enable qspiload console command arm: socfpga: sockit: Enable qspiload console command arm: socfpga: sr1500: Enable qspiload console command arm: socfpga: cyclone5_socdk: Update qspiboot to use UBIFS arm: socfpga: arria5_socdk: Update qspiboot to use UBIFS arm: socfpga: sockit: Update qspiboot to use UBIFS arm: socfpga: sr1500: Update qspiboot to use UBIFS Marek Vasut (11): arm: socfpga: Actually enable L2 cache net: designware: Zap CONFIG_DW_AUTONEG net: designware: Zap trailing backslash arm: socfpga: Make /soc available in pre-reloc arm: socfpga: Enable simple bus in SPL on all boards arm: socfpga: Define NAND reset bit arm: socfpga: Unreset NAND in SPL arm: socfpga: Unreset NAND in U-Boot arm: socfpga: Enable SPL MMC/SPI support only if DM_MMC/SPI is enabled arm: socfpga: Enable DFU MMC support only if DM_MMC is enabled arm: socfpga: Add support for Denali NAND controller Thomas Chou (1): net: eth_designware: select PHYLIB in Kconfig shengjiangwu (3): arm: socfpga: Fix emac1 doesn't work on socdk board arm: socfpga: Fix QSPI doesn't work on socdk board arm: socfpga: Fix USB doesn't work on socdk board arch/arm/dts/socfpga_cyclone5_socdk.dts | 4 ++++ arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 ++- arch/arm/mach-socfpga/misc.c | 17 +++++++++++++++-- arch/arm/mach-socfpga/spl.c | 1 + board/altera/cyclone5-socdk/qts/pinmux_config.h | 64 ++++++++++++++++++++++++++++++++-------------------------------- board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++-- board/spear/spear600/spear600.c | 3 --- configs/socfpga_arria5_defconfig | 2 ++ configs/socfpga_cyclone5_defconfig | 2 ++ configs/socfpga_sr1500_defconfig | 1 + drivers/net/Kconfig | 1 + drivers/net/designware.c | 18 +++++++----------- include/configs/axs101.h | 6 ------ include/configs/bf609-ezkit.h | 1 - include/configs/galileo.h | 1 - include/configs/socfpga_arria5_socdk.h | 12 ++++++------ include/configs/socfpga_common.h | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- include/configs/socfpga_cyclone5_socdk.h | 12 ++++++------ include/configs/socfpga_de0_nano_soc.h | 2 -- include/configs/socfpga_mcvevk.h | 2 -- include/configs/socfpga_sockit.h | 9 +++++++-- include/configs/socfpga_socrates.h | 2 -- include/configs/socfpga_sr1500.h | 10 ++++++---- include/configs/spear-common.h | 1 - include/configs/stv0991.h | 1 - include/configs/sunxi-common.h | 2 -- include/configs/tb100.h | 1 - include/configs/x600.h | 1 - 28 files changed, 161 insertions(+), 91 deletions(-)

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[U-Boot] pull request: u-boot-uniphier/master
by Masahiro Yamada 27 Dec '15

27 Dec '15

Hi Tom, Here are various cleanups and preparation for new SoCs support. Please pull! The following changes since commit f84c2b665b87fc6713a756d0fddf5c45e02255e5: Prepare v2016.01-rc3 (2015-12-21 21:07:04 -0500) are available in the git repository at: git://git.denx.de/u-boot-uniphier.git master for you to fetch changes up to 8182b41994f0b1824c31652d64171ffa596517fc: ARM: dts: uniphier: add SD/MMC pinmux nodes (2015-12-23 00:09:05 +0900) ---------------------------------------------------------------- Masahiro Yamada (22): ARM: uniphier: add static qualifiers to locally used functions ARM: uniphier: add const qualifier to constant array ARM: uniphier: rename DTCR_RNKEN_* register bit to DTCR_RANKEN_* ARM: uniphier: use BIT() macro for DDR PHY header ARM: uniphier: allow DDR function to return more precise error code ARM: dts: uniphier: factor out common nodes to uniphier-common32.dtsi ARM: dts: uniphier: add outer cache nodes ARM: dts: uniphier: use stdout-path instead of console ARM: uniphier: add functions to get SoC model/revision ARM: uniphier: call uniphier_get_board_param() without FDT blob ARM: uniphier: split ProXstream2 board data and change DDR frequency ARM: uniphier: compile uniphier_get_board_param() for U-Boot proper ARM: uniphier: add macros and revision IDs for sLD11 and LD10 ARM: uniphier: display model number all the time on boot up ARM: uniphier: merge umc/ and ddrphy/ into a single directory ARM: uniphier: set DTB file name to fdt_file environment ARM: uniphier: drop fdt_file from CONFIG_EXTRA_ENV_SETTINGS ARM: uniphier: merge ph1_ld4_defconfig and ph1_sld8_defconfig ARM: uniphier: support ProXstream2, PH1-LD6b boards in single defconfig ARM: uniphier: rename rest of defconfig files ARM: uniphier: allow to run zImage rather than uImage ARM: dts: uniphier: add SD/MMC pinmux nodes MAINTAINERS | 2 +- arch/arm/dts/uniphier-common32.dtsi | 105 ++++++++++++++ arch/arm/dts/uniphier-ph1-ld4-ref.dts | 3 +- arch/arm/dts/uniphier-ph1-ld4.dtsi | 269 +++++++++++++--------------------- arch/arm/dts/uniphier-ph1-ld6b-ref.dts | 3 +- arch/arm/dts/uniphier-ph1-pro4-ref.dts | 3 +- arch/arm/dts/uniphier-ph1-pro4.dtsi | 327 +++++++++++++++++------------------------- arch/arm/dts/uniphier-ph1-pro5-4kbox.dts | 3 +- arch/arm/dts/uniphier-ph1-pro5.dtsi | 294 ++++++++++++++++--------------------- arch/arm/dts/uniphier-ph1-sld3-ref.dts | 3 +- arch/arm/dts/uniphier-ph1-sld8-ref.dts | 3 +- arch/arm/dts/uniphier-ph1-sld8.dtsi | 269 +++++++++++++--------------------- arch/arm/dts/uniphier-pinctrl.dtsi | 15 ++ arch/arm/dts/uniphier-proxstream2-gentil.dts | 3 +- arch/arm/dts/uniphier-proxstream2-vodka.dts | 3 +- arch/arm/dts/uniphier-proxstream2.dtsi | 308 ++++++++++++++++----------------------- arch/arm/mach-uniphier/Makefile | 4 +- arch/arm/mach-uniphier/board_late_init.c | 35 +++++ arch/arm/mach-uniphier/boards.c | 27 +++- arch/arm/mach-uniphier/cmd_ddrphy.c | 12 +- arch/arm/mach-uniphier/cpu_info.c | 9 +- arch/arm/mach-uniphier/ddrphy/Makefile | 7 - arch/arm/mach-uniphier/dram/Makefile | 10 ++ arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-ld4.c | 0 arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-pro4.c | 0 arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-sld8.c | 0 arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-training.c | 11 +- arch/arm/mach-uniphier/{umc => dram}/umc-ph1-ld4.c | 0 arch/arm/mach-uniphier/{umc => dram}/umc-ph1-pro4.c | 0 arch/arm/mach-uniphier/{umc => dram}/umc-ph1-sld8.c | 0 arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 95 ++++++------ arch/arm/mach-uniphier/include/mach/init.h | 2 +- arch/arm/mach-uniphier/include/mach/soc_info.h | 15 +- arch/arm/mach-uniphier/init/init.c | 4 +- arch/arm/mach-uniphier/soc_info.c | 22 +++ arch/arm/mach-uniphier/umc/Makefile | 7 - configs/ph1_sld8_defconfig | 30 ---- configs/{ph1_ld4_defconfig => uniphier_ld4_sld8_defconfig} | 1 + configs/{ph1_pro4_defconfig => uniphier_pro4_defconfig} | 0 configs/{ph1_pro5_defconfig => uniphier_pro5_defconfig} | 0 configs/{ph1_ld6b_defconfig => uniphier_pxs2_ld6b_defconfig} | 3 +- configs/{ph1_sld3_defconfig => uniphier_sld3_defconfig} | 0 doc/README.uniphier | 36 ++--- include/configs/uniphier.h | 12 +- 44 files changed, 919 insertions(+), 1036 deletions(-) create mode 100644 arch/arm/dts/uniphier-common32.dtsi delete mode 100644 arch/arm/mach-uniphier/ddrphy/Makefile create mode 100644 arch/arm/mach-uniphier/dram/Makefile rename arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-ld4.c (100%) rename arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-pro4.c (100%) rename arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-sld8.c (100%) rename arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-training.c (92%) rename arch/arm/mach-uniphier/{umc => dram}/umc-ph1-ld4.c (100%) rename arch/arm/mach-uniphier/{umc => dram}/umc-ph1-pro4.c (100%) rename arch/arm/mach-uniphier/{umc => dram}/umc-ph1-sld8.c (100%) delete mode 100644 arch/arm/mach-uniphier/umc/Makefile delete mode 100644 configs/ph1_sld8_defconfig rename configs/{ph1_ld4_defconfig => uniphier_ld4_sld8_defconfig} (95%) rename configs/{ph1_pro4_defconfig => uniphier_pro4_defconfig} (100%) rename configs/{ph1_pro5_defconfig => uniphier_pro5_defconfig} (100%) rename configs/{ph1_ld6b_defconfig => uniphier_pxs2_ld6b_defconfig} (88%) rename configs/{ph1_sld3_defconfig => uniphier_sld3_defconfig} (100%) -- Best Regards Masahiro Yamada

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[U-Boot] [PATCH v4 4/8] mips: ath79: add serial driver for ar933x SOC
by Wills Wang 27 Dec '15

27 Dec '15

Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/serial/Makefile | 1 + drivers/serial/serial_ar933x.c | 225 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 226 insertions(+) create mode 100644 drivers/serial/serial_ar933x.c diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dd87147..9a7ad89 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o +obj-$(CONFIG_AR933X_SERIAL) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_EFI_APP) += serial_efi.o diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c new file mode 100644 index 0000000..efca93c --- /dev/null +++ b/drivers/serial/serial_ar933x.c @@ -0,0 +1,225 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <serial.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/div64.h> +#include <asm/types.h> +#include <asm/arch/ar71xx_regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define AR933X_UART_DATA_REG 0x00 +#define AR933X_UART_CS_REG 0x04 +#define AR933X_UART_CLK_REG 0x08 + +#define AR933X_UART_DATA_TX_RX_MASK 0xff +#define AR933X_UART_DATA_RX_CSR BIT(8) +#define AR933X_UART_DATA_TX_CSR BIT(9) +#define AR933X_UART_CS_IF_MODE_S 2 +#define AR933X_UART_CS_IF_MODE_M 0x3 +#define AR933X_UART_CS_IF_MODE_DTE 1 +#define AR933X_UART_CS_IF_MODE_DCE 2 +#define AR933X_UART_CS_TX_RDY_ORIDE BIT(7) +#define AR933X_UART_CS_RX_RDY_ORIDE BIT(8) +#define AR933X_UART_CLK_STEP_M 0xffff +#define AR933X_UART_CLK_SCALE_M 0xfff +#define AR933X_UART_CLK_SCALE_S 16 +#define AR933X_UART_CLK_STEP_S 0 + +struct ar933x_serial_platdata { + void __iomem *regs; +}; + +struct ar933x_serial_priv { + void __iomem *regs; +}; + +static inline u32 ar933x_serial_read(struct udevice *dev, u32 offset) +{ + struct ar933x_serial_priv *priv = dev_get_priv(dev); + return readl(priv->regs + offset); +} + +static inline void ar933x_serial_write(struct udevice *dev, + u32 val, u32 offset) +{ + struct ar933x_serial_priv *priv = dev_get_priv(dev); + writel(val, priv->regs + offset); +} + +/* + * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17)) + */ +static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step) +{ + u64 t; + u32 div; + + div = (2 << 16) * (scale + 1); + t = clk; + t *= step; + t += (div / 2); + do_div(t, div); + + return t; +} + +static void ar933x_serial_get_scale_step(u32 clk, u32 baud, + u32 *scale, u32 *step) +{ + u32 tscale, baudrate; + long min_diff; + + *scale = 0; + *step = 0; + + min_diff = baud; + for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++) { + u64 tstep; + int diff; + + tstep = baud * (tscale + 1); + tstep *= (2 << 16); + do_div(tstep, clk); + + if (tstep > AR933X_UART_CLK_STEP_M) + break; + + baudrate = ar933x_serial_get_baud(clk, tscale, tstep); + diff = abs(baudrate - baud); + if (diff < min_diff) { + min_diff = diff; + *scale = tscale; + *step = tstep; + } + } +} + +static int ar933x_serial_setbrg(struct udevice *dev, int baudrate) +{ + u32 val, scale, step; + + val = get_serial_clock(); + ar933x_serial_get_scale_step(val, baudrate, &scale, &step); + + val = (scale & AR933X_UART_CLK_SCALE_M) + << AR933X_UART_CLK_SCALE_S; + val |= (step & AR933X_UART_CLK_STEP_M) + << AR933X_UART_CLK_STEP_S; + ar933x_serial_write(dev, val, AR933X_UART_CLK_REG); + + return 0; +} + +static int ar933x_serial_putc(struct udevice *dev, const char c) +{ + u32 data; + + if (c == '\n') + ar933x_serial_putc(dev, '\r'); + + do { + data = ar933x_serial_read(dev, AR933X_UART_DATA_REG); + } while (!(data & AR933X_UART_DATA_TX_CSR)); + + data = (u32)c | AR933X_UART_DATA_TX_CSR; + ar933x_serial_write(dev, data, AR933X_UART_DATA_REG); + + return 0; +} + +static int ar933x_serial_getc(struct udevice *dev) +{ + u32 data; + + do { + data = ar933x_serial_read(dev, AR933X_UART_DATA_REG); + } while (!(data & AR933X_UART_DATA_RX_CSR)); + + data = ar933x_serial_read(dev, AR933X_UART_DATA_REG); + ar933x_serial_write(dev, AR933X_UART_DATA_RX_CSR, + AR933X_UART_DATA_REG); + return data & AR933X_UART_DATA_TX_RX_MASK; +} + +static int ar933x_serial_pending(struct udevice *dev, bool input) +{ + u32 data; + + data = ar933x_serial_read(dev, AR933X_UART_DATA_REG); + if (input) + return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0; + else + return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1; +} + +static int ar933x_serial_probe(struct udevice *dev) +{ + struct ar933x_serial_priv *priv = dev_get_priv(dev); + struct ar933x_serial_platdata *plat = dev_get_platdata(dev); + u32 val; + + priv->regs = plat->regs; + + /* + * UART controller configuration: + * - no DMA + * - no interrupt + * - DCE mode + * - no flow control + * - set RX ready oride + * - set TX ready oride + */ + val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) | + AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE; + ar933x_serial_write(dev, val, AR933X_UART_CS_REG); + return 0; +} + +static int ar933x_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ar933x_serial_platdata *plat = dev_get_platdata(dev); + fdt_addr_t addr; + + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->regs = map_physmem(addr, + AR933X_UART_SIZE, + MAP_NOCACHE); + return 0; +} + +static const struct dm_serial_ops ar933x_serial_ops = { + .putc = ar933x_serial_putc, + .pending = ar933x_serial_pending, + .getc = ar933x_serial_getc, + .setbrg = ar933x_serial_setbrg, +}; + +static const struct udevice_id ar933x_serial_ids[] = { + { .compatible = "ath79,ar933x-uart" }, + { } +}; + +U_BOOT_DRIVER(serial_ar933x) = { + .name = "serial_ar933x", + .id = UCLASS_SERIAL, + .of_match = ar933x_serial_ids, + .ofdata_to_platdata = ar933x_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ar933x_serial_platdata), + .priv_auto_alloc_size = sizeof(struct ar933x_serial_priv), + .probe = ar933x_serial_probe, + .ops = &ar933x_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- 1.9.1

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[U-Boot] [PATCH] sunxi: Remove Orangepi PC RAM speed to 624 MHz
by Hans de Goede 27 Dec '15

27 Dec '15

There are some reports of stability issues at 672 MHz, see: http://linux-sunxi.org/Orange_Pi_PC#DRAM_clock_speed_limit So reduce the DRAM speed to 624MHz which seems to be reliable everywhere. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- configs/orangepi_pc_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 75afca9..358caa5 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN8I_H3=y -CONFIG_DRAM_CLK=672 +CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881979 CONFIG_DRAM_ODT_EN=y # CONFIG_VIDEO is not set -- 2.5.0

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[U-Boot] [PATCH v4 3/8] mips: add base support for atheros ath79 based SOCs
by Wills Wang 27 Dec '15

27 Dec '15

This patch enable work for ar933x SOC, tested on ar9331 board. Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v4: None Changes in v3: None Changes in v2: None arch/mips/Makefile | 1 + arch/mips/include/asm/global_data.h | 5 + arch/mips/mach-ath79/Makefile | 9 + arch/mips/mach-ath79/ar933x/Makefile | 8 + arch/mips/mach-ath79/ar933x/clk.c | 86 ++ arch/mips/mach-ath79/ar933x/cpu.c | 32 + arch/mips/mach-ath79/ar933x/ddr_tap.S | 268 ++++++ arch/mips/mach-ath79/ar933x/lowlevel_init.S | 460 +++++++++ arch/mips/mach-ath79/cpu.c | 171 ++++ arch/mips/mach-ath79/dram.c | 27 + arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1144 +++++++++++++++++++++++ arch/mips/mach-ath79/include/mach/ath79.h | 143 +++ arch/mips/mach-ath79/include/mach/ddr.h | 13 + arch/mips/mach-ath79/reset.c | 46 + 14 files changed, 2413 insertions(+) create mode 100644 arch/mips/mach-ath79/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/clk.c create mode 100644 arch/mips/mach-ath79/ar933x/cpu.c create mode 100644 arch/mips/mach-ath79/ar933x/ddr_tap.S create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S create mode 100644 arch/mips/mach-ath79/cpu.c create mode 100644 arch/mips/mach-ath79/dram.c create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h create mode 100644 arch/mips/mach-ath79/reset.c diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 6a9f798..da5fa72 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ machine-$(CONFIG_SOC_AU1X00) += au1x00 +machine-$(CONFIG_ARCH_ATH79) += ath79 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 2d9a0c9..8cbc298 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -20,6 +20,11 @@ struct arch_global_data { unsigned long tbl; unsigned long lastinc; #endif +#ifdef CONFIG_ARCH_ATH79 + unsigned long soc; + unsigned long rev; + unsigned long id; +#endif }; #include <asm-generic/global_data.h> diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile new file mode 100644 index 0000000..bc0a41f --- /dev/null +++ b/arch/mips/mach-ath79/Makefile @@ -0,0 +1,9 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o +obj-y += cpu.o +obj-y += dram.o + +obj-$(CONFIG_SOC_AR933X) += ar933x/ diff --git a/arch/mips/mach-ath79/ar933x/Makefile b/arch/mips/mach-ath79/ar933x/Makefile new file mode 100644 index 0000000..22107d5 --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += clk.o +obj-y += lowlevel_init.o +obj-y += ddr_tap.o diff --git a/arch/mips/mach-ath79/ar933x/clk.c b/arch/mips/mach-ath79/ar933x/clk.c new file mode 100644 index 0000000..3e130c7 --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/clk.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ar71xx_regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +static u32 ar933x_get_xtal(void) +{ + u32 val; + + val = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR933X_RESET_REG_BOOTSTRAP)); + if (val & AR933X_BOOTSTRAP_REF_CLK_40) + return 40000000; + else + return 25000000; +} + +int get_serial_clock(void) +{ + return ar933x_get_xtal(); +} + +int get_clocks(void) +{ + u32 val, xtal, pll, div; + + xtal = ar933x_get_xtal(); + val = readl(KSEG1ADDR(AR71XX_PLL_BASE + AR933X_PLL_CPU_CONFIG_REG)); + + /* VCOOUT = XTAL * DIV_INT */ + div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) + & AR933X_PLL_CPU_CONFIG_REFDIV_MASK; + pll = xtal / div; + + /* PLLOUT = VCOOUT * (1/2^OUTDIV) */ + div = (val >> AR933X_PLL_CPU_CONFIG_DIVINT_SHIFT) + & AR933X_PLL_CPU_CONFIG_DIVINT_MASK; + pll *= div; + div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) + & AR933X_PLL_CPU_CONFIG_OUTDIV_MASK; + if (!div) + div = 1; + pll >>= div; + + val = readl(KSEG1ADDR(AR71XX_PLL_BASE + AR933X_PLL_CLOCK_CTRL_REG)); + + /* CPU_CLK = PLLOUT / CPU_POST_DIV */ + div = ((val >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) + & AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; + gd->cpu_clk = pll / div; + + /* DDR_CLK = PLLOUT / DDR_POST_DIV */ + div = ((val >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) + & AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; + gd->mem_clk = pll / div; + + /* AHB_CLK = PLLOUT / AHB_POST_DIV */ + div = ((val >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) + & AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; + gd->bus_clk = pll / div; + + return 0; +} + +ulong get_bus_freq(ulong dummy) +{ + if (!gd->bus_clk) + get_clocks(); + return gd->bus_clk; +} + +ulong get_ddr_freq(ulong dummy) +{ + if (!gd->mem_clk) + get_clocks(); + return gd->mem_clk; +} diff --git a/arch/mips/mach-ath79/ar933x/cpu.c b/arch/mips/mach-ath79/ar933x/cpu.c new file mode 100644 index 0000000..e734dac --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/cpu.c @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ar71xx_regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +int arch_cpu_init(void) +{ + u32 val; + + /* + * Set GPIO10 (UART_SO) as output and enable UART, + * BIT(15) in GPIO_FUNCTION_1 register must be written with 1 + */ + val = readl(KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_OE)); + val |= BIT(10); + writel(val, KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_OE)); + + val = readl(KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_FUNC)); + val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15)); + writel(val, KSEG1ADDR(AR71XX_GPIO_BASE + AR71XX_GPIO_REG_FUNC)); + return 0; +} diff --git a/arch/mips/mach-ath79/ar933x/ddr_tap.S b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644 index 0000000..18c57de --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/ddr_tap.S @@ -0,0 +1,268 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/arch/ar71xx_regs.h> + +#define DRAM_K0(x) KSEG0ADDR(x) +#define DRAM_K1(x) KSEG1ADDR(x) + + .text + .set noreorder + +LEAF(ddr_tap_init) + /* Tap settings for the DDR */ + li t0, 0xffffffff + li t1, DRAM_K0(0x500000) + sw t0, 0x0(t1) + sw t0, 0x4(t1) + sw t0, 0x8(t1) + sw t0, 0xc(t1) + nop + nop + + li t8, DRAM_K1(0x2000) + li t0, 0x00 + li t1, 0x100 +0: + andi t2, t0, 0x03 + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0x0(t8) + b 2f + nop +1: + li t3, 0x01 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0x0(t8) + b 2f + nop +1: + li t3, 0x02 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0x0(t8) + b 2f + nop +1: + li t3, 0x03 + bne t2, t3,2f + nop + li t9, 0xffffffff + sw t9, 0x0(t8) +2: + andi t2, t0, 0x0c + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0x4(t8) + b 2f + nop +1: + li t3, 0x04 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0x4(t8) + b 2f + nop +1: + li t3, 0x08 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0x4(t8) + b 2f + nop +1: + li t3, 0x0c + bne t2, t3,2f + li t9, 0xffffffff + sw t9, 0x4(t8) +2: + andi t2, t0, 0x30 + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0x8(t8) + b 2f + nop +1: + li t3, 0x10 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0x8(t8) + b 2f + nop +1: + li t3, 0x20 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0x8(t8) + b 2f + nop +1: + li t3, 0x30 + bne t2, t3,2f + nop + li t9, 0xffffffff + sw t9, 0x8(t8) +2: + andi t2, t0, 0xc0 + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0xc(t8) + b 2f + nop +1: + li t3, 0x40 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0xc(t8) + b 2f + nop +1: + li t3, 0x80 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0xc(t8) + b 2f + nop +1: + li t3, 0xc0 + bne t2, t3,2f + nop + li t9, 0xffffffff + sw t9, 0xc(t8) +2: + addiu t0, t0, 0x1 + addiu t8, t8, 0x10 + bne t0, t1, 0b + nop + + li a0, DRAM_K1(0x2000) # Start address + li a1, DRAM_K0(0x2000) # Start address of the pattern 200 + li a2, DRAM_K0(0x3000) # End Address of the pattern 220 + li t0, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + lw a3, AR71XX_DDR_REG_TAP_CTRL0(t0) + nop # loading default tap value + ori t0, a3, 0x0 + + /* $t1=1 indicates increasing tap value, 0 = decreasing */ + li t1, 0x1 +0: + li t7, 0x2 + li t8, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + sw t0, AR71XX_DDR_REG_TAP_CTRL0(t8) + nop + sw t0, AR71XX_DDR_REG_TAP_CTRL1(t8) + nop + + /* t0 stores current tap setting under test + t1 indicates increment or decrement of tap */ +1: + ori t2, a0, 0x0 + ori t3, a1, 0x0 + ori t4, a2, 0x0 +2: + lw t5, 0x0(t2) # upper and lower limit detection + lw t6, 0x0(t3) + bne t5, t6, 3f + nop + addiu t2, t2, 0x4 + addiu t3, t3, 0x4 + bne t3, t4, 2b + nop + addiu t7, t7, -1 + bnez t7, 1b + nop + + bnez t1, 2f # increment tap if t1 = 1 + nop + bnez t0, 1f # tap=0 works so low limit=0, + nop # else decrement tap value + + li t8, DRAM_K0(0x500000) # assigning lower limit = 0 + sw t0, 0x0(t8) + nop + add t9, t9, t0 # adding lower limit to upper limit + b 4f # used to calc mid value + nop +1: + addiu t0, t0 , -1 # decrement and loading this new tap + b 0b + nop +2: + addiu t0, t0, 0x1 + xori v1, t0, 0x20 # limiting upper limit to 0x20 + bnez v1, 0b + nop + b 1f + nop +3: + bnez t1, 1f # t1=1 fail for upper limit + nop # t1=0 fail for lower limit + addiu t0, t0, 0x1 + nop + li t8, DRAM_K0(0x500000) # storing lower limit + sw t0, 0x0(t8) + nop + add t9, t9, t0 # adding lower limit and upper limit + b 4f + nop +1: + addiu t0, t0, -1 + li t1, 0x0 # changing to decreasing tap mode + li t8, DRAM_K0(0x500000) # storing upper limit + sw t0, 0x4(t8) + nop + ori t9, t0, 0x0 + ori t0, a3, 0x0 # loading default tap value + b 0b + nop + + /* calculating mid value of the tap, storing DQS0, DQS1 in + 0x80500008, 0x8050000c resp */ +4: + li t7, 0x2 + div t9, t7 + nop + mfhi t6 + mflo t5 + add t6, t6, t5 + li t8, DRAM_K0(0x500000) + sw t5, 0x8(t8) + nop + sw t6, 0xc(t8) + nop + li t8, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + sw t5, AR71XX_DDR_REG_TAP_CTRL0(t8) + nop + sw t6, AR71XX_DDR_REG_TAP_CTRL1(t8) + nop + + nop + jr ra + nop + END(ddr_tap_init) diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 index 0000000..72509ca --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S @@ -0,0 +1,460 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/arch/ar71xx_regs.h> + +#define SET_BIT(val, bit) ((val) | (1 << (bit))) +#define SET_PLL_PD(val) SET_BIT(val, 30) +#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16) +#define PLL_BYPASS(val) SET_BIT(val, 2) + +#define MK_PLL_CONF(divint, refdiv, range, outdiv) \ + (((0x3F & divint) << 10) | \ + ((0x1F & refdiv) << 16) | \ + ((0x1 & range) << 21) | \ + ((0x7 & outdiv) << 23) ) + +#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ + (((0x3 & (cpudiv - 1)) << 5) | \ + ((0x3 & (ddrdiv - 1)) << 10) | \ + ((0x3 & (ahbdiv - 1)) << 15) ) + +/* + * PLL_CPU_CONFIG_VAL + * + * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL) + * After PLL configuration we need to clear this bit + * + * Values written into CPU PLL Configuration (CPU_PLL_CONFIG) + * + * bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL) + * => 32 (0x20) VCOOUT = XTAL * DIV_INT + * bits 16..20 (5bit) REFDIV (Reference clock divider) + * => 1 (0x1) [Must start at values 1] + * bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL) + * => 0 (0x0) [Doesn't impact clock values] + * bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output) + * => 1 (0x1) [0 is illegal!] + * PLLOUT = VCOOUT * (1/2^OUTDIV) + */ +/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ +#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1) +/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ +#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1) + +/* + * PLL_CLK_CONTROL_VAL + * + * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL) + * After PLL configuration we need to clear this bit + * + * Values written into CPU Clock Control Register CLOCK_CONTROL + * + * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test. + * Software must enable the CPU PLL for normal and + * then set this bit to 0) + * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1) + * CPU_CLK = PLLOUT / CPU_POST_DIV + * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1) + * DDR_CLK = PLLOUT / DDR_POST_DIV + * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2) + * AHB_CLK = PLLOUT / AHB_POST_DIV + * + */ +#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2) + + .text + .set noreorder + +LEAF(lowlevel_init) + /* These three WLAN_RESET will avoid original issue */ + li t3, 0x03 +1: + li t0, KSEG1ADDR(AR71XX_RESET_BASE) + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) + ori t1, t1, 0x0800 + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) + nop + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) + li t2, 0xfffff7ff + and t1, t1, t2 + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) + nop + addi t3, t3, -1 + bnez t3, 1b + nop + + li t2, 0x20 +2: + beqz t2, 1b + nop + addi t2, t2, -1 + lw t5, AR933X_RESET_REG_BOOTSTRAP(t0) + andi t1, t5, 0x10 + bnez t1, 2b + nop + + li t1, 0x02110E + sw t1, AR933X_RESET_REG_BOOTSTRAP(t0) + nop + + /* RTC Force Wake */ + li t0, KSEG1ADDR(AR933X_RTC_BASE) + li t1, 0x03 + sw t1, AR933X_RTC_REG_FORCE_WAKE(t0) + nop + nop + + /* RTC Reset */ + li t1, 0x00 + sw t1, AR933X_RTC_REG_RESET(t0) + nop + nop + + li t1, 0x01 + sw t1, AR933X_RTC_REG_RESET(t0) + nop + nop + + /* Wait for RTC in on state */ +1: + lw t1, AR933X_RTC_REG_STATUS(t0) + andi t1, t1, 0x02 + beqz t1, 1b + nop + + /* Program ki/kd */ + li t0, KSEG1ADDR(AR933X_SRIF_BASE) + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x19e82f01 + b 2f + nop +1: + li t1, 0x18e82f01 +2: + sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0) + + /* Program phase shift */ + lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + li t2, 0xc07fffff + and t1, t1, t2 + li t2, 0x800000 # meas_at_txon + or t1, t1, t2 + sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + nop + + /* Max AHB Master wait time out ... */ + li t0, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + li t1, 0xfffff + sw t1, AR933X_DDR_REG_TIMEOUT_MAX(t0) + nop + + /* in some cases, the SoC doesn't start with higher clock on AHB */ + li t0, KSEG1ADDR(AR71XX_PLL_BASE) + li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL)) + sw t1, AR933X_PLL_CLOCK_CTRL_REG(t0) + nop + + /* Set SETTLE_TIME in CPU PLL */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x0352 + b 2f + nop +1: + li t1, 0x0550 +2: + sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0) + nop + + /* Set nint, frac, refdiv, outdiv, range according to xtal */ +0: + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M) + b 2f + nop +1: + li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M) +2: + sw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + nop +1: + lw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + li t2, 0x80000000 + and t1, t1, t2 + bnez t1, 1b + nop + + /* Put frac bit19:10 configuration */ + li t1, 0x1003E8 + sw t1, AR71XX_PLL_REG_ETH0_INT_CLOCK(t0) + nop + + /* Clear PLL power down bit in CPU PLL configuration */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, PLL_CPU_CONFIG_VAL_25M + b 2f + nop +1: + li t1, PLL_CPU_CONFIG_VAL_40M +2: + sw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + nop + + /* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */ +1: + lw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + li t2, 0x80000000 + and t1, t1, t2 + bnez t1, 1b + nop + + /* Confirm DDR PLL lock */ + li t3, 100 + li t4, 0 + +2: + addi t4, t4, 1 + bgt t4, t3, 0b + nop + + li t3, 5 +3: + /* Clear do_meas */ + li t0, KSEG1ADDR(AR933X_SRIF_BASE) + lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + li t2, 0xBFFFFFFF + and t1, t1, t2 + sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + nop + + li t2, 10 +1: + subu t2, t2, 1 + bnez t2, 1b + nop + + /* Set do_meas */ + li t2, 0x40000000 + or t1, t1, t2 + sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + nop + + /* Check meas_done */ +1: + lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0) + andi t1, t1, 0x8 + beqz t1, 1b + nop + + lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + li t2, 0x007FFFF8 + and t1, t1, t2 + srl t1, t1, 3 + li t2, 0x4000 + bgt t1, t2, 2b + nop + addi t3, t3, -1 + bnez t3, 3b + nop + + /* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */ + li t0, KSEG1ADDR(AR71XX_PLL_BASE) + li t1, PLL_CLK_CONTROL_VAL + sw t1, AR933X_PLL_CLOCK_CTRL_REG(t0) + nop + + li t0, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + li t1, 0x7fbc8cd0 + sw t1, AR71XX_DDR_REG_CONFIG(t0) + + li t1, 0x9dd0e6a8 + sw t1, AR71XX_DDR_REG_CONFIG2(t0) + + andi t1, t5, 0x2000 # t5 BOOT_STRAP + beqz t1, 3f + nop + + /* Enable DDR2 */ + li t1, 0xA59 + sw t1, AR933X_DDR_REG_DDR2_CONFIG(t0) + + /* Precharge All */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Disable High Temperature Self-Refresh Rate */ + li t1, 0x00 + sw t1, AR933X_DDR_REG_EMR2(t0) + + /* Extended Mode Register 2 Set (EMR2S) */ + li t1, 0x10 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + li t1, 0x00 + sw t1, AR933X_DDR_REG_EMR3(t0) + + /* Extended Mode Register 3 Set (EMR3S) */ + li t1, 0x20 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Enable DLL */ + li t1, 0x00 + sw t1, AR71XX_DDR_REG_EMR(t0) + + /* Extended Mode Register Set (EMRS) */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Reset DLL */ + li t1, 0x100 + sw t1, AR71XX_DDR_REG_MODE(t0) + + /* Mode Register Set (MRS) */ + li t1, 0x01 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Precharge All */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Auto Refresh */ + li t1, 0x04 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Auto Refresh */ + li t1, 0x04 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */ + li t1, 0xa33 + sw t1, AR71XX_DDR_REG_MODE(t0) + + /* Mode Register Set (MRS) */ + li t1, 0x01 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* E7,E8,E9 equal to 1(Enable OCD defaults), Enable DLL, + Reduced Drive Strength */ + li t1, 0x382 + sw t1, AR71XX_DDR_REG_EMR(t0) + + /* Extended Mode Register Set (EMRS) */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* E7,E8,E9 equal to 0(OCD exit), Enable DLL, + Reduced Drive Strength */ + li t1, 0x402 + sw t1, AR71XX_DDR_REG_EMR(t0) + + /* Extended Mode Register Set (EMRS) */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x4186 + b 2f + nop +1: + li t1, 0x4270 +2: + sw t1, AR71XX_DDR_REG_REFRESH(t0) + + /* DQS 0 Tap Control (needs tuning) */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_TAP_CTRL0(t0) + + /* DQS 1 Tap Control (needs tuning) */ + li t1, 0x09 + sw t1, AR71XX_DDR_REG_TAP_CTRL1(t0) + + /* For 16-bit DDR */ + li t1, 0xff + sw t1, AR71XX_DDR_REG_RD_CYCLE(t0) + nop + b 4f + nop + + /* DDR1 config */ +3: + /* Precharge All */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Write Mode Word */ + li t1, 0x133 + sw t1, AR71XX_DDR_REG_MODE(t0) + + /* Forces an MRS update cycle in DDR */ + li t1, 0x01 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Enable DLL, High drive strength from DDR */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_EMR(t0) + + /* Write Extended Mode Word of DDR */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Precharge All */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* DLL out of reset, CAS Latency 3 */ + li t1, 0x33 + sw t1, AR71XX_DDR_REG_MODE(t0) + + /* Write mode word */ + li t1, 0x01 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x4270 + b 2f + nop +1: + li t1, 0x4186 +2: + sw t1, AR71XX_DDR_REG_REFRESH(t0) + + /* DQS 0 Tap Control (needs tuning) */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_TAP_CTRL0(t0) + + /* DQS 1 Tap Control (needs tuning) */ + li t1, 0x09 + sw t1, AR71XX_DDR_REG_TAP_CTRL1(t0) + + /* For 16-bit DDR */ + li t1, 0xff + sw t1, AR71XX_DDR_REG_RD_CYCLE(t0) + +4: + nop + jr ra + nop + END(lowlevel_init) diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c new file mode 100644 index 0000000..681127c --- /dev/null +++ b/arch/mips/mach-ath79/cpu.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ath79.h> +#include <asm/arch/ar71xx_regs.h> + +int print_cpuinfo(void) +{ + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; + char *chip = "????"; + u32 id, major, minor; + u32 rev = 0; + u32 ver = 1; + + id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID)); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; + rev &= AR71XX_REV_ID_REVISION_MASK; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + soc = ATH79_SOC_AR7130; + chip = "7130"; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + soc = ATH79_SOC_AR7141; + chip = "7141"; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + soc = ATH79_SOC_AR7161; + chip = "7161"; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + soc = ATH79_SOC_AR7240; + chip = "7240"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR7241: + soc = ATH79_SOC_AR7241; + chip = "7241"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR7242: + soc = ATH79_SOC_AR7242; + chip = "7242"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + rev = id >> AR913X_REV_ID_REVISION_SHIFT; + rev &= AR913X_REV_ID_REVISION_MASK; + switch (minor) { + case AR913X_REV_ID_MINOR_AR9130: + soc = ATH79_SOC_AR9130; + chip = "9130"; + break; + + case AR913X_REV_ID_MINOR_AR9132: + soc = ATH79_SOC_AR9132; + chip = "9132"; + break; + } + break; + + case REV_ID_MAJOR_AR9330: + soc = ATH79_SOC_AR9330; + chip = "9330"; + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9331: + soc = ATH79_SOC_AR9331; + chip = "9331"; + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9341: + soc = ATH79_SOC_AR9341; + chip = "9341"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9342: + soc = ATH79_SOC_AR9342; + chip = "9342"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9344: + soc = ATH79_SOC_AR9344; + chip = "9344"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9533_V2: + ver = 2; + /* drop through */ + + case REV_ID_MAJOR_QCA9533: + soc = ATH79_SOC_QCA9533; + chip = "9533"; + rev = id & QCA953X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9556: + soc = ATH79_SOC_QCA9556; + chip = "9556"; + rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9558: + soc = ATH79_SOC_QCA9558; + chip = "9558"; + rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_TP9343: + soc = ATH79_SOC_TP9343; + chip = "9343"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9561: + soc = ATH79_SOC_QCA9561; + chip = "9561"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + } + + gd->arch.soc = soc; + gd->arch.rev = rev; + gd->arch.id = id; + puts("SoC: "); + switch (soc) { + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA9561: + printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip, + ver, rev); + break; + case ATH79_SOC_TP9343: + printf("Qualcomm Atheros TP%s rev %u\n", chip, rev); + break; + case ATH79_SOC_UNKNOWN: + printf("ATH79: unknown SoC, id:0x%08x", id); + default: + printf("Atheros AR%s rev %u\n", chip, rev); + } + + return 0; +} diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c new file mode 100644 index 0000000..42539dc --- /dev/null +++ b/arch/mips/mach-ath79/dram.c @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/addrspace.h> +#include <asm/arch/ddr.h> + +phys_size_t initdram(int board_type) +{ + uint8_t *addr, *p; + int i; + + ddr_tap_init(); + addr = (uint8_t *)KSEG1; + *addr = 0x77; + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) { + p += 0x1000000; + *p = i; + if (*addr != 0x77) + break; + } + return (phys_size_t)(p - addr); +} diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file mode 100644 index 0000000..994aeef --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -0,0 +1,1144 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2015 Wills Wang, <wills.wang(a)live.com> + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan(a)atheros.com> + * Copyright (C) 2008-2010 Gabor Juhos <juhosg(a)openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz(a)openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT(nr) (1UL << (nr)) +#endif +#endif + +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x100 + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) +#define AR933X_RTC_SIZE 0x1000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 +#define AR933X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR933X_SRIF_SIZE 0x1000 + +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 +#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 +#define AR934X_NFC_BASE 0x1b000200 +#define AR934X_NFC_SIZE 0xb8 +#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR934X_SRIF_SIZE 0x1000 + +#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA953X_GMAC_SIZE 0x14 +#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA953X_WMAC_SIZE 0x20000 +#define QCA953X_EHCI_BASE 0x1b000000 +#define QCA953X_EHCI_SIZE 0x200 +#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define QCA953X_SRIF_SIZE 0x1000 + +#define QCA953X_PCI_CFG_BASE0 0x14000000 +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA953X_PCI_MEM_BASE0 0x10000000 +#define QCA953X_PCI_MEM_SIZE 0x02000000 + +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_NFC_BASE 0x1b800200 +#define QCA955X_NFC_SIZE 0xb8 + +#define QCA956X_PCI_MEM_BASE1 0x12000000 +#define QCA956X_PCI_MEM_SIZE 0x02000000 +#define QCA956X_PCI_CFG_BASE1 0x16000000 +#define QCA956X_PCI_CFG_SIZE 0x1000 +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA956X_PCI_CRP_SIZE 0x1000 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA956X_PCI_CTRL_SIZE 0x100 + +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA956X_WMAC_SIZE 0x20000 +#define QCA956X_EHCI0_BASE 0x1b000000 +#define QCA956X_EHCI1_BASE 0x1b400000 +#define QCA956X_EHCI_SIZE 0x200 +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA956X_GMAC_SIZE 0x64 + +#define AR9300_OTP_BASE 0x14000 +#define AR9300_OTP_STATUS 0x15f18 +#define AR9300_OTP_STATUS_TYPE 0x7 +#define AR9300_OTP_STATUS_VALID 0x4 +#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 +#define AR9300_OTP_STATUS_SM_BUSY 0x1 +#define AR9300_OTP_READ_DATA 0x15f1c + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_CONFIG 0x00 +#define AR71XX_DDR_REG_CONFIG2 0x04 +#define AR71XX_DDR_REG_MODE 0x08 +#define AR71XX_DDR_REG_EMR 0x0c +#define AR71XX_DDR_REG_CONTROL 0x10 +#define AR71XX_DDR_REG_REFRESH 0x14 +#define AR71XX_DDR_REG_RD_CYCLE 0x18 +#define AR71XX_DDR_REG_TAP_CTRL0 0x1c +#define AR71XX_DDR_REG_TAP_CTRL1 0x20 + +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 +#define AR933X_DDR_REG_DDR2_CONFIG 0x8c +#define AR933X_DDR_REG_EMR2 0x90 +#define AR933X_DDR_REG_EMR3 0x94 +#define AR933X_DDR_REG_BURST 0x98 +#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c +#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c +#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c + +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac + +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 +#define QCA953X_DDR_REG_FLUSH_USB 0xa4 +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +#define AR913X_ETH0_PLL_SHIFT 20 +#define AR913X_ETH1_PLL_SHIFT 22 + +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +#define AR933X_PLL_CPU_CONFIG_DIVINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_DIVINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) + +#define QCA953X_PLL_CPU_CONFIG_REG 0x00 +#define QCA953X_PLL_DDR_CONFIG_REG 0x04 +#define QCA953X_PLL_CLK_CTRL_REG 0x08 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48 + +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA956X_PLL_CPU_CONFIG_REG 0x00 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c +#define QCA956X_PLL_CLK_CTRL_REG 0x10 + +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +/* + * USB_CONFIG block + */ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA953X_RESET_REG_RESET_MODULE 0x1c +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA955X_RESET_REG_RESET_MODULE 0x1c +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +#define QCA956X_RESET_REG_RESET_MODULE 0x1c +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac + +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) + +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR934X_RESET_HOST BIT(31) +#define AR934X_RESET_SLIC BIT(30) +#define AR934X_RESET_HDMA BIT(29) +#define AR934X_RESET_EXTERNAL BIT(28) +#define AR934X_RESET_RTC BIT(27) +#define AR934X_RESET_PCIE_EP_INT BIT(26) +#define AR934X_RESET_CHKSUM_ACC BIT(25) +#define AR934X_RESET_FULL_CHIP BIT(24) +#define AR934X_RESET_GE1_MDIO BIT(23) +#define AR934X_RESET_GE0_MDIO BIT(22) +#define AR934X_RESET_CPU_NMI BIT(21) +#define AR934X_RESET_CPU_COLD BIT(20) +#define AR934X_RESET_HOST_RESET_INT BIT(19) +#define AR934X_RESET_PCIE_EP BIT(18) +#define AR934X_RESET_UART1 BIT(17) +#define AR934X_RESET_DDR BIT(16) +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define AR934X_RESET_NANDF BIT(14) +#define AR934X_RESET_GE1_MAC BIT(13) +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_HOST_DMA_INT BIT(10) +#define AR934X_RESET_GE0_MAC BIT(9) +#define AR934X_RESET_ETH_SWITCH BIT(8) +#define AR934X_RESET_PCIE_PHY BIT(7) +#define AR934X_RESET_PCIE BIT(6) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) + +#define QCA953X_RESET_USB_EXT_PWR BIT(29) +#define QCA953X_RESET_EXTERNAL BIT(28) +#define QCA953X_RESET_RTC BIT(27) +#define QCA953X_RESET_FULL_CHIP BIT(24) +#define QCA953X_RESET_GE1_MDIO BIT(23) +#define QCA953X_RESET_GE0_MDIO BIT(22) +#define QCA953X_RESET_CPU_NMI BIT(21) +#define QCA953X_RESET_CPU_COLD BIT(20) +#define QCA953X_RESET_DDR BIT(16) +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA953X_RESET_GE1_MAC BIT(13) +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA953X_RESET_GE0_MAC BIT(9) +#define QCA953X_RESET_ETH_SWITCH BIT(8) +#define QCA953X_RESET_PCIE_PHY BIT(7) +#define QCA953X_RESET_PCIE BIT(6) +#define QCA953X_RESET_USB_HOST BIT(5) +#define QCA953X_RESET_USB_PHY BIT(4) +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) + +#define QCA955X_RESET_HOST BIT(31) +#define QCA955X_RESET_SLIC BIT(30) +#define QCA955X_RESET_HDMA BIT(29) +#define QCA955X_RESET_EXTERNAL BIT(28) +#define QCA955X_RESET_RTC BIT(27) +#define QCA955X_RESET_PCIE_EP_INT BIT(26) +#define QCA955X_RESET_CHKSUM_ACC BIT(25) +#define QCA955X_RESET_FULL_CHIP BIT(24) +#define QCA955X_RESET_GE1_MDIO BIT(23) +#define QCA955X_RESET_GE0_MDIO BIT(22) +#define QCA955X_RESET_CPU_NMI BIT(21) +#define QCA955X_RESET_CPU_COLD BIT(20) +#define QCA955X_RESET_HOST_RESET_INT BIT(19) +#define QCA955X_RESET_PCIE_EP BIT(18) +#define QCA955X_RESET_UART1 BIT(17) +#define QCA955X_RESET_DDR BIT(16) +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA955X_RESET_NANDF BIT(14) +#define QCA955X_RESET_GE1_MAC BIT(13) +#define QCA955X_RESET_SGMII_ANALOG BIT(12) +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA955X_RESET_HOST_DMA_INT BIT(10) +#define QCA955X_RESET_GE0_MAC BIT(9) +#define QCA955X_RESET_SGMII BIT(8) +#define QCA955X_RESET_PCIE_PHY BIT(7) +#define QCA955X_RESET_PCIE BIT(6) +#define QCA955X_RESET_USB_HOST BIT(5) +#define QCA955X_RESET_USB_PHY BIT(4) +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) +#define QCA955X_RESET_LUT BIT(2) +#define QCA955X_RESET_MBOX BIT(1) +#define QCA955X_RESET_I2S BIT(0) + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define QCA953X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) + +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) + +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ + (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ + QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) + +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ + (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ + QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ + QCA953X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + +#define QCA956X_EXT_INT_WMAC_MISC BIT(0) +#define QCA956X_EXT_INT_WMAC_TX BIT(1) +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA956X_EXT_INT_USB1 BIT(24) +#define QCA956X_EXT_INT_USB2 BIT(28) + +#define QCA956X_EXT_INT_WMAC_ALL \ + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) + +#define QCA956X_EXT_INT_PCIE_RC1_ALL \ + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ + QCA956X_EXT_INT_PCIE_RC1_INT3) + +#define QCA956X_EXT_INT_PCIE_RC2_ALL \ + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ + QCA956X_EXT_INT_PCIE_RC2_INT3) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9533 0x0140 +#define REV_ID_MAJOR_QCA9533_V2 0x0160 +#define REV_ID_MAJOR_QCA9556 0x0130 +#define REV_ID_MAJOR_QCA9558 0x1130 +#define REV_ID_MAJOR_TP9343 0x0150 +#define REV_ID_MAJOR_QCA9561 0x1150 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR913X_REV_ID_MINOR_MASK 0x3 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 +#define AR913X_REV_ID_REVISION_MASK 0x3 +#define AR913X_REV_ID_REVISION_SHIFT 2 + +#define AR933X_REV_ID_REVISION_MASK 0x3 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +#define AR934X_REV_ID_REVISION_MASK 0xf + +#define QCA953X_REV_ID_REVISION_MASK 0xf + +#define QCA955X_REV_ID_REVISION_MASK 0xf + +#define QCA956X_REV_ID_REVISION_MASK 0xf + +/* + * RTC block + */ +#define AR933X_RTC_REG_RESET 0x40 +#define AR933X_RTC_REG_STATUS 0x44 +#define AR933X_RTC_REG_DERIVED 0x48 +#define AR933X_RTC_REG_FORCE_WAKE 0x4c +#define AR933X_RTC_REG_INT_CAUSE 0x50 +#define AR933X_RTC_REG_CAUSE_CLR 0x50 +#define AR933X_RTC_REG_INT_ENABLE 0x54 +#define AR933X_RTC_REG_INT_MASKE 0x58 + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ + AR71XX_SPI_IOC_CS2) + +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 +#define AR933X_GPIO_REG_FUNC 0x30 + +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 +#define AR934X_GPIO_REG_FUNC 0x6c + +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA953X_GPIO_REG_FUNC 0x6c + +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA955X_GPIO_REG_FUNC 0x6c + +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 +#define QCA956X_GPIO_REG_FUNC 0x6c + +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 + +#define AR71XX_GPIO_COUNT 16 +#define AR7240_GPIO_COUNT 18 +#define AR7241_GPIO_COUNT 20 +#define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 +#define QCA953X_GPIO_COUNT 18 +#define QCA955X_GPIO_COUNT 24 +#define QCA956X_GPIO_COUNT 23 + +/* + * SRIF block + */ +#define AR933X_SRIF_DDR_DPLL1_REG 0x240 +#define AR933X_SRIF_DDR_DPLL2_REG 0x244 +#define AR933X_SRIF_DDR_DPLL3_REG 0x248 +#define AR933X_SRIF_DDR_DPLL4_REG 0x24c + +#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 +#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 +#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define AR934X_SRIF_DDR_DPLL1_REG 0x240 +#define AR934X_SRIF_DDR_DPLL2_REG 0x244 +#define AR934X_SRIF_DDR_DPLL3_REG 0x248 + +#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 +#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff +#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 + +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 + +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR913X_GPIO_FUNC_UART_EN BIT(8) +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) + +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR933X_GPIO_FUNC_XLNA_EN BIT(12) + +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) + +#define AR934X_GPIO_OUT_GPIO 0 +#define AR934X_GPIO_OUT_SPI_CS1 7 +#define AR934X_GPIO_OUT_LED_LINK0 41 +#define AR934X_GPIO_OUT_LED_LINK1 42 +#define AR934X_GPIO_OUT_LED_LINK2 43 +#define AR934X_GPIO_OUT_LED_LINK3 44 +#define AR934X_GPIO_OUT_LED_LINK4 45 +#define AR934X_GPIO_OUT_EXT_LNA0 46 +#define AR934X_GPIO_OUT_EXT_LNA1 47 + +#define QCA955X_GPIO_OUT_GPIO 0 + +/* + * MII_CTRL block + */ +#define AR71XX_MII_REG_MII0_CTRL 0x00 +#define AR71XX_MII_REG_MII1_CTRL 0x04 + +#define AR71XX_MII_CTRL_IF_MASK 3 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 +#define AR71XX_MII_CTRL_SPEED_MASK 3 +#define AR71XX_MII_CTRL_SPEED_10 0 +#define AR71XX_MII_CTRL_SPEED_100 1 +#define AR71XX_MII_CTRL_SPEED_1000 2 + +#define AR71XX_MII0_CTRL_IF_GMII 0 +#define AR71XX_MII0_CTRL_IF_MII 1 +#define AR71XX_MII0_CTRL_IF_RGMII 2 +#define AR71XX_MII0_CTRL_IF_RMII 3 + +#define AR71XX_MII1_CTRL_IF_RGMII 0 +#define AR71XX_MII1_CTRL_IF_RMII 1 + +/* + * AR933X GMAC interface + */ +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) + +/* + * AR934X GMAC Interface + */ +#define AR934X_GMAC_REG_ETH_CFG 0x00 + +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) +#define AR934X_ETH_CFG_RXD_DELAY BIT(14) +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 +#define AR934X_ETH_CFG_RDV_DELAY BIT(16) +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 + +/* + * QCA953X GMAC Interface + */ +#define QCA953X_GMAC_REG_ETH_CFG 0x00 + +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + +/* + * QCA955X GMAC Interface + */ + +#define QCA955X_GMAC_REG_ETH_CFG 0x00 + +#define QCA955X_ETH_CFG_RGMII_EN BIT(0) +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) + +#endif /* __ASM_AR71XX_H */ diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h new file mode 100644 index 0000000..58c8224 --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ath79.h @@ -0,0 +1,143 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2015 Wills Wang, <wills.wang(a)live.com> + * Copyright (C) 2008-2011 Gabor Juhos <juhosg(a)openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz(a)openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_ATH79_H +#define __ASM_MACH_ATH79_H + +#include <linux/types.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum ath79_soc_type { + ATH79_SOC_UNKNOWN, + ATH79_SOC_AR7130, + ATH79_SOC_AR7141, + ATH79_SOC_AR7161, + ATH79_SOC_AR7240, + ATH79_SOC_AR7241, + ATH79_SOC_AR7242, + ATH79_SOC_AR9130, + ATH79_SOC_AR9132, + ATH79_SOC_AR9330, + ATH79_SOC_AR9331, + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, + ATH79_SOC_QCA9533, + ATH79_SOC_QCA9556, + ATH79_SOC_QCA9558, + ATH79_SOC_TP9343, + ATH79_SOC_QCA9561, +}; + +static inline int soc_is_ar71xx(void) +{ + return gd->arch.soc == ATH79_SOC_AR7130 || + gd->arch.soc == ATH79_SOC_AR7141 || + gd->arch.soc == ATH79_SOC_AR7161; +} + +static inline int soc_is_ar724x(void) +{ + return gd->arch.soc == ATH79_SOC_AR7240 || + gd->arch.soc == ATH79_SOC_AR7241 || + gd->arch.soc == ATH79_SOC_AR7242; +} + +static inline int soc_is_ar7240(void) +{ + return gd->arch.soc == ATH79_SOC_AR7240; +} + +static inline int soc_is_ar7241(void) +{ + return gd->arch.soc == ATH79_SOC_AR7241; +} + +static inline int soc_is_ar7242(void) +{ + return gd->arch.soc == ATH79_SOC_AR7242; +} + +static inline int soc_is_ar913x(void) +{ + return gd->arch.soc == ATH79_SOC_AR9130 || + gd->arch.soc == ATH79_SOC_AR9132; +} + +static inline int soc_is_ar933x(void) +{ + return gd->arch.soc == ATH79_SOC_AR9330 || + gd->arch.soc == ATH79_SOC_AR9331; +} + +static inline int soc_is_ar9341(void) +{ + return gd->arch.soc == ATH79_SOC_AR9341; +} + +static inline int soc_is_ar9342(void) +{ + return gd->arch.soc == ATH79_SOC_AR9342; +} + +static inline int soc_is_ar9344(void) +{ + return gd->arch.soc == ATH79_SOC_AR9344; +} + +static inline int soc_is_ar934x(void) +{ + return soc_is_ar9341() || + soc_is_ar9342() || + soc_is_ar9344(); +} + +static inline int soc_is_qca9533(void) +{ + return gd->arch.soc == ATH79_SOC_QCA9533; +} + +static inline int soc_is_qca953x(void) +{ + return soc_is_qca9533(); +} + +static inline int soc_is_qca9556(void) +{ + return gd->arch.soc == ATH79_SOC_QCA9556; +} + +static inline int soc_is_qca9558(void) +{ + return gd->arch.soc == ATH79_SOC_QCA9558; +} + +static inline int soc_is_qca955x(void) +{ + return soc_is_qca9556() || soc_is_qca9558(); +} + +static inline int soc_is_tp9343(void) +{ + return gd->arch.soc == ATH79_SOC_TP9343; +} + +static inline int soc_is_qca9561(void) +{ + return gd->arch.soc == ATH79_SOC_QCA9561; +} + +static inline int soc_is_qca956x(void) +{ + return soc_is_tp9343() || soc_is_qca9561(); +} + +#endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/mach-ath79/include/mach/ddr.h b/arch/mips/mach-ath79/include/mach/ddr.h new file mode 100644 index 0000000..e90c9a1 --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ddr.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_DDR_H +#define __ASM_MACH_DDR_H + +void ddr_tap_init(void); + +#endif /* __ASM_MACH_DDR_H */ diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c new file mode 100644 index 0000000..5322df3 --- /dev/null +++ b/arch/mips/mach-ath79/reset.c @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ath79.h> +#include <asm/arch/ar71xx_regs.h> + +void _machine_restart(void) +{ + u32 val, reg = 0; + + if (soc_is_ar71xx()) + reg = AR71XX_RESET_REG_RESET_MODULE; + else if (soc_is_ar724x()) + reg = AR724X_RESET_REG_RESET_MODULE; + else if (soc_is_ar913x()) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x()) + reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_RESET_MODULE; + else if (soc_is_qca953x()) + reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; + else if (soc_is_qca956x()) + reg = QCA956X_RESET_REG_RESET_MODULE; + else + puts("Reset register not defined for this SOC\n"); + + if (reg) { + val = readl(KSEG1ADDR(AR71XX_RESET_BASE + reg)); + val |= AR71XX_RESET_FULL_CHIP; + writel(val, KSEG1ADDR(AR71XX_RESET_BASE + reg)); + } + + while (1) + /* NOP */; +} -- 1.9.1

3 5

[U-Boot] [PATCH v4 6/8] mips: ath79: add AP121 reference board
by Wills Wang 27 Dec '15

27 Dec '15

Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v4: None Changes in v3: None Changes in v2: None arch/mips/Kconfig | 8 +++++ arch/mips/dts/Makefile | 2 +- arch/mips/dts/ap121.dts | 37 +++++++++++++++++++ arch/mips/dts/ar933x.dtsi | 64 +++++++++++++++++++++++++++++++++ board/ath79/ap121/Kconfig | 15 ++++++++ board/ath79/ap121/MAINTAINERS | 6 ++++ board/ath79/ap121/Makefile | 8 +++++ board/ath79/ap121/README | 18 ++++++++++ board/ath79/ap121/ap121.c | 17 +++++++++ board/ath79/ap121/config.mk | 16 +++++++++ configs/ap121_defconfig | 42 ++++++++++++++++++++++ include/configs/ap121.h | 82 +++++++++++++++++++++++++++++++++++++++++++ 12 files changed, 314 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/ap121.dts create mode 100644 arch/mips/dts/ar933x.dtsi create mode 100644 board/ath79/ap121/Kconfig create mode 100644 board/ath79/ap121/MAINTAINERS create mode 100644 board/ath79/ap121/Makefile create mode 100644 board/ath79/ap121/README create mode 100644 board/ath79/ap121/ap121.c create mode 100644 board/ath79/ap121/config.mk create mode 100644 configs/ap121_defconfig create mode 100644 include/configs/ap121.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7f7e258..09b8709 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -51,6 +51,13 @@ config TARGET_PB1X00 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD +config TARGET_AP121 + bool "Support ap121" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SYS_MIPS_CACHE_INIT_RAM_LOAD + endchoice @@ -59,6 +66,7 @@ source "board/imgtec/malta/Kconfig" source "board/micronas/vct/Kconfig" source "board/pb1x00/Kconfig" source "board/qemu-mips/Kconfig" +source "board/ath79/ap121/Kconfig" if MIPS diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 47b6eb5..6f8b413 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -dtb-y += +dtb-$(CONFIG_TARGET_AP121) += ap121.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts new file mode 100644 index 0000000..769458a --- /dev/null +++ b/arch/mips/dts/ap121.dts @@ -0,0 +1,37 @@ +/dts-v1/; +#include "ar933x.dtsi" + +/ { + model = "AP121 Reference Board"; + compatible = "ath79,ap121", "ath79,ar933x"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&xtal { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + spi-max-frequency = <25000000>; + status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + memory-map = <0x9f000000 0x00800000>; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi new file mode 100644 index 0000000..64b30f7 --- /dev/null +++ b/arch/mips/dts/ar933x.dtsi @@ -0,0 +1,64 @@ +#include "skeleton.dtsi" + +/ { + compatible = "ath79,ar933x"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24Kc"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xtal"; + }; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@18020000 { + compatible = "ath79,ar933x-uart"; + reg = <0x18020000 0x20>; + + status = "disabled"; + }; + }; + + spi0: spi@1f000000 { + compatible = "ath79,ath79-spi"; + reg = <0x1f000000 0x10>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/board/ath79/ap121/Kconfig b/board/ath79/ap121/Kconfig new file mode 100644 index 0000000..88d9eff --- /dev/null +++ b/board/ath79/ap121/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AP121 + +config SYS_BOARD + default "ap121" + +config SYS_VENDOR + default "ath79" + +config SYS_SOC + default "ath79" + +config SYS_CONFIG_NAME + default "ap121" + +endif diff --git a/board/ath79/ap121/MAINTAINERS b/board/ath79/ap121/MAINTAINERS new file mode 100644 index 0000000..319b521 --- /dev/null +++ b/board/ath79/ap121/MAINTAINERS @@ -0,0 +1,6 @@ +AP121 BOARD +M: Wills Wang <wills.wang(a)live.com> +S: Maintained +F: board/ath79/ap121/ +F: include/configs/ap121.h +F: configs/ap121_defconfig diff --git a/board/ath79/ap121/Makefile b/board/ath79/ap121/Makefile new file mode 100644 index 0000000..9132118 --- /dev/null +++ b/board/ath79/ap121/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ap121.o diff --git a/board/ath79/ap121/README b/board/ath79/ap121/README new file mode 100644 index 0000000..104850f --- /dev/null +++ b/board/ath79/ap121/README @@ -0,0 +1,18 @@ +ATHEROS AP121 +================== + +Supported hardware: AP121 referance board. + +Files of the AP121 port +-------------------------- + +arch/mips/mach-ath79/ar933x/ - The CPU support code for the Atheros ar933x +arch/mips/include/asm/arch-ath79 - Header files for the Atheros ath79 +board/ath79/ap121/ - AP121 board specific files +include/configs/ap121.h - AP121 configuration file + +Configure +------------------- + +To configure for the current board + make ap121_defconfig diff --git a/board/ath79/ap121/ap121.c b/board/ath79/ap121/ap121.c new file mode 100644 index 0000000..f60f88b --- /dev/null +++ b/board/ath79/ap121/ap121.c @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/io.h> + +int checkboard(void) +{ + return 0; +} diff --git a/board/ath79/ap121/config.mk b/board/ath79/ap121/config.mk new file mode 100644 index 0000000..f7dd3b7 --- /dev/null +++ b/board/ath79/ap121/config.mk @@ -0,0 +1,16 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# +# AP121 referance board, MIPS32 core +# + +# ROM version +CONFIG_SYS_TEXT_BASE = 0x9f000000 + +# RAM version +#CONFIG_SYS_TEXT_BASE = 0x80010000 diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig new file mode 100644 index 0000000..cec0bb7 --- /dev/null +++ b/configs/ap121_defconfig @@ -0,0 +1,42 @@ +CONFIG_MIPS=y +CONFIG_TARGET_AP121=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_PROMPT="ap121 # " +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="ap121" +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ATH79_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_USE_4K_SECTORS=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_CMD_DM=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_NET is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_NET is not set +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/ap121.h b/include/configs/ap121.h new file mode 100644 index 0000000..5a01d11 --- /dev/null +++ b/include/configs/ap121.h @@ -0,0 +1,82 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <linux/kconfig.h> +#include <linux/sizes.h> + +#define CONFIG_ARCH_ATH79 +#define CONFIG_SOC_AR933X + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_OF_LIBFDT + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 200 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 32 * SZ_1K +#define CONFIG_SYS_ICACHE_SIZE 64 * SZ_1K +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN ROUND(0x30000 + 128 * SZ_1K, 0x1000) + +#define CONFIG_SYS_BOOTPARAMS_LEN 128 * SZ_1K + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x20000 +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_AR933X_SERIAL +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock2 " \ + "rootfstype=squashfs" +#define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ + "bootm 0x9f300000" +#define CONFIG_LZMA + +#define MTDIDS_DEFAULT "nor0=spi-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:256k(u-boot)," \ + "64k(u-boot-env),2752k(rootfs),896k(uImage),64k(NVRAM),64k(ART)" + +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET (256 * SZ_1K) +#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) +#define CONFIG_ENV_SIZE (64 * SZ_1K) + +/* + * Command + */ +#define CONFIG_CMD_MTDPARTS + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Diagnostics + */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x83f00000 +#define CONFIG_CMD_MEMTEST + +#endif /* __CONFIG_H */ -- 1.9.1

3 7

[U-Boot] [PATCH v4 7/8] mips: support optimize tuning for same common processor cores
by Wills Wang 27 Dec '15

27 Dec '15

Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v4: None Changes in v3: None Changes in v2: None arch/mips/Makefile | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index da5fa72..0be5e64 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -2,6 +2,13 @@ # SPDX-License-Identifier: GPL-2.0+ # +tune-$(CONFIG_OPTIMIZE_CPU_MIPS_4KC) =-mtune=4kc +tune-$(CONFIG_OPTIMIZE_CPU_MIPS_24KC) =-mtune=24kc + +tune-y := $(tune-y) + +PLATFORM_CPPFLAGS += $(tune-y) + head-y := arch/mips/cpu/start.o libs-y += arch/mips/cpu/ -- 1.9.1

3 3

[U-Boot] [PATCH] MIPS: Kconfig: optimize gcc -march and -mtune setup
by Daniel Schwierzeck 26 Dec '15

26 Dec '15

Move setup of -march to arch/mips/Makefile and follow the design on ARM. Also add a possibility to chose specific CPU tune options. Signed-off-by: Wills Wang <wills.wang(a)live.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- arch/mips/Kconfig | 12 +++++++++++- arch/mips/Makefile | 13 +++++++++++++ arch/mips/config.mk | 6 ------ arch/mips/mach-au1x00/config.mk | 8 -------- 4 files changed, 24 insertions(+), 15 deletions(-) delete mode 100644 arch/mips/mach-au1x00/config.mk diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7f7e258..388e4c0 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -43,6 +43,7 @@ config TARGET_DBAU1X00 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD + select MIPS_TUNE_4KC config TARGET_PB1X00 bool "Support pb1x00" @@ -50,7 +51,7 @@ config TARGET_PB1X00 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD - + select MIPS_TUNE_4KC endchoice @@ -174,6 +175,15 @@ config CPU_MIPS64 bool default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 +config MIPS_TUNE_4KC + bool + +config MIPS_TUNE_14KC + bool + +config MIPS_TUNE_24KC + bool + config 32BIT bool diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 6a9f798..90cd590 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -13,3 +13,16 @@ machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) + +# Optimize for MIPS architectures +arch-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32 +arch-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2 +arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 +arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 + +# Allow extra optimization for specific CPUs/SoCs +tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc +tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc +tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc + +PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 3ebc202..bf8dd9c 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -35,12 +35,6 @@ PLATFORM_LDFLAGS += -m$(64bit-emul) OBJCOPYFLAGS += -O $(64bit-bfd) endif -cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32 -cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2 -cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 -cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 -PLATFORM_CPPFLAGS += $(cpuflags-y) - PLATFORM_CPPFLAGS += -D__MIPS__ # diff --git a/arch/mips/mach-au1x00/config.mk b/arch/mips/mach-au1x00/config.mk deleted file mode 100644 index 5c89129..0000000 --- a/arch/mips/mach-au1x00/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2011 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mtune=4kc -- 2.5.0

1 0

[U-Boot] [PATCH v4 8/8] mips: move optimize tuning option from deprecated config.mk to Kconfig
by Wills Wang 26 Dec '15

26 Dec '15

config.mk files in mach-xxx directory are deprecated, this patch move the processor tuning option of compiler into Kconfig Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v4: - Add div64 macro for MIPS - Convert physical address to uncached and cached(KSEG0/1) memory range in map_physmem - Auto calculate baudrate for serial driver - Move pinctrl code in serial driver into arch/mips/mach-ath79 - Use global_data to save CPU/DDR/AHB clock - Use get_serial_clock to serial clock source - Use get_bus_freq instead of hardcode in SPI driver - Use arch_global_data to save SOC's type, revison and id - move CPU optimize tuning flag from config.mk to Kconfig Changes in v3: - Convert serial driver to driver model - Convert spi driver to driver model - Add support for device tree - Move SoC specific header files into arch/mips/mach-ath79/include/mach - Optimize assembly code - Same code style convertion Changes in v2: - Move all SoC specific header files into arch/mips/include/asm/arch-ath79 - Check SOC type and extract common code into arch/mips/mach-ath79 - Add a compatible spi driver - Move serial driver code into drivers/serial - Add a reference board implemention arch/mips/Kconfig | 9 +++++++++ arch/mips/mach-au1x00/config.mk | 8 -------- 2 files changed, 9 insertions(+), 8 deletions(-) delete mode 100644 arch/mips/mach-au1x00/config.mk diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 09b8709..8672cc6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -43,6 +43,7 @@ config TARGET_DBAU1X00 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD + select OPTIMIZE_CPU_MIPS_4KC config TARGET_PB1X00 bool "Support pb1x00" @@ -50,6 +51,7 @@ config TARGET_PB1X00 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD + select OPTIMIZE_CPU_MIPS_4KC config TARGET_AP121 bool "Support ap121" @@ -57,6 +59,7 @@ config TARGET_AP121 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD + select OPTIMIZE_CPU_MIPS_24KC endchoice @@ -174,6 +177,12 @@ config SUPPORTS_CPU_MIPS64_R1 config SUPPORTS_CPU_MIPS64_R2 bool +config OPTIMIZE_CPU_MIPS_4KC + bool + +config OPTIMIZE_CPU_MIPS_24KC + bool + config CPU_MIPS32 bool default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 diff --git a/arch/mips/mach-au1x00/config.mk b/arch/mips/mach-au1x00/config.mk deleted file mode 100644 index 5c89129..0000000 --- a/arch/mips/mach-au1x00/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2011 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mtune=4kc -- 1.9.1

2 2

[U-Boot] [PATCH v4 5/8] mips: ath79: add spi driver
by Wills Wang 26 Dec '15

26 Dec '15

Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/spi/Kconfig | 8 ++ drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 211 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 220 insertions(+) create mode 100644 drivers/spi/ath79_spi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2cdb110..a9e1d31 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -23,6 +23,14 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ATH79_SPI + bool "Atheros SPI driver" + help + Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used + to access SPI NOR flash and other SPI peripherals. This driver + uses driver model and requires a device tree binding to + operate. + config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3eca745..7fb2926 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c new file mode 100644 index 0000000..dcce584 --- /dev/null +++ b/drivers/spi/ath79_spi.c @@ -0,0 +1,211 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spi.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ar71xx_regs.h> + +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */ +#define SPI_CLK_DIV(x) (((x) >> 1) - 1) + +struct ath79_spi_platdata { + void __iomem *regs; +}; + +struct ath79_spi_priv { + void __iomem *regs; +}; + +static inline u32 ath79_spi_read(struct udevice *bus, u32 offset) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + return readl(priv->regs + offset); +} + +static inline void ath79_spi_write(struct udevice *bus, + u32 val, u32 offset) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + writel(val, priv->regs + offset); +} + +static int ath79_spi_claim_bus(struct udevice *dev) +{ + return 0; +} + +static int ath79_spi_release_bus(struct udevice *dev) +{ + return 0; +} + +static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + uint8_t *rx = din; + const uint8_t *tx = dout; + uint8_t curbyte, curbitlen, restbits; + uint32_t bytes = bitlen / 8; + uint32_t out; + uint32_t in; + + if (flags & SPI_XFER_BEGIN) { + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC); + } + + restbits = (bitlen % 8); + if (restbits) + bytes++; + + /* enable chip select */ + out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs)); + while (bytes--) { + curbyte = 0; + if (tx) + curbyte = *tx++; + + if (restbits) { + curbitlen = restbits; + curbyte <<= 8 - restbits; + } else { + curbitlen = 8; + } + + /* clock starts at inactive polarity */ + for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) { + if (curbyte & 0x80) + out |= AR71XX_SPI_IOC_DO; + else + out &= ~(AR71XX_SPI_IOC_DO); + + /* setup MSB (to slave) on trailing edge */ + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC); + ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK, + AR71XX_SPI_REG_IOC); + curbyte <<= 1; + } + + in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS); + if (rx) { + if (restbits) + *rx++ = (in << (8 - restbits)); + else + *rx++ = in; + } + } + + if (flags & SPI_XFER_END) { + ath79_spi_write(bus, AR71XX_SPI_IOC_CS(slave->cs), + AR71XX_SPI_REG_IOC); + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + } + + return 0; +} + + +static int ath79_spi_set_speed(struct udevice *bus, uint speed) +{ + u32 val, div = 0; + + if (speed) + div = get_bus_freq(0) / speed; + + if (div > 63) + div = 63; + + if (div < 5) + div = 5; + + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + val = ath79_spi_read(bus, AR71XX_SPI_REG_CTRL); + val &= ~AR71XX_SPI_CTRL_DIV_MASK; + val |= SPI_CLK_DIV(div); + ath79_spi_write(bus, val, AR71XX_SPI_REG_CTRL); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + return 0; +} + +static int ath79_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int ath79_spi_probe(struct udevice *bus) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + struct ath79_spi_platdata *plat = dev_get_platdata(bus); + + priv->regs = plat->regs; + + /* Init SPI Hardware, disable remap, set clock */ + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + ath79_spi_write(bus, AR71XX_SPI_CTRL_RD | SPI_CLK_DIV(8), + AR71XX_SPI_REG_CTRL); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + + return 0; +} + +static int ath79_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + /* Always allow activity on CS 0/1/2 */ + if (cs >= 3) + return -ENODEV; + + return 0; +} + +static int ath79_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct ath79_spi_platdata *plat = dev_get_platdata(bus); + fdt_addr_t addr; + + addr = dev_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->regs = map_physmem(addr, + AR71XX_SPI_SIZE, + MAP_NOCACHE); + return 0; +} + +static const struct dm_spi_ops ath79_spi_ops = { + .claim_bus = ath79_spi_claim_bus, + .release_bus = ath79_spi_release_bus, + .xfer = ath79_spi_xfer, + .set_speed = ath79_spi_set_speed, + .set_mode = ath79_spi_set_mode, + .cs_info = ath79_cs_info, +}; + +static const struct udevice_id ath79_spi_ids[] = { + { .compatible = "ath79,ath79-spi" }, + {} +}; + +U_BOOT_DRIVER(ath79_spi) = { + .name = "ath79_spi", + .id = UCLASS_SPI, + .of_match = ath79_spi_ids, + .ops = &ath79_spi_ops, + .ofdata_to_platdata = ath79_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ath79_spi_platdata), + .priv_auto_alloc_size = sizeof(struct ath79_spi_priv), + .probe = ath79_spi_probe, +}; -- 1.9.1

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