December 2015 - U-Boot

[U-Boot] [PATCH v3 1/4] mips: add base support for atheros ath79 based SOCs
by Wills Wang 28 Dec '15

28 Dec '15

This patch enable work for ar933x SOC, tested on ar9331 board. Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v3: None Changes in v2: None arch/mips/Makefile | 1 + arch/mips/config.mk | 1 + arch/mips/mach-ath79/Makefile | 9 + arch/mips/mach-ath79/ar933x/Makefile | 6 + arch/mips/mach-ath79/ar933x/ddr_tap.S | 268 ++++++ arch/mips/mach-ath79/ar933x/lowlevel_init.S | 460 +++++++++ arch/mips/mach-ath79/cpu.c | 269 ++++++ arch/mips/mach-ath79/dram.c | 27 + arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1144 +++++++++++++++++++++++ arch/mips/mach-ath79/include/mach/ar933x_uart.h | 66 ++ arch/mips/mach-ath79/include/mach/ath79.h | 143 +++ arch/mips/mach-ath79/include/mach/ddr.h | 13 + arch/mips/mach-ath79/reset.c | 55 ++ 13 files changed, 2462 insertions(+) create mode 100644 arch/mips/mach-ath79/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/ddr_tap.S create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S create mode 100644 arch/mips/mach-ath79/cpu.c create mode 100644 arch/mips/mach-ath79/dram.c create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h create mode 100644 arch/mips/mach-ath79/include/mach/ar933x_uart.h create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h create mode 100644 arch/mips/mach-ath79/reset.c diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 6a9f798..da5fa72 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ machine-$(CONFIG_SOC_AU1X00) += au1x00 +machine-$(CONFIG_ARCH_ATH79) += ath79 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 3ebc202..fd50909 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -39,6 +39,7 @@ cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32 cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2 cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 +cpuflags-$(CONFIG_ARCH_ATH79) += -mtune=24kc PLATFORM_CPPFLAGS += $(cpuflags-y) PLATFORM_CPPFLAGS += -D__MIPS__ diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile new file mode 100644 index 0000000..bc0a41f --- /dev/null +++ b/arch/mips/mach-ath79/Makefile @@ -0,0 +1,9 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += reset.o +obj-y += cpu.o +obj-y += dram.o + +obj-$(CONFIG_SOC_AR933X) += ar933x/ diff --git a/arch/mips/mach-ath79/ar933x/Makefile b/arch/mips/mach-ath79/ar933x/Makefile new file mode 100644 index 0000000..0da8fd4 --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/Makefile @@ -0,0 +1,6 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += lowlevel_init.o +obj-y += ddr_tap.o diff --git a/arch/mips/mach-ath79/ar933x/ddr_tap.S b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644 index 0000000..18c57de --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/ddr_tap.S @@ -0,0 +1,268 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/arch/ar71xx_regs.h> + +#define DRAM_K0(x) KSEG0ADDR(x) +#define DRAM_K1(x) KSEG1ADDR(x) + + .text + .set noreorder + +LEAF(ddr_tap_init) + /* Tap settings for the DDR */ + li t0, 0xffffffff + li t1, DRAM_K0(0x500000) + sw t0, 0x0(t1) + sw t0, 0x4(t1) + sw t0, 0x8(t1) + sw t0, 0xc(t1) + nop + nop + + li t8, DRAM_K1(0x2000) + li t0, 0x00 + li t1, 0x100 +0: + andi t2, t0, 0x03 + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0x0(t8) + b 2f + nop +1: + li t3, 0x01 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0x0(t8) + b 2f + nop +1: + li t3, 0x02 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0x0(t8) + b 2f + nop +1: + li t3, 0x03 + bne t2, t3,2f + nop + li t9, 0xffffffff + sw t9, 0x0(t8) +2: + andi t2, t0, 0x0c + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0x4(t8) + b 2f + nop +1: + li t3, 0x04 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0x4(t8) + b 2f + nop +1: + li t3, 0x08 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0x4(t8) + b 2f + nop +1: + li t3, 0x0c + bne t2, t3,2f + li t9, 0xffffffff + sw t9, 0x4(t8) +2: + andi t2, t0, 0x30 + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0x8(t8) + b 2f + nop +1: + li t3, 0x10 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0x8(t8) + b 2f + nop +1: + li t3, 0x20 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0x8(t8) + b 2f + nop +1: + li t3, 0x30 + bne t2, t3,2f + nop + li t9, 0xffffffff + sw t9, 0x8(t8) +2: + andi t2, t0, 0xc0 + li t3, 0x00 + bne t2, t3,1f + nop + li t9, 0x00000000 + sw t9, 0xc(t8) + b 2f + nop +1: + li t3, 0x40 + bne t2, t3,1f + nop + li t9, 0x0000ffff + sw t9, 0xc(t8) + b 2f + nop +1: + li t3, 0x80 + bne t2, t3,1f + nop + li t9, 0xffff0000 + sw t9, 0xc(t8) + b 2f + nop +1: + li t3, 0xc0 + bne t2, t3,2f + nop + li t9, 0xffffffff + sw t9, 0xc(t8) +2: + addiu t0, t0, 0x1 + addiu t8, t8, 0x10 + bne t0, t1, 0b + nop + + li a0, DRAM_K1(0x2000) # Start address + li a1, DRAM_K0(0x2000) # Start address of the pattern 200 + li a2, DRAM_K0(0x3000) # End Address of the pattern 220 + li t0, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + lw a3, AR71XX_DDR_REG_TAP_CTRL0(t0) + nop # loading default tap value + ori t0, a3, 0x0 + + /* $t1=1 indicates increasing tap value, 0 = decreasing */ + li t1, 0x1 +0: + li t7, 0x2 + li t8, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + sw t0, AR71XX_DDR_REG_TAP_CTRL0(t8) + nop + sw t0, AR71XX_DDR_REG_TAP_CTRL1(t8) + nop + + /* t0 stores current tap setting under test + t1 indicates increment or decrement of tap */ +1: + ori t2, a0, 0x0 + ori t3, a1, 0x0 + ori t4, a2, 0x0 +2: + lw t5, 0x0(t2) # upper and lower limit detection + lw t6, 0x0(t3) + bne t5, t6, 3f + nop + addiu t2, t2, 0x4 + addiu t3, t3, 0x4 + bne t3, t4, 2b + nop + addiu t7, t7, -1 + bnez t7, 1b + nop + + bnez t1, 2f # increment tap if t1 = 1 + nop + bnez t0, 1f # tap=0 works so low limit=0, + nop # else decrement tap value + + li t8, DRAM_K0(0x500000) # assigning lower limit = 0 + sw t0, 0x0(t8) + nop + add t9, t9, t0 # adding lower limit to upper limit + b 4f # used to calc mid value + nop +1: + addiu t0, t0 , -1 # decrement and loading this new tap + b 0b + nop +2: + addiu t0, t0, 0x1 + xori v1, t0, 0x20 # limiting upper limit to 0x20 + bnez v1, 0b + nop + b 1f + nop +3: + bnez t1, 1f # t1=1 fail for upper limit + nop # t1=0 fail for lower limit + addiu t0, t0, 0x1 + nop + li t8, DRAM_K0(0x500000) # storing lower limit + sw t0, 0x0(t8) + nop + add t9, t9, t0 # adding lower limit and upper limit + b 4f + nop +1: + addiu t0, t0, -1 + li t1, 0x0 # changing to decreasing tap mode + li t8, DRAM_K0(0x500000) # storing upper limit + sw t0, 0x4(t8) + nop + ori t9, t0, 0x0 + ori t0, a3, 0x0 # loading default tap value + b 0b + nop + + /* calculating mid value of the tap, storing DQS0, DQS1 in + 0x80500008, 0x8050000c resp */ +4: + li t7, 0x2 + div t9, t7 + nop + mfhi t6 + mflo t5 + add t6, t6, t5 + li t8, DRAM_K0(0x500000) + sw t5, 0x8(t8) + nop + sw t6, 0xc(t8) + nop + li t8, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + sw t5, AR71XX_DDR_REG_TAP_CTRL0(t8) + nop + sw t6, AR71XX_DDR_REG_TAP_CTRL1(t8) + nop + + nop + jr ra + nop + END(ddr_tap_init) diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 index 0000000..72509ca --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S @@ -0,0 +1,460 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/arch/ar71xx_regs.h> + +#define SET_BIT(val, bit) ((val) | (1 << (bit))) +#define SET_PLL_PD(val) SET_BIT(val, 30) +#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16) +#define PLL_BYPASS(val) SET_BIT(val, 2) + +#define MK_PLL_CONF(divint, refdiv, range, outdiv) \ + (((0x3F & divint) << 10) | \ + ((0x1F & refdiv) << 16) | \ + ((0x1 & range) << 21) | \ + ((0x7 & outdiv) << 23) ) + +#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \ + (((0x3 & (cpudiv - 1)) << 5) | \ + ((0x3 & (ddrdiv - 1)) << 10) | \ + ((0x3 & (ahbdiv - 1)) << 15) ) + +/* + * PLL_CPU_CONFIG_VAL + * + * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL) + * After PLL configuration we need to clear this bit + * + * Values written into CPU PLL Configuration (CPU_PLL_CONFIG) + * + * bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL) + * => 32 (0x20) VCOOUT = XTAL * DIV_INT + * bits 16..20 (5bit) REFDIV (Reference clock divider) + * => 1 (0x1) [Must start at values 1] + * bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL) + * => 0 (0x0) [Doesn't impact clock values] + * bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output) + * => 1 (0x1) [0 is illegal!] + * PLLOUT = VCOOUT * (1/2^OUTDIV) + */ +/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ +#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1) +/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ +#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1) + +/* + * PLL_CLK_CONTROL_VAL + * + * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL) + * After PLL configuration we need to clear this bit + * + * Values written into CPU Clock Control Register CLOCK_CONTROL + * + * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test. + * Software must enable the CPU PLL for normal and + * then set this bit to 0) + * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1) + * CPU_CLK = PLLOUT / CPU_POST_DIV + * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1) + * DDR_CLK = PLLOUT / DDR_POST_DIV + * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2) + * AHB_CLK = PLLOUT / AHB_POST_DIV + * + */ +#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2) + + .text + .set noreorder + +LEAF(lowlevel_init) + /* These three WLAN_RESET will avoid original issue */ + li t3, 0x03 +1: + li t0, KSEG1ADDR(AR71XX_RESET_BASE) + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) + ori t1, t1, 0x0800 + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) + nop + lw t1, AR933X_RESET_REG_RESET_MODULE(t0) + li t2, 0xfffff7ff + and t1, t1, t2 + sw t1, AR933X_RESET_REG_RESET_MODULE(t0) + nop + addi t3, t3, -1 + bnez t3, 1b + nop + + li t2, 0x20 +2: + beqz t2, 1b + nop + addi t2, t2, -1 + lw t5, AR933X_RESET_REG_BOOTSTRAP(t0) + andi t1, t5, 0x10 + bnez t1, 2b + nop + + li t1, 0x02110E + sw t1, AR933X_RESET_REG_BOOTSTRAP(t0) + nop + + /* RTC Force Wake */ + li t0, KSEG1ADDR(AR933X_RTC_BASE) + li t1, 0x03 + sw t1, AR933X_RTC_REG_FORCE_WAKE(t0) + nop + nop + + /* RTC Reset */ + li t1, 0x00 + sw t1, AR933X_RTC_REG_RESET(t0) + nop + nop + + li t1, 0x01 + sw t1, AR933X_RTC_REG_RESET(t0) + nop + nop + + /* Wait for RTC in on state */ +1: + lw t1, AR933X_RTC_REG_STATUS(t0) + andi t1, t1, 0x02 + beqz t1, 1b + nop + + /* Program ki/kd */ + li t0, KSEG1ADDR(AR933X_SRIF_BASE) + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x19e82f01 + b 2f + nop +1: + li t1, 0x18e82f01 +2: + sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0) + + /* Program phase shift */ + lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + li t2, 0xc07fffff + and t1, t1, t2 + li t2, 0x800000 # meas_at_txon + or t1, t1, t2 + sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + nop + + /* Max AHB Master wait time out ... */ + li t0, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + li t1, 0xfffff + sw t1, AR933X_DDR_REG_TIMEOUT_MAX(t0) + nop + + /* in some cases, the SoC doesn't start with higher clock on AHB */ + li t0, KSEG1ADDR(AR71XX_PLL_BASE) + li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL)) + sw t1, AR933X_PLL_CLOCK_CTRL_REG(t0) + nop + + /* Set SETTLE_TIME in CPU PLL */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x0352 + b 2f + nop +1: + li t1, 0x0550 +2: + sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0) + nop + + /* Set nint, frac, refdiv, outdiv, range according to xtal */ +0: + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M) + b 2f + nop +1: + li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M) +2: + sw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + nop +1: + lw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + li t2, 0x80000000 + and t1, t1, t2 + bnez t1, 1b + nop + + /* Put frac bit19:10 configuration */ + li t1, 0x1003E8 + sw t1, AR71XX_PLL_REG_ETH0_INT_CLOCK(t0) + nop + + /* Clear PLL power down bit in CPU PLL configuration */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, PLL_CPU_CONFIG_VAL_25M + b 2f + nop +1: + li t1, PLL_CPU_CONFIG_VAL_40M +2: + sw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + nop + + /* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */ +1: + lw t1, AR933X_PLL_CPU_CONFIG_REG(t0) + li t2, 0x80000000 + and t1, t1, t2 + bnez t1, 1b + nop + + /* Confirm DDR PLL lock */ + li t3, 100 + li t4, 0 + +2: + addi t4, t4, 1 + bgt t4, t3, 0b + nop + + li t3, 5 +3: + /* Clear do_meas */ + li t0, KSEG1ADDR(AR933X_SRIF_BASE) + lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + li t2, 0xBFFFFFFF + and t1, t1, t2 + sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + nop + + li t2, 10 +1: + subu t2, t2, 1 + bnez t2, 1b + nop + + /* Set do_meas */ + li t2, 0x40000000 + or t1, t1, t2 + sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + nop + + /* Check meas_done */ +1: + lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0) + andi t1, t1, 0x8 + beqz t1, 1b + nop + + lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0) + li t2, 0x007FFFF8 + and t1, t1, t2 + srl t1, t1, 3 + li t2, 0x4000 + bgt t1, t2, 2b + nop + addi t3, t3, -1 + bnez t3, 3b + nop + + /* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */ + li t0, KSEG1ADDR(AR71XX_PLL_BASE) + li t1, PLL_CLK_CONTROL_VAL + sw t1, AR933X_PLL_CLOCK_CTRL_REG(t0) + nop + + li t0, KSEG1ADDR(AR71XX_DDR_CTRL_BASE) + li t1, 0x7fbc8cd0 + sw t1, AR71XX_DDR_REG_CONFIG(t0) + + li t1, 0x9dd0e6a8 + sw t1, AR71XX_DDR_REG_CONFIG2(t0) + + andi t1, t5, 0x2000 # t5 BOOT_STRAP + beqz t1, 3f + nop + + /* Enable DDR2 */ + li t1, 0xA59 + sw t1, AR933X_DDR_REG_DDR2_CONFIG(t0) + + /* Precharge All */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Disable High Temperature Self-Refresh Rate */ + li t1, 0x00 + sw t1, AR933X_DDR_REG_EMR2(t0) + + /* Extended Mode Register 2 Set (EMR2S) */ + li t1, 0x10 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + li t1, 0x00 + sw t1, AR933X_DDR_REG_EMR3(t0) + + /* Extended Mode Register 3 Set (EMR3S) */ + li t1, 0x20 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Enable DLL */ + li t1, 0x00 + sw t1, AR71XX_DDR_REG_EMR(t0) + + /* Extended Mode Register Set (EMRS) */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Reset DLL */ + li t1, 0x100 + sw t1, AR71XX_DDR_REG_MODE(t0) + + /* Mode Register Set (MRS) */ + li t1, 0x01 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Precharge All */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Auto Refresh */ + li t1, 0x04 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Auto Refresh */ + li t1, 0x04 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */ + li t1, 0xa33 + sw t1, AR71XX_DDR_REG_MODE(t0) + + /* Mode Register Set (MRS) */ + li t1, 0x01 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* E7,E8,E9 equal to 1(Enable OCD defaults), Enable DLL, + Reduced Drive Strength */ + li t1, 0x382 + sw t1, AR71XX_DDR_REG_EMR(t0) + + /* Extended Mode Register Set (EMRS) */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* E7,E8,E9 equal to 0(OCD exit), Enable DLL, + Reduced Drive Strength */ + li t1, 0x402 + sw t1, AR71XX_DDR_REG_EMR(t0) + + /* Extended Mode Register Set (EMRS) */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x4186 + b 2f + nop +1: + li t1, 0x4270 +2: + sw t1, AR71XX_DDR_REG_REFRESH(t0) + + /* DQS 0 Tap Control (needs tuning) */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_TAP_CTRL0(t0) + + /* DQS 1 Tap Control (needs tuning) */ + li t1, 0x09 + sw t1, AR71XX_DDR_REG_TAP_CTRL1(t0) + + /* For 16-bit DDR */ + li t1, 0xff + sw t1, AR71XX_DDR_REG_RD_CYCLE(t0) + nop + b 4f + nop + + /* DDR1 config */ +3: + /* Precharge All */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Write Mode Word */ + li t1, 0x133 + sw t1, AR71XX_DDR_REG_MODE(t0) + + /* Forces an MRS update cycle in DDR */ + li t1, 0x01 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Enable DLL, High drive strength from DDR */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_EMR(t0) + + /* Write Extended Mode Word of DDR */ + li t1, 0x02 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Precharge All */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* DLL out of reset, CAS Latency 3 */ + li t1, 0x33 + sw t1, AR71XX_DDR_REG_MODE(t0) + + /* Write mode word */ + li t1, 0x01 + sw t1, AR71XX_DDR_REG_CONTROL(t0) + + /* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */ + andi t1, t5, 0x01 # t5 BOOT_STRAP + bnez t1, 1f + nop + li t1, 0x4270 + b 2f + nop +1: + li t1, 0x4186 +2: + sw t1, AR71XX_DDR_REG_REFRESH(t0) + + /* DQS 0 Tap Control (needs tuning) */ + li t1, 0x08 + sw t1, AR71XX_DDR_REG_TAP_CTRL0(t0) + + /* DQS 1 Tap Control (needs tuning) */ + li t1, 0x09 + sw t1, AR71XX_DDR_REG_TAP_CTRL1(t0) + + /* For 16-bit DDR */ + li t1, 0xff + sw t1, AR71XX_DDR_REG_RD_CYCLE(t0) + +4: + nop + jr ra + nop + END(lowlevel_init) diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c new file mode 100644 index 0000000..1f58877 --- /dev/null +++ b/arch/mips/mach-ath79/cpu.c @@ -0,0 +1,269 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ath79.h> +#include <asm/arch/ar71xx_regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum ath79_soc_type get_soc_type(void) +{ + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; + u32 id, major, minor; + + id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID)); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + soc = ATH79_SOC_AR7130; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + soc = ATH79_SOC_AR7141; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + soc = ATH79_SOC_AR7161; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + soc = ATH79_SOC_AR7240; + break; + + case REV_ID_MAJOR_AR7241: + soc = ATH79_SOC_AR7241; + break; + + case REV_ID_MAJOR_AR7242: + soc = ATH79_SOC_AR7242; + break; + + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + switch (minor) { + case AR913X_REV_ID_MINOR_AR9130: + soc = ATH79_SOC_AR9130; + break; + + case AR913X_REV_ID_MINOR_AR9132: + soc = ATH79_SOC_AR9132; + break; + } + break; + + case REV_ID_MAJOR_AR9330: + soc = ATH79_SOC_AR9330; + break; + + case REV_ID_MAJOR_AR9331: + soc = ATH79_SOC_AR9331; + break; + + case REV_ID_MAJOR_AR9341: + soc = ATH79_SOC_AR9341; + break; + + case REV_ID_MAJOR_AR9342: + soc = ATH79_SOC_AR9342; + break; + + case REV_ID_MAJOR_AR9344: + soc = ATH79_SOC_AR9344; + break; + + case REV_ID_MAJOR_QCA9533_V2: + /* drop through */ + + case REV_ID_MAJOR_QCA9533: + soc = ATH79_SOC_QCA9533; + break; + + case REV_ID_MAJOR_QCA9556: + soc = ATH79_SOC_QCA9556; + break; + + case REV_ID_MAJOR_QCA9558: + soc = ATH79_SOC_QCA9558; + break; + + case REV_ID_MAJOR_TP9343: + soc = ATH79_SOC_TP9343; + break; + + case REV_ID_MAJOR_QCA9561: + soc = ATH79_SOC_QCA9561; + break; + default: + break; + } + + return soc; +} + +int print_cpuinfo(void) +{ + enum ath79_soc_type soc = ATH79_SOC_UNKNOWN; + char *chip = "????"; + u32 id, major, minor; + u32 rev = 0; + u32 ver = 1; + + id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID)); + major = id & REV_ID_MAJOR_MASK; + + switch (major) { + case REV_ID_MAJOR_AR71XX: + minor = id & AR71XX_REV_ID_MINOR_MASK; + rev = id >> AR71XX_REV_ID_REVISION_SHIFT; + rev &= AR71XX_REV_ID_REVISION_MASK; + switch (minor) { + case AR71XX_REV_ID_MINOR_AR7130: + soc = ATH79_SOC_AR7130; + chip = "7130"; + break; + + case AR71XX_REV_ID_MINOR_AR7141: + soc = ATH79_SOC_AR7141; + chip = "7141"; + break; + + case AR71XX_REV_ID_MINOR_AR7161: + soc = ATH79_SOC_AR7161; + chip = "7161"; + break; + } + break; + + case REV_ID_MAJOR_AR7240: + soc = ATH79_SOC_AR7240; + chip = "7240"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR7241: + soc = ATH79_SOC_AR7241; + chip = "7241"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR7242: + soc = ATH79_SOC_AR7242; + chip = "7242"; + rev = id & AR724X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR913X: + minor = id & AR913X_REV_ID_MINOR_MASK; + rev = id >> AR913X_REV_ID_REVISION_SHIFT; + rev &= AR913X_REV_ID_REVISION_MASK; + switch (minor) { + case AR913X_REV_ID_MINOR_AR9130: + soc = ATH79_SOC_AR9130; + chip = "9130"; + break; + + case AR913X_REV_ID_MINOR_AR9132: + soc = ATH79_SOC_AR9132; + chip = "9132"; + break; + } + break; + + case REV_ID_MAJOR_AR9330: + soc = ATH79_SOC_AR9330; + chip = "9330"; + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9331: + soc = ATH79_SOC_AR9331; + chip = "9331"; + rev = id & AR933X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9341: + soc = ATH79_SOC_AR9341; + chip = "9341"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9342: + soc = ATH79_SOC_AR9342; + chip = "9342"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_AR9344: + soc = ATH79_SOC_AR9344; + chip = "9344"; + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9533_V2: + ver = 2; + /* drop through */ + + case REV_ID_MAJOR_QCA9533: + soc = ATH79_SOC_QCA9533; + chip = "9533"; + rev = id & QCA953X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9556: + soc = ATH79_SOC_QCA9556; + chip = "9556"; + rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9558: + soc = ATH79_SOC_QCA9558; + chip = "9558"; + rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_TP9343: + soc = ATH79_SOC_TP9343; + chip = "9343"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCA9561: + soc = ATH79_SOC_QCA9561; + chip = "9561"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + } + + puts("SoC: "); + switch (soc) { + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA9561: + printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip, ver, rev); + break; + case ATH79_SOC_TP9343: + printf("Qualcomm Atheros TP%s rev %u\n", chip, rev); + break; + case ATH79_SOC_UNKNOWN: + printf("ATH79: unknown SoC, id:0x%08x", id); + default: + printf("Atheros AR%s rev %u\n", chip, rev); + } + + return 0; +} diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c new file mode 100644 index 0000000..42539dc --- /dev/null +++ b/arch/mips/mach-ath79/dram.c @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/addrspace.h> +#include <asm/arch/ddr.h> + +phys_size_t initdram(int board_type) +{ + uint8_t *addr, *p; + int i; + + ddr_tap_init(); + addr = (uint8_t *)KSEG1; + *addr = 0x77; + for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) { + p += 0x1000000; + *p = i; + if (*addr != 0x77) + break; + } + return (phys_size_t)(p - addr); +} diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file mode 100644 index 0000000..228ae02 --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -0,0 +1,1144 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2015 Wills Wang, <wills.wang(a)live.com> + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan(a)atheros.com> + * Copyright (C) 2008-2010 Gabor Juhos <juhosg(a)openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz(a)openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#else +#ifndef BIT +#define BIT(nr) (1UL << (nr)) +#endif +#endif + +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x100 + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) +#define AR933X_RTC_SIZE 0x1000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 +#define AR933X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR933X_SRIF_SIZE 0x1000 + +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 +#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 +#define AR934X_NFC_BASE 0x1b000200 +#define AR934X_NFC_SIZE 0xb8 +#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define AR934X_SRIF_SIZE 0x1000 + +#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA953X_GMAC_SIZE 0x14 +#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA953X_WMAC_SIZE 0x20000 +#define QCA953X_EHCI_BASE 0x1b000000 +#define QCA953X_EHCI_SIZE 0x200 +#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +#define QCA953X_SRIF_SIZE 0x1000 + +#define QCA953X_PCI_CFG_BASE0 0x14000000 +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA953X_PCI_MEM_BASE0 0x10000000 +#define QCA953X_PCI_MEM_SIZE 0x02000000 + +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_NFC_BASE 0x1b800200 +#define QCA955X_NFC_SIZE 0xb8 + +#define QCA956X_PCI_MEM_BASE1 0x12000000 +#define QCA956X_PCI_MEM_SIZE 0x02000000 +#define QCA956X_PCI_CFG_BASE1 0x16000000 +#define QCA956X_PCI_CFG_SIZE 0x1000 +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA956X_PCI_CRP_SIZE 0x1000 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA956X_PCI_CTRL_SIZE 0x100 + +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA956X_WMAC_SIZE 0x20000 +#define QCA956X_EHCI0_BASE 0x1b000000 +#define QCA956X_EHCI1_BASE 0x1b400000 +#define QCA956X_EHCI_SIZE 0x200 +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA956X_GMAC_SIZE 0x64 + +#define AR9300_OTP_BASE 0x14000 +#define AR9300_OTP_STATUS 0x15f18 +#define AR9300_OTP_STATUS_TYPE 0x7 +#define AR9300_OTP_STATUS_VALID 0x4 +#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 +#define AR9300_OTP_STATUS_SM_BUSY 0x1 +#define AR9300_OTP_READ_DATA 0x15f1c + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_CONFIG 0x00 +#define AR71XX_DDR_REG_CONFIG2 0x04 +#define AR71XX_DDR_REG_MODE 0x08 +#define AR71XX_DDR_REG_EMR 0x0c +#define AR71XX_DDR_REG_CONTROL 0x10 +#define AR71XX_DDR_REG_REFRESH 0x14 +#define AR71XX_DDR_REG_RD_CYCLE 0x18 +#define AR71XX_DDR_REG_TAP_CTRL0 0x1c +#define AR71XX_DDR_REG_TAP_CTRL1 0x20 + +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 +#define AR933X_DDR_REG_DDR2_CONFIG 0x8c +#define AR933X_DDR_REG_EMR2 0x90 +#define AR933X_DDR_REG_EMR3 0x94 +#define AR933X_DDR_REG_BURST 0x98 +#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c +#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c +#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c + +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac + +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 +#define QCA953X_DDR_REG_FLUSH_USB 0xa4 +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +#define AR913X_ETH0_PLL_SHIFT 20 +#define AR913X_ETH1_PLL_SHIFT 22 + +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) + +#define QCA953X_PLL_CPU_CONFIG_REG 0x00 +#define QCA953X_PLL_DDR_CONFIG_REG 0x04 +#define QCA953X_PLL_CLK_CTRL_REG 0x08 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48 + +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA956X_PLL_CPU_CONFIG_REG 0x00 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c +#define QCA956X_PLL_CLK_CTRL_REG 0x10 + +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +/* + * USB_CONFIG block + */ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA953X_RESET_REG_RESET_MODULE 0x1c +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA955X_RESET_REG_RESET_MODULE 0x1c +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +#define QCA956X_RESET_REG_RESET_MODULE 0x1c +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac + +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) + +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR934X_RESET_HOST BIT(31) +#define AR934X_RESET_SLIC BIT(30) +#define AR934X_RESET_HDMA BIT(29) +#define AR934X_RESET_EXTERNAL BIT(28) +#define AR934X_RESET_RTC BIT(27) +#define AR934X_RESET_PCIE_EP_INT BIT(26) +#define AR934X_RESET_CHKSUM_ACC BIT(25) +#define AR934X_RESET_FULL_CHIP BIT(24) +#define AR934X_RESET_GE1_MDIO BIT(23) +#define AR934X_RESET_GE0_MDIO BIT(22) +#define AR934X_RESET_CPU_NMI BIT(21) +#define AR934X_RESET_CPU_COLD BIT(20) +#define AR934X_RESET_HOST_RESET_INT BIT(19) +#define AR934X_RESET_PCIE_EP BIT(18) +#define AR934X_RESET_UART1 BIT(17) +#define AR934X_RESET_DDR BIT(16) +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define AR934X_RESET_NANDF BIT(14) +#define AR934X_RESET_GE1_MAC BIT(13) +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_HOST_DMA_INT BIT(10) +#define AR934X_RESET_GE0_MAC BIT(9) +#define AR934X_RESET_ETH_SWITCH BIT(8) +#define AR934X_RESET_PCIE_PHY BIT(7) +#define AR934X_RESET_PCIE BIT(6) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) + +#define QCA953X_RESET_USB_EXT_PWR BIT(29) +#define QCA953X_RESET_EXTERNAL BIT(28) +#define QCA953X_RESET_RTC BIT(27) +#define QCA953X_RESET_FULL_CHIP BIT(24) +#define QCA953X_RESET_GE1_MDIO BIT(23) +#define QCA953X_RESET_GE0_MDIO BIT(22) +#define QCA953X_RESET_CPU_NMI BIT(21) +#define QCA953X_RESET_CPU_COLD BIT(20) +#define QCA953X_RESET_DDR BIT(16) +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA953X_RESET_GE1_MAC BIT(13) +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA953X_RESET_GE0_MAC BIT(9) +#define QCA953X_RESET_ETH_SWITCH BIT(8) +#define QCA953X_RESET_PCIE_PHY BIT(7) +#define QCA953X_RESET_PCIE BIT(6) +#define QCA953X_RESET_USB_HOST BIT(5) +#define QCA953X_RESET_USB_PHY BIT(4) +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) + +#define QCA955X_RESET_HOST BIT(31) +#define QCA955X_RESET_SLIC BIT(30) +#define QCA955X_RESET_HDMA BIT(29) +#define QCA955X_RESET_EXTERNAL BIT(28) +#define QCA955X_RESET_RTC BIT(27) +#define QCA955X_RESET_PCIE_EP_INT BIT(26) +#define QCA955X_RESET_CHKSUM_ACC BIT(25) +#define QCA955X_RESET_FULL_CHIP BIT(24) +#define QCA955X_RESET_GE1_MDIO BIT(23) +#define QCA955X_RESET_GE0_MDIO BIT(22) +#define QCA955X_RESET_CPU_NMI BIT(21) +#define QCA955X_RESET_CPU_COLD BIT(20) +#define QCA955X_RESET_HOST_RESET_INT BIT(19) +#define QCA955X_RESET_PCIE_EP BIT(18) +#define QCA955X_RESET_UART1 BIT(17) +#define QCA955X_RESET_DDR BIT(16) +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA955X_RESET_NANDF BIT(14) +#define QCA955X_RESET_GE1_MAC BIT(13) +#define QCA955X_RESET_SGMII_ANALOG BIT(12) +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA955X_RESET_HOST_DMA_INT BIT(10) +#define QCA955X_RESET_GE0_MAC BIT(9) +#define QCA955X_RESET_SGMII BIT(8) +#define QCA955X_RESET_PCIE_PHY BIT(7) +#define QCA955X_RESET_PCIE BIT(6) +#define QCA955X_RESET_USB_HOST BIT(5) +#define QCA955X_RESET_USB_PHY BIT(4) +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) +#define QCA955X_RESET_LUT BIT(2) +#define QCA955X_RESET_MBOX BIT(1) +#define QCA955X_RESET_I2S BIT(0) + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define QCA953X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) + +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) + +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ + (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ + QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) + +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ + (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ + QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ + QCA953X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + +#define QCA956X_EXT_INT_WMAC_MISC BIT(0) +#define QCA956X_EXT_INT_WMAC_TX BIT(1) +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA956X_EXT_INT_USB1 BIT(24) +#define QCA956X_EXT_INT_USB2 BIT(28) + +#define QCA956X_EXT_INT_WMAC_ALL \ + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) + +#define QCA956X_EXT_INT_PCIE_RC1_ALL \ + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ + QCA956X_EXT_INT_PCIE_RC1_INT3) + +#define QCA956X_EXT_INT_PCIE_RC2_ALL \ + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ + QCA956X_EXT_INT_PCIE_RC2_INT3) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9533 0x0140 +#define REV_ID_MAJOR_QCA9533_V2 0x0160 +#define REV_ID_MAJOR_QCA9556 0x0130 +#define REV_ID_MAJOR_QCA9558 0x1130 +#define REV_ID_MAJOR_TP9343 0x0150 +#define REV_ID_MAJOR_QCA9561 0x1150 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR913X_REV_ID_MINOR_MASK 0x3 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 +#define AR913X_REV_ID_REVISION_MASK 0x3 +#define AR913X_REV_ID_REVISION_SHIFT 2 + +#define AR933X_REV_ID_REVISION_MASK 0x3 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +#define AR934X_REV_ID_REVISION_MASK 0xf + +#define QCA953X_REV_ID_REVISION_MASK 0xf + +#define QCA955X_REV_ID_REVISION_MASK 0xf + +#define QCA956X_REV_ID_REVISION_MASK 0xf + +/* + * RTC block + */ +#define AR933X_RTC_REG_RESET 0x40 +#define AR933X_RTC_REG_STATUS 0x44 +#define AR933X_RTC_REG_DERIVED 0x48 +#define AR933X_RTC_REG_FORCE_WAKE 0x4c +#define AR933X_RTC_REG_INT_CAUSE 0x50 +#define AR933X_RTC_REG_CAUSE_CLR 0x50 +#define AR933X_RTC_REG_INT_ENABLE 0x54 +#define AR933X_RTC_REG_INT_MASKE 0x58 + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ + AR71XX_SPI_IOC_CS2) + +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 +#define AR933X_GPIO_REG_FUNC 0x30 + +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 +#define AR934X_GPIO_REG_FUNC 0x6c + +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA953X_GPIO_REG_FUNC 0x6c + +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA955X_GPIO_REG_FUNC 0x6c + +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 +#define QCA956X_GPIO_REG_FUNC 0x6c + +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 + +#define AR71XX_GPIO_COUNT 16 +#define AR7240_GPIO_COUNT 18 +#define AR7241_GPIO_COUNT 20 +#define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 +#define QCA953X_GPIO_COUNT 18 +#define QCA955X_GPIO_COUNT 24 +#define QCA956X_GPIO_COUNT 23 + +/* + * SRIF block + */ +#define AR933X_SRIF_DDR_DPLL1_REG 0x240 +#define AR933X_SRIF_DDR_DPLL2_REG 0x244 +#define AR933X_SRIF_DDR_DPLL3_REG 0x248 +#define AR933X_SRIF_DDR_DPLL4_REG 0x24c + +#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 +#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 +#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define AR934X_SRIF_DDR_DPLL1_REG 0x240 +#define AR934X_SRIF_DDR_DPLL2_REG 0x244 +#define AR934X_SRIF_DDR_DPLL3_REG 0x248 + +#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 +#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff +#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 + +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 + +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff + +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 + +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR913X_GPIO_FUNC_UART_EN BIT(8) +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) + +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR933X_GPIO_FUNC_XLNA_EN BIT(12) + +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) + +#define AR934X_GPIO_OUT_GPIO 0 +#define AR934X_GPIO_OUT_SPI_CS1 7 +#define AR934X_GPIO_OUT_LED_LINK0 41 +#define AR934X_GPIO_OUT_LED_LINK1 42 +#define AR934X_GPIO_OUT_LED_LINK2 43 +#define AR934X_GPIO_OUT_LED_LINK3 44 +#define AR934X_GPIO_OUT_LED_LINK4 45 +#define AR934X_GPIO_OUT_EXT_LNA0 46 +#define AR934X_GPIO_OUT_EXT_LNA1 47 + +#define QCA955X_GPIO_OUT_GPIO 0 + +/* + * MII_CTRL block + */ +#define AR71XX_MII_REG_MII0_CTRL 0x00 +#define AR71XX_MII_REG_MII1_CTRL 0x04 + +#define AR71XX_MII_CTRL_IF_MASK 3 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 +#define AR71XX_MII_CTRL_SPEED_MASK 3 +#define AR71XX_MII_CTRL_SPEED_10 0 +#define AR71XX_MII_CTRL_SPEED_100 1 +#define AR71XX_MII_CTRL_SPEED_1000 2 + +#define AR71XX_MII0_CTRL_IF_GMII 0 +#define AR71XX_MII0_CTRL_IF_MII 1 +#define AR71XX_MII0_CTRL_IF_RGMII 2 +#define AR71XX_MII0_CTRL_IF_RMII 3 + +#define AR71XX_MII1_CTRL_IF_RGMII 0 +#define AR71XX_MII1_CTRL_IF_RMII 1 + +/* + * AR933X GMAC interface + */ +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) + +/* + * AR934X GMAC Interface + */ +#define AR934X_GMAC_REG_ETH_CFG 0x00 + +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) +#define AR934X_ETH_CFG_RXD_DELAY BIT(14) +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 +#define AR934X_ETH_CFG_RDV_DELAY BIT(16) +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 + +/* + * QCA953X GMAC Interface + */ +#define QCA953X_GMAC_REG_ETH_CFG 0x00 + +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + +/* + * QCA955X GMAC Interface + */ + +#define QCA955X_GMAC_REG_ETH_CFG 0x00 + +#define QCA955X_ETH_CFG_RGMII_EN BIT(0) +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) + +#endif /* __ASM_AR71XX_H */ diff --git a/arch/mips/mach-ath79/include/mach/ar933x_uart.h b/arch/mips/mach-ath79/include/mach/ar933x_uart.h new file mode 100644 index 0000000..40da419 --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ar933x_uart.h @@ -0,0 +1,66 @@ +/* + * Atheros AR933X UART defines + * + * Copyright (C) 2015 Wills Wang, <wills.wang(a)live.com> + * Copyright (C) 2011 Gabor Juhos <juhosg(a)openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AR933X_UART_H +#define __AR933X_UART_H + +#define AR933X_UART_REGS_SIZE 20 +#define AR933X_UART_FIFO_SIZE 16 + +#define AR933X_UART_DATA_REG 0x00 +#define AR933X_UART_CS_REG 0x04 +#define AR933X_UART_CLOCK_REG 0x08 +#define AR933X_UART_INT_REG 0x0c +#define AR933X_UART_INT_EN_REG 0x10 + +#define AR933X_UART_DATA_TX_RX_MASK 0xff +#define AR933X_UART_DATA_RX_CSR BIT(8) +#define AR933X_UART_DATA_TX_CSR BIT(9) + +#define AR933X_UART_CS_PARITY_S 0 +#define AR933X_UART_CS_PARITY_M 0x3 +#define AR933X_UART_CS_PARITY_NONE 0 +#define AR933X_UART_CS_PARITY_ODD 1 +#define AR933X_UART_CS_PARITY_EVEN 2 +#define AR933X_UART_CS_IF_MODE_S 2 +#define AR933X_UART_CS_IF_MODE_M 0x3 +#define AR933X_UART_CS_IF_MODE_NONE 0 +#define AR933X_UART_CS_IF_MODE_DTE 1 +#define AR933X_UART_CS_IF_MODE_DCE 2 +#define AR933X_UART_CS_FLOW_CTRL_S 4 +#define AR933X_UART_CS_FLOW_CTRL_M 0x3 +#define AR933X_UART_CS_DMA_EN BIT(6) +#define AR933X_UART_CS_TX_READY_ORIDE BIT(7) +#define AR933X_UART_CS_RX_READY_ORIDE BIT(8) +#define AR933X_UART_CS_TX_READY BIT(9) +#define AR933X_UART_CS_RX_BREAK BIT(10) +#define AR933X_UART_CS_TX_BREAK BIT(11) +#define AR933X_UART_CS_HOST_INT BIT(12) +#define AR933X_UART_CS_HOST_INT_EN BIT(13) +#define AR933X_UART_CS_TX_BUSY BIT(14) +#define AR933X_UART_CS_RX_BUSY BIT(15) + +#define AR933X_UART_CLOCK_STEP_M 0xffff +#define AR933X_UART_CLOCK_SCALE_M 0xfff +#define AR933X_UART_CLOCK_SCALE_S 16 +#define AR933X_UART_CLOCK_STEP_S 0 + +#define AR933X_UART_INT_RX_VALID BIT(0) +#define AR933X_UART_INT_TX_READY BIT(1) +#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2) +#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3) +#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4) +#define AR933X_UART_INT_RX_PARITY_ERR BIT(5) +#define AR933X_UART_INT_RX_BREAK_ON BIT(6) +#define AR933X_UART_INT_RX_BREAK_OFF BIT(7) +#define AR933X_UART_INT_RX_FULL BIT(8) +#define AR933X_UART_INT_TX_EMPTY BIT(9) +#define AR933X_UART_INT_ALLINTS 0x3ff + +#endif /* __AR933X_UART_H */ diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h new file mode 100644 index 0000000..15bb590 --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ath79.h @@ -0,0 +1,143 @@ +/* + * Atheros AR71XX/AR724X/AR913X common definitions + * + * Copyright (C) 2015 Wills Wang, <wills.wang(a)live.com> + * Copyright (C) 2008-2011 Gabor Juhos <juhosg(a)openwrt.org> + * Copyright (C) 2008 Imre Kaloz <kaloz(a)openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_ATH79_H +#define __ASM_MACH_ATH79_H + +#include <linux/types.h> + +enum ath79_soc_type { + ATH79_SOC_UNKNOWN, + ATH79_SOC_AR7130, + ATH79_SOC_AR7141, + ATH79_SOC_AR7161, + ATH79_SOC_AR7240, + ATH79_SOC_AR7241, + ATH79_SOC_AR7242, + ATH79_SOC_AR9130, + ATH79_SOC_AR9132, + ATH79_SOC_AR9330, + ATH79_SOC_AR9331, + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, + ATH79_SOC_QCA9533, + ATH79_SOC_QCA9556, + ATH79_SOC_QCA9558, + ATH79_SOC_TP9343, + ATH79_SOC_QCA9561, +}; + +enum ath79_soc_type get_soc_type(void); + +static inline int soc_is_ar71xx(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7130 || + soc == ATH79_SOC_AR7141 || + soc == ATH79_SOC_AR7161; +} + +static inline int soc_is_ar724x(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7240 || + soc == ATH79_SOC_AR7241 || + soc == ATH79_SOC_AR7242; +} + +static inline int soc_is_ar7240(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7240; +} + +static inline int soc_is_ar7241(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7241; +} + +static inline int soc_is_ar7242(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR7242; +} + +static inline int soc_is_ar913x(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9130 || + soc == ATH79_SOC_AR9132; +} + +static inline int soc_is_ar933x(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9330 || + soc == ATH79_SOC_AR9331; +} + +static inline int soc_is_ar9341(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9341; +} + +static inline int soc_is_ar9342(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9342; +} + +static inline int soc_is_ar9344(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_AR9344; +} + +static inline int soc_is_ar934x(enum ath79_soc_type soc) +{ + return soc_is_ar9341(soc) || + soc_is_ar9342(soc) || + soc_is_ar9344(soc); +} + +static inline int soc_is_qca9533(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_QCA9533; +} + +static inline int soc_is_qca953x(enum ath79_soc_type soc) +{ + return soc_is_qca9533(soc); +} + +static inline int soc_is_qca9556(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_QCA9556; +} + +static inline int soc_is_qca9558(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_QCA9558; +} + +static inline int soc_is_qca955x(enum ath79_soc_type soc) +{ + return soc_is_qca9556(soc) || soc_is_qca9558(soc); +} + +static inline int soc_is_tp9343(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_TP9343; +} + +static inline int soc_is_qca9561(enum ath79_soc_type soc) +{ + return soc == ATH79_SOC_QCA9561; +} + +static inline int soc_is_qca956x(enum ath79_soc_type soc) +{ + return soc_is_tp9343(soc) || soc_is_qca9561(soc); +} + +#endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/mach-ath79/include/mach/ddr.h b/arch/mips/mach-ath79/include/mach/ddr.h new file mode 100644 index 0000000..e90c9a1 --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/ddr.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_DDR_H +#define __ASM_MACH_DDR_H + +void ddr_tap_init(void); + +#endif /* __ASM_MACH_DDR_H */ diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c new file mode 100644 index 0000000..0ace05d --- /dev/null +++ b/arch/mips/mach-ath79/reset.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ath79.h> +#include <asm/arch/ar71xx_regs.h> + +#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) +#define REG_WRITE(b, o, v) writel(v, KSEG1ADDR((b + o))) +#define RST_READ(a) REG_READ(AR71XX_RESET_BASE, a) +#define RST_WRITE(a, v) REG_WRITE(AR71XX_RESET_BASE, a, v) + +DECLARE_GLOBAL_DATA_PTR; + +void _machine_restart(void) +{ + enum ath79_soc_type soc; + u32 val, reg = 0; + + soc = get_soc_type(); + if (soc_is_ar71xx(soc)) + reg = AR71XX_RESET_REG_RESET_MODULE; + else if (soc_is_ar724x(soc)) + reg = AR724X_RESET_REG_RESET_MODULE; + else if (soc_is_ar913x(soc)) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x(soc)) + reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x(soc)) + reg = AR934X_RESET_REG_RESET_MODULE; + else if (soc_is_qca953x(soc)) + reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x(soc)) + reg = QCA955X_RESET_REG_RESET_MODULE; + else if (soc_is_qca956x(soc)) + reg = QCA956X_RESET_REG_RESET_MODULE; + else + puts("Reset register not defined for this SOC\n"); + + if (reg) { + val = RST_READ(reg); + val |= AR71XX_RESET_FULL_CHIP; + RST_WRITE(reg, val); + } + + while (1) + /* NOP */; +} -- 1.9.1

3 28

[U-Boot] [RFC PATCH 00/11] Add support for 96boards Dragonboard410C board
by Mateusz Kulikowski 28 Dec '15

28 Dec '15

Hi All, With a slight delay (Sorry Syed) I'm finally ready to show code I've been working recently on. This series add support for: - New board - 96board Dragonboard 410C (ARMv8) - Qualcomm snapdragon architecture (for now only single SoC) - Some Qualcomm peripherals (UART, GPIO, PMIC including bus, SDHCI, USB...) - New bus (SPMI) - It also adds minor function to ehci HCD Please take a look at it and give me feedback what can be changed so it will be ready for submission. I'd like to thank Przemyslaw Marczak for doing initial reviews and helping me figure out what is the best approach in some cases. Notes/Design decisions I made/Issues I have/had (please comment them as well) 0) If I missed someone on CC - please let me know; If I misused patman - apologize for that - It's my first time with patman. 1) Documentation is missing - dt-bindings, spmi bus documentation. I left it as I expect some redesign after your review. 2) I tried to use DM and Kconfig where possible, but some drivers (USB) depend on subsystems that don't support Kconfig yet 3) There are 3 long-line warnings and some complains about too short Kconfig - is it ok to ignore lines that are 1-2 characters longer (and making them shorter will cause code to be less readable)? 4) Licensing (@trini) My code is based on 2 trees: Linux: https://git.linaro.org/landing-teams/working/qualcomm/kernel.git LittleKernel: https://git.linaro.org/people/nicolas.dechesne/lk.git One is GPLv2, other BSD(-clause3 I think). When tried to figure out how to write drivers, I looked at both drivers, and even if some drivers are totally different than their originals, they are derivative work. I decided to use Linux license where possible (where I was almost sure I copied/analyzed Linux drivers), left BSD only for SPMI code. Is it ok? Or should I run tool like Protex and drop references where code no longer matches linux/lk codebase (not that I have Protex at home) 5) Clock mapping - I need advice on how to properly access clock controller from devices that need some clocks to be enabled. I want clock controller code to be as simple as possible, but am not sure how to add links to a specific clocks. 6) SPMI: I decided to add new bus. Contrary to other vendors, Qualcomm SoCs use SPMI to talk with PMICs. This is "closed" bus (you need to pay membership to get specification), and I need it to properly describe pmics inside device tree. 7) Snapdragon mach: I added new MACH as my plan is to support more than one Qualcomm SoC/board - hopefully days where U-Boot had no Qualcomm support will be over soon :) 8) I didn't modified Maintainers files - will do that for PATCH v1 9) I moved register offsets to driver files (didn't put them in one big header file. I know it's not common but IMO it's better if drivers are self contained (and there are not many registers anyways). 10) Compilation causes 8 warnings, none in my code: - 1x in asix88179 driver (format %u expects...) - 7x in ulpi-viewport code The problem is - this drivers are handling poorly ARMv8 processors, where sizeof(int) < sizeof(void*) and sizeof(int) < sizeof(long). Fix for asix would be trivial, with ULPI it's worse as in my opinion it needs slight redesign (use phaddr_t or something). Is it ok if I redesign that? Or just ignore warnings or write my own ulpi code (I wanted to avoid code duplication) Best Regards, Mateusz Mateusz Kulikowski (11): serial: Add support for Qualcomm serial port gpio: Add support for Qualcomm gpio controller mmc: Add support for Qualcomm SDHCI controller ehci-hcd: Add init_after_reset ehci: Add support for Qualcomm EHCI drivers: Add SPMI bus uclass drivers: spmi: Add support for Qualcomm SPMI bus driver pmic: Add support for Qualcomm PM8916 PMIC gpio: Add support for Qualcomm PM8916 gpios arm: Add support for Qualcomm Snapdragon family board: Add Qualcomm Dragonboard 410C support arch/arm/Kconfig | 12 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/dragonboard410c.dts | 157 +++++++++++ arch/arm/mach-snapdragon/Kconfig | 15 + arch/arm/mach-snapdragon/Makefile | 8 + arch/arm/mach-snapdragon/clock-apq8016.c | 262 ++++++++++++++++++ arch/arm/mach-snapdragon/include/mach/gpio.h | 25 ++ .../mach-snapdragon/include/mach/sysmap-apq8016.h | 15 + arch/arm/mach-snapdragon/reset.c | 40 +++ board/qualcomm/dragonboard410c/Kconfig | 15 + board/qualcomm/dragonboard410c/Makefile | 8 + board/qualcomm/dragonboard410c/dragonboard410c.c | 111 ++++++++ board/qualcomm/dragonboard410c/head.S | 20 ++ board/qualcomm/dragonboard410c/readme.txt | 40 +++ board/qualcomm/dragonboard410c/u-boot.lds | 90 ++++++ configs/dragonboard410c_defconfig | 29 ++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/gpio/Kconfig | 14 + drivers/gpio/Makefile | 3 +- drivers/gpio/msm_gpio.c | 115 ++++++++ drivers/gpio/pm8916_gpio.c | 306 +++++++++++++++++++++ drivers/mmc/Kconfig | 6 + drivers/mmc/Makefile | 1 + drivers/mmc/msm_sdhci.c | 149 ++++++++++ drivers/power/pmic/Kconfig | 14 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pm8916.c | 92 +++++++ drivers/serial/Kconfig | 5 + drivers/serial/Makefile | 1 + drivers/serial/serial_msm.c | 204 ++++++++++++++ drivers/spmi/Kconfig | 16 ++ drivers/spmi/Makefile | 8 + drivers/spmi/spmi-msm.c | 183 ++++++++++++ drivers/spmi/spmi-uclass.c | 53 ++++ drivers/usb/host/Kconfig | 8 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-hcd.c | 6 + drivers/usb/host/ehci-msm.c | 198 +++++++++++++ drivers/usb/host/ehci.h | 1 + include/configs/dragonboard410c.h | 184 +++++++++++++ include/dm/uclass-id.h | 1 + include/spmi/spmi.h | 44 +++ 44 files changed, 2466 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/dragonboard410c.dts create mode 100644 arch/arm/mach-snapdragon/Kconfig create mode 100644 arch/arm/mach-snapdragon/Makefile create mode 100644 arch/arm/mach-snapdragon/clock-apq8016.c create mode 100644 arch/arm/mach-snapdragon/include/mach/gpio.h create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h create mode 100644 arch/arm/mach-snapdragon/reset.c create mode 100644 board/qualcomm/dragonboard410c/Kconfig create mode 100644 board/qualcomm/dragonboard410c/Makefile create mode 100644 board/qualcomm/dragonboard410c/dragonboard410c.c create mode 100644 board/qualcomm/dragonboard410c/head.S create mode 100644 board/qualcomm/dragonboard410c/readme.txt create mode 100644 board/qualcomm/dragonboard410c/u-boot.lds create mode 100644 configs/dragonboard410c_defconfig create mode 100644 drivers/gpio/msm_gpio.c create mode 100644 drivers/gpio/pm8916_gpio.c create mode 100644 drivers/mmc/msm_sdhci.c create mode 100644 drivers/power/pmic/pm8916.c create mode 100644 drivers/serial/serial_msm.c create mode 100644 drivers/spmi/Kconfig create mode 100644 drivers/spmi/Makefile create mode 100644 drivers/spmi/spmi-msm.c create mode 100644 drivers/spmi/spmi-uclass.c create mode 100644 drivers/usb/host/ehci-msm.c create mode 100644 include/configs/dragonboard410c.h create mode 100644 include/spmi/spmi.h -- 2.5.0

6 42

[U-Boot] [PATCH 0/8] sf: Add flash_ids inside Core
by Jagan Teki 28 Dec '15

28 Dec '15

This series handle flash_ids stuff inside spi_flash core. Jagan Teki (8): sf: Add spi_flash_ids local to core sf: Rename SST_WR to SST_WRITE sf: Remove SPI_NOR_DUAL|QUAD_READ sf: Use sf_params in sandbox sf: Remove SECT_32K sf: Add SECT_4K_PMC sf: Use CONFIG_SPI_FLASH_USE_4K_SECTORS sf: Fix few naming convension for read modes drivers/mtd/spi/Makefile | 4 +- drivers/mtd/spi/sf_internal.h | 5 +- drivers/mtd/spi/spi_flash.c | 446 +++++++++++++++++++++++++++++++++++------- include/linux/err.h | 5 + 4 files changed, 383 insertions(+), 77 deletions(-) -- 1.9.1

2 10

[U-Boot] [PATCH 1/5] altera_qspi: call callback even if the erase failed
by Thomas Chou 28 Dec '15

28 Dec '15

Erase is an asynchronous operation. Device drivers are supposed to call instr->callback() whenever the operation completes, even if it completes with a failure. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- drivers/mtd/altera_qspi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c index c7e37ad..627a8cc 100644 --- a/drivers/mtd/altera_qspi.c +++ b/drivers/mtd/altera_qspi.c @@ -146,6 +146,7 @@ static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info *instr) debug("erase %08x fail %x\n", sect, stat); writel(stat, &regs->isr); /* clear isr */ instr->state = MTD_ERASE_FAILED; + mtd_erase_callback(instr); return -EIO; } addr += mtd->erasesize; -- 2.5.0

2 29

[U-Boot] [PATCH v3 1/4] sf: Fix quad bit set for micron devices
by Jagan Teki 28 Dec '15

28 Dec '15

Setting up quad bit for micron devices need to do the same way as other flash devices like spansion, winbond etc does using enhanced volatile config register so this patch adds this support instead of printing "QEB is volatile" Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Peter Pan <peterpandong(a)micron.com> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Jagan Teki <jteki(a)openedev.com> --- Changes for v3: - Fixed if statement for 'quad bit not clear' Changes for v2: - none drivers/mtd/spi/sf_internal.h | 3 +++ drivers/mtd/spi/spi_flash.c | 62 +++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 63 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 561abc3..55ba81e 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -77,6 +77,7 @@ enum spi_nor_option_flags { #define CMD_WRITE_DISABLE 0x04 #define CMD_WRITE_ENABLE 0x06 #define CMD_QUAD_PAGE_PROGRAM 0x32 +#define CMD_WRITE_EVCR 0x61 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -90,6 +91,7 @@ enum spi_nor_option_flags { #define CMD_READ_STATUS1 0x35 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 +#define CMD_READ_EVCR 0x65 /* Bank addr access commands */ #ifdef CONFIG_SPI_FLASH_BAR @@ -104,6 +106,7 @@ enum spi_nor_option_flags { #define STATUS_QEB_WINSPAN BIT(1) #define STATUS_QEB_MXIC BIT(6) #define STATUS_PEC BIT(7) +#define STATUS_QEB_MICRON BIT(7) #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 6fe8c9d..30058d0 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -111,6 +111,37 @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif +#ifdef CONFIG_SPI_FLASH_STMICRO +static int read_evcr(struct spi_flash *flash, u8 *evcr) +{ + int ret; + const u8 cmd = CMD_READ_EVCR; + + ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1); + if (ret < 0) { + debug("SF: error reading EVCR\n"); + return ret; + } + + return 0; +} + +static int write_evcr(struct spi_flash *flash, u8 evcr) +{ + u8 cmd; + int ret; + + cmd = CMD_WRITE_EVCR; + ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1); + if (ret < 0) { + debug("SF: error while writing EVCR register\n"); + return ret; + } + + return 0; +} +#endif + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_write_bar(struct spi_flash *flash, u32 offset) { @@ -843,6 +874,34 @@ static int spansion_quad_enable(struct spi_flash *flash) } #endif +#ifdef CONFIG_SPI_FLASH_STMICRO +static int micron_quad_enable(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = read_evcr(flash, &qeb_status); + if (ret < 0) + return ret; + + if (!(qeb_status & STATUS_QEB_MICRON)) + return 0; + + ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON); + if (ret < 0) + return ret; + + /* read EVCR and check it */ + ret = read_evcr(flash, &qeb_status); + if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) { + printf("SF: Micron EVCR Quad bit not clear\n"); + return -EINVAL; + } + + return ret; +} +#endif + static int set_quad_mode(struct spi_flash *flash, u8 idcode0) { switch (idcode0) { @@ -857,8 +916,7 @@ static int set_quad_mode(struct spi_flash *flash, u8 idcode0) #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: - debug("SF: QEB is volatile for %02x flash\n", idcode0); - return 0; + return micron_quad_enable(flash); #endif default: printf("SF: Need set QEB func for %02x flash\n", idcode0); -- 1.9.1

1 7

[U-Boot] [PATCH 0/8] spi: Cleanup set
by Jagan Teki 28 Dec '15

28 Dec '15

Cleanup set on spi_slave{} Jagan Teki (8): spi: Remove SPI_OPM_RX_EXTN spi: Remove SPI_OPM_RX_DIO|QIOF spi: Rename SPI_OPM_RX_* to SPI_RX_* spi: Rename op_mode_rx to mode_rx spi: Move mode, mode_rx, flags macro's to structure spi: Fix bit assignment with flags spi: Use BIT macro spi: Minor cleanup drivers/mtd/spi/spi_flash.c | 2 +- drivers/spi/ich.c | 2 +- drivers/spi/ti_qspi.c | 2 +- include/spi.h | 65 +++++++++++++++++++-------------------------- 4 files changed, 31 insertions(+), 40 deletions(-) -- 1.9.1

3 24

[U-Boot] Fwd: [PATCH] Initial fw_cfg support for qemu-x86 targets.
by Saket Sinha 28 Dec '15

28 Dec '15

Hi Mian, This was the initial attempt to add fw_cfg interface support for qemu-x86 targets to mainly support ACPI tables. The patches were dropped due to the issues discussed in the thread. If we can collaborate the patches in the sense that we are able to load ACPI tables(and other tables) successfully, it would be great. Regards, Saket Sinha ---------- Forwarded message ---------- From: Bin Meng <bmeng.cn(a)gmail.com> Date: Fri, Jun 5, 2015 at 2:36 PM Subject: Re: [PATCH] Initial fw_cfg support for qemu-x86 targets. To: Saket Sinha <saket.sinha89(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Hi Saket, On Fri, Jun 5, 2015 at 4:50 PM, Saket Sinha <saket.sinha89(a)gmail.com> wrote: > Hi Bin, > >>> Error: Hardware did not enter ACPI mode >>> Unable to enable ACPI >>> Interpreter disabled. >>> >>> What can be the reason for these errors ? >> >> Sorry I have no idea. I think you have to read the whole ACPI >> specification to understand how the ACPI is used to be the interface >> between OS and the underlying hardware, and that's your primary GSoC >> job I believe :) >> > > Sure. I have been going through the ACPI specification. > Hope to find how to debug this error soon. > > Would it be reasonable to send this patch to mainline now, with the > present fw_cfg support that we have got working so far? > I would recommend we investigate the kernel ACPI error first and see what's going on there. Also I noticed that the QEMU fw_cfg ACPI table is huge (exactly 128KB). But lots of its memory space is just zero. I think this needs to be investigated. Also before sending patches to mainline, you need do some house keeping like fixing up all these camel case variables/structure names. > The next thing I am looking forward to is adding builtin ACPI support > for qemu targets in u-boot. > > If getting tables from fw_cfg fails, then all these ACPI tables would > be written. > Since it would fail for all non-qemu targets, this code snipet would > also apply for minnowboard and other x86 targets. > > Something like this - > fw = fw_cfg_acpi_tables(current); > if (fw) > return fw; > else > write_acpi_tables(current); Please follow the same way we write PIRQ/SFI tables. See arch/x86/Kconfig for a Kconfig option control. > I would deliberatley get it failed for qemu targets to see if builtin > ACPI table works. > Once these builtin table start working on qemu, it should work on > minnowmax too with little or no changes. > Regards, Bin

1 0

[U-Boot] U-Boot Device Driver Development Guide
by jerroldm＠blackmagicdesign.com 28 Dec '15

28 Dec '15

Dear Sir, I am considering using U-Boot as a software platform to bring up a hardware platform that am developing. In doing so, I may need to develop a couple of Device Drivers. I was wondering if anyone could point me to a document or a website that might help guide me to do this in the correction fashion. To be a bit more specific, I have a custom UHS-II SD Card Host Controller which I would like to access through FAT and EXFAT commands. I am using a Zynq FPGA as a platform. Thank you, Jerrold

3 2

[U-Boot] [PATCH V2 00/12] Series to move headers to a consistent include location
by Nishanth Menon 28 Dec '15

28 Dec '15

Hi, This series is hopefully to setup the stage for consolidation of board/vendor/common include header organization in u-boot. Discussion thread: https://patchwork.ozlabs.org/patch/540280/ https://patchwork.ozlabs.org/patch/541068/ https://patchwork.ozlabs.org/patch/542424/ In short, we: a) Dont want to have symlinks for include headers b) Want to be able to reference headers in reuse by doing #include <board-common/xyz.h> So, we follow the "option #6" discussed in the last of the threads above. Only the first patch in this series was pasted and discussed previously. The remaining 11 in the series is natural cleanups as a result. The series is Based on: master ade766acfb27 Merge branch 'next' of git://git.denx.de/u-boot-blackfin Script 1: identifying the board/vendors impacted: #!/bin/bash for common in `git grep "../common" board|grep "#include"|cut -d ':' -f1|cut -d '/' -f1,2|sort -u` do cfiles=`git grep "../common" $common|grep "#include"|cut -d '"' -f2|sort -u|grep c$` headers=`git grep "../common" $common|grep "#include"|cut -d '"' -f2|sort -u|grep h$` if [ -z "$headers" ]; then continue; fi echo $common : $headers : $cfiles done Output: board/BuR : ../common/bur_common.h : board/compulab : ../common/common.h ../common/eeprom.h : board/freescale : ../common/cadmus.h ../common/dcu_sii9022a.h ../common/diu_ch7301.h ../common/eeprom.h ../common/fman.h ../common/idt8t49n222a_serdes_clk.h ../common/ngpixis.h ../common/pfuze.h ../common/pixis.h ../common/pq-mds-pib.h ../common/qixis.h ../common/sgmii_riser.h ../common/sleep.h ../common/via.h ../common/vid.h ../common/vsc3316_3308.h ../common/zm7300.h : board/gdsys : ../common/dp501.h ../common/mclink.h ../common/osd.h ../common/phy.h : board/keymile : ../common/common.h : board/LaCie : ../common/common.h ../common/cpld-gpio-bus.h : board/mpl : ../common/common_util.h ../common/isa.h : board/seco : ../common/mx6.h : board/siemens : ../common/factoryset.h : ../common/board.c board/varisys : ../common/eeprom.h : board/xes : ../common/fsl_8xxx_misc.h : Script2: this is used to move the headers to relevant locations: #!/bin/bash vendor=$1 common=$vendor/common cfiles=`git grep "../common" $vendor|grep "#include"|cut -d '"' -f2|sort -u|grep c$` headers=`git grep "../common" $vendor|grep "#include"|cut -d '"' -f2|sort -u|grep h$` mkdir -p $common/include/board-common set -x for header in $headers do echo "processing $header in $common" hbase=`basename $header` git mv $common/$hbase $common/include/board-common sed -i -e "s/\"..\/common\/$hbase\"/<board-common\/$hbase>/g" $vendor/*/*.[chS] sed -i -e "s/\"$hbase\"/<board-common\/$hbase>/g" $vendor/common/*.[chS] done Build tested with the following with at least the ARM platforms: MAKEALL -v compulab -v BuR -v LaCie -v seco -v siemens NOTE: I know this series impacts a lot of platforms.. other than patch #1, they are probably nice to have.. but upto you guys if you'd like it or not.. it will be good to standardize things a bit here. I am *NOT* trying to fix the following code: $ git grep "\.\./common" board/*/*/*.[chS]|sort -u board/amcc/bamboo/flash.c:#include "../common/flash.c" board/amcc/bubinga/flash.c:#include "../common/flash.c" board/amcc/luan/flash.c:#include "../common/flash.c" board/amcc/walnut/flash.c:#include "../common/flash.c" board/esd/cpci2dp/flash.c:#include "../common/flash.c" board/esd/cpci405/cpci405.c:#include "../common/fpga.c" board/esd/cpci405/flash.c:#include "../common/flash.c" board/esd/plu405/flash.c:#include "../common/flash.c" board/esd/plu405/plu405.c:#include "../common/fpga.c" board/esd/vom405/flash.c:#include "../common/flash.c" board/siemens/draco/board.c:#include "../common/board.c" board/siemens/pxm2/board.c:#include "../common/board.c" board/siemens/rut/board.c:#include "../common/board.c" Nishanth Menon (12): Makefile: Include vendor common library in include search path board: BuR: Move common headers to board-common directory board: compulab: Move common headers to board-common directory board: freescale: Move common headers to board-common directory board: gdsys: Move common headers to board-common directory board: keymile: Move common headers to board-common directory board: LaCie: Move common headers to board-common directory board: mpl: Move common headers to board-common directory board: seco: Move common headers to board-common directory board: siemens: Move common headers to board-common directory board: varisys: Move common headers to board-common directory board: xes: Move common headers to board-common directory Makefile | 3 +++ board/BuR/common/common.c | 2 +- board/BuR/common/{ => include/board-common}/bur_common.h | 0 board/BuR/kwb/board.c | 2 +- board/BuR/tseries/board.c | 2 +- board/LaCie/common/cpld-gpio-bus.c | 2 +- board/LaCie/common/{ => include/board-common}/common.h | 0 board/LaCie/common/{ => include/board-common}/cpld-gpio-bus.h | 0 board/LaCie/edminiv2/edminiv2.c | 2 +- board/LaCie/net2big_v2/net2big_v2.c | 4 ++-- board/LaCie/netspace_v2/netspace_v2.c | 2 +- board/compulab/cm_fx6/cm_fx6.c | 4 ++-- board/compulab/cm_t335/cm_t335.c | 2 +- board/compulab/cm_t35/cm_t35.c | 4 ++-- board/compulab/cm_t3517/cm_t3517.c | 4 ++-- board/compulab/cm_t54/cm_t54.c | 2 +- board/compulab/common/common.c | 4 ++-- board/compulab/common/eeprom.c | 2 +- board/compulab/common/{ => include/board-common}/common.h | 0 board/compulab/common/{ => include/board-common}/eeprom.h | 0 board/compulab/common/omap3_smc911x.c | 2 +- board/freescale/b4860qds/b4860qds.c | 8 ++++---- board/freescale/b4860qds/eth_b4860qds.c | 6 +++--- board/freescale/b4860qds/spl.c | 2 +- board/freescale/bsc9132qds/bsc9132qds.c | 2 +- board/freescale/common/arm_sleep.c | 2 +- board/freescale/common/cds_pci_ft.c | 2 +- board/freescale/common/ics307_clk.c | 6 +++--- board/freescale/common/idt8t49n222a_serdes_clk.c | 2 +- board/freescale/common/{ => include/board-common}/cadmus.h | 0 board/freescale/common/{ => include/board-common}/dcu_sii9022a.h | 0 board/freescale/common/{ => include/board-common}/diu_ch7301.h | 0 board/freescale/common/{ => include/board-common}/eeprom.h | 0 board/freescale/common/{ => include/board-common}/fman.h | 0 .../common/{ => include/board-common}/idt8t49n222a_serdes_clk.h | 0 board/freescale/common/{ => include/board-common}/ngpixis.h | 0 board/freescale/common/{ => include/board-common}/pfuze.h | 0 board/freescale/common/{ => include/board-common}/pixis.h | 0 board/freescale/common/{ => include/board-common}/pq-mds-pib.h | 0 board/freescale/common/{ => include/board-common}/qixis.h | 0 board/freescale/common/{ => include/board-common}/sgmii_riser.h | 0 board/freescale/common/{ => include/board-common}/sleep.h | 0 board/freescale/common/{ => include/board-common}/via.h | 0 board/freescale/common/{ => include/board-common}/vid.h | 0 board/freescale/common/{ => include/board-common}/vsc3316_3308.h | 0 board/freescale/common/{ => include/board-common}/zm7300.h | 0 board/freescale/common/mpc85xx_sleep.c | 2 +- board/freescale/common/ngpixis.c | 2 +- board/freescale/common/pq-mds-pib.c | 2 +- board/freescale/common/qixis.c | 2 +- board/freescale/common/sys_eeprom.c | 2 +- board/freescale/common/vid.c | 2 +- board/freescale/common/vsc3316_3308.c | 2 +- board/freescale/common/zm7300.c | 2 +- board/freescale/corenet_ds/corenet_ds.c | 2 +- board/freescale/corenet_ds/eth_hydra.c | 4 ++-- board/freescale/corenet_ds/eth_p4080.c | 4 ++-- board/freescale/corenet_ds/eth_superhydra.c | 4 ++-- board/freescale/ls1021aqds/dcu.c | 2 +- board/freescale/ls1021aqds/eth.c | 4 ++-- board/freescale/ls1021aqds/ls1021aqds.c | 4 ++-- board/freescale/ls1021atwr/dcu.c | 2 +- board/freescale/ls1021atwr/ls1021atwr.c | 2 +- board/freescale/ls1043ardb/eth.c | 2 +- board/freescale/ls2085aqds/eth.c | 2 +- board/freescale/ls2085aqds/ls2085aqds.c | 2 +- board/freescale/ls2085ardb/ls2085ardb.c | 2 +- board/freescale/mpc832xemds/mpc832xemds.c | 2 +- board/freescale/mpc832xemds/pci.c | 2 +- board/freescale/mpc837xemds/mpc837xemds.c | 2 +- board/freescale/mpc8536ds/mpc8536ds.c | 2 +- board/freescale/mpc8541cds/mpc8541cds.c | 6 +++--- board/freescale/mpc8544ds/mpc8544ds.c | 2 +- board/freescale/mpc8548cds/mpc8548cds.c | 6 +++--- board/freescale/mpc8555cds/mpc8555cds.c | 6 +++--- board/freescale/mpc8569mds/mpc8569mds.c | 2 +- board/freescale/mpc8572ds/mpc8572ds.c | 2 +- board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c | 2 +- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 2 +- board/freescale/mx6sabresd/mx6sabresd.c | 2 +- board/freescale/mx6slevk/mx6slevk.c | 2 +- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +- board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 2 +- board/freescale/mx7dsabresd/mx7dsabresd.c | 2 +- board/freescale/p1022ds/diu.c | 2 +- board/freescale/p1022ds/p1022ds.c | 2 +- board/freescale/p1022ds/spl.c | 2 +- board/freescale/p2041rdb/eth.c | 2 +- board/freescale/t102xqds/eth_t102xqds.c | 4 ++-- board/freescale/t102xqds/spl.c | 2 +- board/freescale/t102xqds/t102xqds.c | 4 ++-- board/freescale/t102xrdb/eth_t102xrdb.c | 2 +- board/freescale/t102xrdb/spl.c | 2 +- board/freescale/t102xrdb/t102xrdb.c | 2 +- board/freescale/t1040qds/diu.c | 4 ++-- board/freescale/t1040qds/eth.c | 4 ++-- board/freescale/t1040qds/t1040qds.c | 4 ++-- board/freescale/t104xrdb/diu.c | 2 +- board/freescale/t104xrdb/eth.c | 2 +- board/freescale/t104xrdb/spl.c | 2 +- board/freescale/t104xrdb/t104xrdb.c | 2 +- board/freescale/t208xqds/eth_t208xqds.c | 4 ++-- board/freescale/t208xqds/spl.c | 2 +- board/freescale/t208xqds/t208xqds.c | 6 +++--- board/freescale/t208xrdb/t208xrdb.c | 2 +- board/freescale/t4qds/eth.c | 4 ++-- board/freescale/t4qds/spl.c | 2 +- board/freescale/t4qds/t4240qds.c | 4 ++-- board/freescale/t4rdb/eth.c | 2 +- board/gdsys/405ep/dlvision-10g.c | 2 +- board/gdsys/405ep/iocon.c | 6 +++--- board/gdsys/common/{ => include/board-common}/dp501.h | 0 board/gdsys/common/{ => include/board-common}/mclink.h | 0 board/gdsys/common/{ => include/board-common}/osd.h | 0 board/gdsys/common/{ => include/board-common}/phy.h | 0 board/gdsys/common/osd.c | 2 +- board/gdsys/mpc8308/hrcon.c | 6 +++--- board/gdsys/p1022/controlcenterd.c | 2 +- board/keymile/common/common.c | 2 +- board/keymile/common/{ => include/board-common}/common.h | 0 board/keymile/common/ivm.c | 2 +- board/keymile/km82xx/km82xx.c | 2 +- board/keymile/km83xx/km83xx.c | 2 +- board/keymile/km83xx/km83xx_i2c.c | 2 +- board/keymile/km_arm/km_arm.c | 2 +- board/keymile/kmp204x/kmp204x.c | 2 +- board/keymile/kmp204x/qrio.c | 2 +- board/mpl/common/common_util.c | 2 +- board/mpl/common/{ => include/board-common}/common_util.h | 0 board/mpl/common/{ => include/board-common}/isa.h | 0 board/mpl/common/isa.c | 2 +- board/mpl/common/kbd.c | 2 +- board/mpl/common/pci.c | 2 +- board/mpl/mip405/cmd_mip405.c | 2 +- board/mpl/mip405/mip405.c | 2 +- board/mpl/pip405/cmd_pip405.c | 2 +- board/mpl/pip405/pip405.c | 4 ++-- board/mpl/vcma9/cmd_vcma9.c | 2 +- board/mpl/vcma9/vcma9.c | 2 +- board/seco/common/{ => include/board-common}/mx6.h | 0 board/seco/mx6quq7/mx6quq7.c | 2 +- board/siemens/common/board.c | 2 +- board/siemens/common/factoryset.c | 2 +- board/siemens/common/{ => include/board-common}/factoryset.h | 0 board/siemens/draco/board.c | 2 +- board/siemens/pxm2/board.c | 2 +- board/siemens/rut/board.c | 2 +- board/varisys/common/{ => include/board-common}/eeprom.h | 0 board/varisys/common/sys_eeprom.c | 2 +- board/varisys/cyrus/cyrus.c | 2 +- board/xes/common/board.c | 2 +- board/xes/common/{ => include/board-common}/fsl_8xxx_misc.h | 0 board/xes/xpedite517x/xpedite517x.c | 2 +- 153 files changed, 160 insertions(+), 157 deletions(-) rename board/BuR/common/{ => include/board-common}/bur_common.h (100%) rename board/LaCie/common/{ => include/board-common}/common.h (100%) rename board/LaCie/common/{ => include/board-common}/cpld-gpio-bus.h (100%) rename board/compulab/common/{ => include/board-common}/common.h (100%) rename board/compulab/common/{ => include/board-common}/eeprom.h (100%) rename board/freescale/common/{ => include/board-common}/cadmus.h (100%) rename board/freescale/common/{ => include/board-common}/dcu_sii9022a.h (100%) rename board/freescale/common/{ => include/board-common}/diu_ch7301.h (100%) rename board/freescale/common/{ => include/board-common}/eeprom.h (100%) rename board/freescale/common/{ => include/board-common}/fman.h (100%) rename board/freescale/common/{ => include/board-common}/idt8t49n222a_serdes_clk.h (100%) rename board/freescale/common/{ => include/board-common}/ngpixis.h (100%) rename board/freescale/common/{ => include/board-common}/pfuze.h (100%) rename board/freescale/common/{ => include/board-common}/pixis.h (100%) rename board/freescale/common/{ => include/board-common}/pq-mds-pib.h (100%) rename board/freescale/common/{ => include/board-common}/qixis.h (100%) rename board/freescale/common/{ => include/board-common}/sgmii_riser.h (100%) rename board/freescale/common/{ => include/board-common}/sleep.h (100%) rename board/freescale/common/{ => include/board-common}/via.h (100%) rename board/freescale/common/{ => include/board-common}/vid.h (100%) rename board/freescale/common/{ => include/board-common}/vsc3316_3308.h (100%) rename board/freescale/common/{ => include/board-common}/zm7300.h (100%) rename board/gdsys/common/{ => include/board-common}/dp501.h (100%) rename board/gdsys/common/{ => include/board-common}/mclink.h (100%) rename board/gdsys/common/{ => include/board-common}/osd.h (100%) rename board/gdsys/common/{ => include/board-common}/phy.h (100%) rename board/keymile/common/{ => include/board-common}/common.h (100%) rename board/mpl/common/{ => include/board-common}/common_util.h (100%) rename board/mpl/common/{ => include/board-common}/isa.h (100%) rename board/seco/common/{ => include/board-common}/mx6.h (100%) rename board/siemens/common/{ => include/board-common}/factoryset.h (100%) rename board/varisys/common/{ => include/board-common}/eeprom.h (100%) rename board/xes/common/{ => include/board-common}/fsl_8xxx_misc.h (100%) -- 2.6.2.402.g2635c2b

11 34

[U-Boot] Please pull u-boot-sunxi master (v2016.01 bugfix)
by Hans de Goede 27 Dec '15

27 Dec '15

Hi Tom, Here is a sunxi pull-req with a small bugfix for v2016.01: The following changes since commit f84c2b665b87fc6713a756d0fddf5c45e02255e5: Prepare v2016.01-rc3 (2015-12-21 21:07:04 -0500) are available in the git repository at: http://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to e7d6aa0b74b7f4d08ee68da8a586c76c761348e2: sunxi: Reduce Orangepi PC RAM speed to 624 MHz (2015-12-27 12:30:39 +0100) ---------------------------------------------------------------- Hans de Goede (1): sunxi: Reduce Orangepi PC RAM speed to 624 MHz configs/orangepi_pc_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Regards, Hans

2 1